arch/arm/dts/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         soc {
  17                 usb: usb@d0078080 {
  18                         compatible = "amlogic,meson-gxl-usb-ctrl";
  19                         reg = <0x0 0xd0078080 0x0 0x20>;
  20                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  21                         #address-cells = <2>;
  22                         #size-cells = <2>;
  23                         ranges;
  24
  25                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
  26                         clock-names = "usb_ctrl", "ddr";
  27                         resets = <&reset RESET_USB_OTG>;
  28
  29                         dr_mode = "otg";
  30
  31                         phys = <&usb2_phy0>, <&usb2_phy1>;
  32                         phy-names = "usb2-phy0", "usb2-phy1";
  33
  34                         dwc2: usb@c9100000 {
  35                                 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
  36                                 reg = <0x0 0xc9100000 0x0 0x40000>;
  37                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  38                                 clocks = <&clkc CLKID_USB1>;
  39                                 clock-names = "otg";
  40                                 phys = <&usb2_phy1>;
  41                                 dr_mode = "peripheral";
  42                                 g-rx-fifo-size = <192>;
  43                                 g-np-tx-fifo-size = <128>;
  44                                 g-tx-fifo-size = <128 128 16 16 16>;
  45                         };
  46
  47                         dwc3: usb@c9000000 {
  48                                 compatible = "snps,dwc3";
  49                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  50                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  51                                 dr_mode = "host";
  52                                 maximum-speed = "high-speed";
  53                                 snps,dis_u2_susphy_quirk;
  54                         };
  55                 };
  56
  57                 acodec: audio-controller@c8832000 {
  58                         compatible = "amlogic,t9015";
  59                         reg = <0x0 0xc8832000 0x0 0x14>;
  60                         #sound-dai-cells = <0>;
  61                         sound-name-prefix = "ACODEC";
  62                         clocks = <&clkc CLKID_ACODEC>;
  63                         clock-names = "pclk";
  64                         resets = <&reset RESET_ACODEC>;
  65                         status = "disabled";
  66                 };
  67
  68                 crypto: crypto@c883e000 {
  69                         compatible = "amlogic,gxl-crypto";
  70                         reg = <0x0 0xc883e000 0x0 0x36>;
  71                         interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
  72                                      <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  73                         clocks = <&clkc CLKID_BLKMV>;
  74                         clock-names = "blkmv";
  75                         status = "okay";
  76                 };
  77         };
  78 };
  79
  80 &aiu {
  81         compatible = "amlogic,aiu-gxl", "amlogic,aiu";
  82         clocks = <&clkc CLKID_AIU_GLUE>,
  83                  <&clkc CLKID_I2S_OUT>,
  84                  <&clkc CLKID_AOCLK_GATE>,
  85                  <&clkc CLKID_CTS_AMCLK>,
  86                  <&clkc CLKID_MIXER_IFACE>,
  87                  <&clkc CLKID_IEC958>,
  88                  <&clkc CLKID_IEC958_GATE>,
  89                  <&clkc CLKID_CTS_MCLK_I958>,
  90                  <&clkc CLKID_CTS_I958>;
  91         clock-names = "pclk",
  92                       "i2s_pclk",
  93                       "i2s_aoclk",
  94                       "i2s_mclk",
  95                       "i2s_mixer",
  96                       "spdif_pclk",
  97                       "spdif_aoclk",
  98                       "spdif_mclk",
  99                       "spdif_mclk_sel";
 100         resets = <&reset RESET_AIU>;
 101 };
 102
 103 &apb {
 104         usb2_phy0: phy@78000 {
 105                 compatible = "amlogic,meson-gxl-usb2-phy";
 106                 #phy-cells = <0>;
 107                 reg = <0x0 0x78000 0x0 0x20>;
 108                 clocks = <&clkc CLKID_USB>;
 109                 clock-names = "phy";
 110                 resets = <&reset RESET_USB_OTG>;
 111                 reset-names = "phy";
 112                 status = "okay";
 113         };
 114
 115         usb2_phy1: phy@78020 {
 116                 compatible = "amlogic,meson-gxl-usb2-phy";
 117                 #phy-cells = <0>;
 118                 reg = <0x0 0x78020 0x0 0x20>;
 119                 clocks = <&clkc CLKID_USB>;
 120                 clock-names = "phy";
 121                 resets = <&reset RESET_USB_OTG>;
 122                 reset-names = "phy";
 123                 status = "okay";
 124         };
 125 };
 126
 127 &efuse {
 128         clocks = <&clkc CLKID_EFUSE>;
 129 };
 130
 131 &ethmac {
 132         clocks = <&clkc CLKID_ETH>,
 133                  <&clkc CLKID_FCLK_DIV2>,
 134                  <&clkc CLKID_MPLL2>;
 135         clock-names = "stmmaceth", "clkin0", "clkin1";
 136
 137         mdio0: mdio {
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140                 compatible = "snps,dwmac-mdio";
 141         };
 142 };
 143
 144 &aobus {
 145         pinctrl_aobus: pinctrl@14 {
 146                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
 147                 #address-cells = <2>;
 148                 #size-cells = <2>;
 149                 ranges;
 150
 151                 gpio_ao: bank@14 {
 152                         reg = <0x0 0x00014 0x0 0x8>,
 153                               <0x0 0x0002c 0x0 0x4>,
 154                               <0x0 0x00024 0x0 0x8>;
 155                         reg-names = "mux", "pull", "gpio";
 156                         gpio-controller;
 157                         #gpio-cells = <2>;
 158                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 159                 };
 160
 161                 uart_ao_a_pins: uart_ao_a {
 162                         mux {
 163                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 164                                 function = "uart_ao";
 165                                 bias-disable;
 166                         };
 167                 };
 168
 169                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 170                         mux {
 171                                 groups = "uart_cts_ao_a",
 172                                        "uart_rts_ao_a";
 173                                 function = "uart_ao";
 174                                 bias-disable;
 175                         };
 176                 };
 177
 178                 uart_ao_b_pins: uart_ao_b {
 179                         mux {
 180                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 181                                 function = "uart_ao_b";
 182                                 bias-disable;
 183                         };
 184                 };
 185
 186                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 187                         mux {
 188                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 189                                 function = "uart_ao_b";
 190                                 bias-disable;
 191                         };
 192                 };
 193
 194                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 195                         mux {
 196                                 groups = "uart_cts_ao_b",
 197                                        "uart_rts_ao_b";
 198                                 function = "uart_ao_b";
 199                                 bias-disable;
 200                         };
 201                 };
 202
 203                 remote_input_ao_pins: remote_input_ao {
 204                         mux {
 205                                 groups = "remote_input_ao";
 206                                 function = "remote_input_ao";
 207                                 bias-disable;
 208                         };
 209                 };
 210
 211                 i2c_ao_pins: i2c_ao {
 212                         mux {
 213                                 groups = "i2c_sck_ao",
 214                                        "i2c_sda_ao";
 215                                 function = "i2c_ao";
 216                                 bias-disable;
 217                         };
 218                 };
 219
 220                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 221                         mux {
 222                                 groups = "pwm_ao_a_3";
 223                                 function = "pwm_ao_a";
 224                                 bias-disable;
 225                         };
 226                 };
 227
 228                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 229                         mux {
 230                                 groups = "pwm_ao_a_8";
 231                                 function = "pwm_ao_a";
 232                                 bias-disable;
 233                         };
 234                 };
 235
 236                 pwm_ao_b_pins: pwm_ao_b {
 237                         mux {
 238                                 groups = "pwm_ao_b";
 239                                 function = "pwm_ao_b";
 240                                 bias-disable;
 241                         };
 242                 };
 243
 244                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 245                         mux {
 246                                 groups = "pwm_ao_b_6";
 247                                 function = "pwm_ao_b";
 248                                 bias-disable;
 249                         };
 250                 };
 251
 252                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 253                         mux {
 254                                 groups = "i2s_out_ch23_ao";
 255                                 function = "i2s_out_ao";
 256                                 bias-disable;
 257                         };
 258                 };
 259
 260                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 261                         mux {
 262                                 groups = "i2s_out_ch45_ao";
 263                                 function = "i2s_out_ao";
 264                                 bias-disable;
 265                         };
 266                 };
 267
 268                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 269                         mux {
 270                                 groups = "spdif_out_ao_6";
 271                                 function = "spdif_out_ao";
 272                                 bias-disable;
 273                         };
 274                 };
 275
 276                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 277                         mux {
 278                                 groups = "spdif_out_ao_9";
 279                                 function = "spdif_out_ao";
 280                                 bias-disable;
 281                         };
 282                 };
 283
 284                 ao_cec_pins: ao_cec {
 285                         mux {
 286                                 groups = "ao_cec";
 287                                 function = "cec_ao";
 288                                 bias-disable;
 289                         };
 290                 };
 291
 292                 ee_cec_pins: ee_cec {
 293                         mux {
 294                                 groups = "ee_cec";
 295                                 function = "cec_ao";
 296                                 bias-disable;
 297                         };
 298                 };
 299         };
 300 };
 301
 302 &cec_AO {
 303         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 304         clock-names = "core";
 305 };
 306
 307 &clkc_AO {
 308         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 309         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 310         clock-names = "xtal", "mpeg-clk";
 311 };
 312
 313 &gpio_intc {
 314         compatible = "amlogic,meson-gpio-intc",
 315                      "amlogic,meson-gxl-gpio-intc";
 316         status = "okay";
 317 };
 318
 319 &hdmi_tx {
 320         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 321         resets = <&reset RESET_HDMITX_CAPB3>,
 322                  <&reset RESET_HDMI_SYSTEM_RESET>,
 323                  <&reset RESET_HDMI_TX>;
 324         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 325         clocks = <&clkc CLKID_HDMI_PCLK>,
 326                  <&clkc CLKID_CLK81>,
 327                  <&clkc CLKID_GCLK_VENCI_INT0>;
 328         clock-names = "isfr", "iahb", "venci";
 329 };
 330
 331 &sysctrl {
 332         clkc: clock-controller {
 333                 compatible = "amlogic,gxl-clkc";
 334                 #clock-cells = <1>;
 335                 clocks = <&xtal>;
 336                 clock-names = "xtal";
 337         };
 338 };
 339
 340 &i2c_A {
 341         clocks = <&clkc CLKID_I2C>;
 342 };
 343
 344 &i2c_AO {
 345         clocks = <&clkc CLKID_AO_I2C>;
 346 };
 347
 348 &i2c_B {
 349         clocks = <&clkc CLKID_I2C>;
 350 };
 351
 352 &i2c_C {
 353         clocks = <&clkc CLKID_I2C>;
 354 };
 355
 356 &periphs {
 357         pinctrl_periphs: pinctrl@4b0 {
 358                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 359                 #address-cells = <2>;
 360                 #size-cells = <2>;
 361                 ranges;
 362
 363                 gpio: bank@4b0 {
 364                         reg = <0x0 0x004b0 0x0 0x28>,
 365                               <0x0 0x004e8 0x0 0x14>,
 366                               <0x0 0x00520 0x0 0x14>,
 367                               <0x0 0x00430 0x0 0x40>;
 368                         reg-names = "mux", "pull", "pull-enable", "gpio";
 369                         gpio-controller;
 370                         #gpio-cells = <2>;
 371                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 372                 };
 373
 374                 emmc_pins: emmc {
 375                         mux-0 {
 376                                 groups = "emmc_nand_d07",
 377                                        "emmc_cmd";
 378                                 function = "emmc";
 379                                 bias-pull-up;
 380                         };
 381
 382                         mux-1 {
 383                                 groups = "emmc_clk";
 384                                 function = "emmc";
 385                                 bias-disable;
 386                         };
 387                 };
 388
 389                 emmc_ds_pins: emmc-ds {
 390                         mux {
 391                                 groups = "emmc_ds";
 392                                 function = "emmc";
 393                                 bias-pull-down;
 394                         };
 395                 };
 396
 397                 emmc_clk_gate_pins: emmc_clk_gate {
 398                         mux {
 399                                 groups = "BOOT_8";
 400                                 function = "gpio_periphs";
 401                                 bias-pull-down;
 402                         };
 403                 };
 404
 405                 nor_pins: nor {
 406                         mux {
 407                                 groups = "nor_d",
 408                                        "nor_q",
 409                                        "nor_c",
 410                                        "nor_cs";
 411                                 function = "nor";
 412                                 bias-disable;
 413                         };
 414                 };
 415
 416                 spi_pins: spi-pins {
 417                         mux {
 418                                 groups = "spi_miso",
 419                                         "spi_mosi",
 420                                         "spi_sclk";
 421                                 function = "spi";
 422                                 bias-disable;
 423                         };
 424                 };
 425
 426                 spi_ss0_pins: spi-ss0 {
 427                         mux {
 428                                 groups = "spi_ss0";
 429                                 function = "spi";
 430                                 bias-disable;
 431                         };
 432                 };
 433
 434                 sdcard_pins: sdcard {
 435                         mux-0 {
 436                                 groups = "sdcard_d0",
 437                                        "sdcard_d1",
 438                                        "sdcard_d2",
 439                                        "sdcard_d3",
 440                                        "sdcard_cmd";
 441                                 function = "sdcard";
 442                                 bias-pull-up;
 443                         };
 444
 445                         mux-1 {
 446                                 groups = "sdcard_clk";
 447                                 function = "sdcard";
 448                                 bias-disable;
 449                         };
 450                 };
 451
 452                 sdcard_clk_gate_pins: sdcard_clk_gate {
 453                         mux {
 454                                 groups = "CARD_2";
 455                                 function = "gpio_periphs";
 456                                 bias-pull-down;
 457                         };
 458                 };
 459
 460                 sdio_pins: sdio {
 461                         mux-0 {
 462                                 groups = "sdio_d0",
 463                                        "sdio_d1",
 464                                        "sdio_d2",
 465                                        "sdio_d3",
 466                                        "sdio_cmd";
 467                                 function = "sdio";
 468                                 bias-pull-up;
 469                         };
 470
 471                         mux-1 {
 472                                 groups = "sdio_clk";
 473                                 function = "sdio";
 474                                 bias-disable;
 475                         };
 476                 };
 477
 478                 sdio_clk_gate_pins: sdio_clk_gate {
 479                         mux {
 480                                 groups = "GPIOX_4";
 481                                 function = "gpio_periphs";
 482                                 bias-pull-down;
 483                         };
 484                 };
 485
 486                 sdio_irq_pins: sdio_irq {
 487                         mux {
 488                                 groups = "sdio_irq";
 489                                 function = "sdio";
 490                                 bias-disable;
 491                         };
 492                 };
 493
 494                 uart_a_pins: uart_a {
 495                         mux {
 496                                 groups = "uart_tx_a",
 497                                        "uart_rx_a";
 498                                 function = "uart_a";
 499                                 bias-disable;
 500                         };
 501                 };
 502
 503                 uart_a_cts_rts_pins: uart_a_cts_rts {
 504                         mux {
 505                                 groups = "uart_cts_a",
 506                                        "uart_rts_a";
 507                                 function = "uart_a";
 508                                 bias-disable;
 509                         };
 510                 };
 511
 512                 uart_b_pins: uart_b {
 513                         mux {
 514                                 groups = "uart_tx_b",
 515                                        "uart_rx_b";
 516                                 function = "uart_b";
 517                                 bias-disable;
 518                         };
 519                 };
 520
 521                 uart_b_cts_rts_pins: uart_b_cts_rts {
 522                         mux {
 523                                 groups = "uart_cts_b",
 524                                        "uart_rts_b";
 525                                 function = "uart_b";
 526                                 bias-disable;
 527                         };
 528                 };
 529
 530                 uart_c_pins: uart_c {
 531                         mux {
 532                                 groups = "uart_tx_c",
 533                                        "uart_rx_c";
 534                                 function = "uart_c";
 535                                 bias-disable;
 536                         };
 537                 };
 538
 539                 uart_c_cts_rts_pins: uart_c_cts_rts {
 540                         mux {
 541                                 groups = "uart_cts_c",
 542                                        "uart_rts_c";
 543                                 function = "uart_c";
 544                                 bias-disable;
 545                         };
 546                 };
 547
 548                 i2c_a_pins: i2c_a {
 549                         mux {
 550                                 groups = "i2c_sck_a",
 551                                      "i2c_sda_a";
 552                                 function = "i2c_a";
 553                                 bias-disable;
 554                         };
 555                 };
 556
 557                 i2c_b_pins: i2c_b {
 558                         mux {
 559                                 groups = "i2c_sck_b",
 560                                       "i2c_sda_b";
 561                                 function = "i2c_b";
 562                                 bias-disable;
 563                         };
 564                 };
 565
 566                 i2c_c_pins: i2c_c {
 567                         mux {
 568                                 groups = "i2c_sck_c",
 569                                       "i2c_sda_c";
 570                                 function = "i2c_c";
 571                                 bias-disable;
 572                         };
 573                 };
 574
 575                 i2c_c_dv18_pins: i2c_c_dv18 {
 576                         mux {
 577                                 groups = "i2c_sck_c_dv19",
 578                                       "i2c_sda_c_dv18";
 579                                 function = "i2c_c";
 580                                 bias-disable;
 581                         };
 582                 };
 583
 584                 eth_pins: eth_c {
 585                         mux {
 586                                 groups = "eth_mdio",
 587                                        "eth_mdc",
 588                                        "eth_clk_rx_clk",
 589                                        "eth_rx_dv",
 590                                        "eth_rxd0",
 591                                        "eth_rxd1",
 592                                        "eth_rxd2",
 593                                        "eth_rxd3",
 594                                        "eth_rgmii_tx_clk",
 595                                        "eth_tx_en",
 596                                        "eth_txd0",
 597                                        "eth_txd1",
 598                                        "eth_txd2",
 599                                        "eth_txd3";
 600                                 function = "eth";
 601                                 bias-disable;
 602                         };
 603                 };
 604
 605                 eth_link_led_pins: eth_link_led {
 606                         mux {
 607                                 groups = "eth_link_led";
 608                                 function = "eth_led";
 609                                 bias-disable;
 610                         };
 611                 };
 612
 613                 eth_act_led_pins: eth_act_led {
 614                         mux {
 615                                 groups = "eth_act_led";
 616                                 function = "eth_led";
 617                         };
 618                 };
 619
 620                 pwm_a_pins: pwm_a {
 621                         mux {
 622                                 groups = "pwm_a";
 623                                 function = "pwm_a";
 624                                 bias-disable;
 625                         };
 626                 };
 627
 628                 pwm_b_pins: pwm_b {
 629                         mux {
 630                                 groups = "pwm_b";
 631                                 function = "pwm_b";
 632                                 bias-disable;
 633                         };
 634                 };
 635
 636                 pwm_c_pins: pwm_c {
 637                         mux {
 638                                 groups = "pwm_c";
 639                                 function = "pwm_c";
 640                                 bias-disable;
 641                         };
 642                 };
 643
 644                 pwm_d_pins: pwm_d {
 645                         mux {
 646                                 groups = "pwm_d";
 647                                 function = "pwm_d";
 648                                 bias-disable;
 649                         };
 650                 };
 651
 652                 pwm_e_pins: pwm_e {
 653                         mux {
 654                                 groups = "pwm_e";
 655                                 function = "pwm_e";
 656                                 bias-disable;
 657                         };
 658                 };
 659
 660                 pwm_f_clk_pins: pwm_f_clk {
 661                         mux {
 662                                 groups = "pwm_f_clk";
 663                                 function = "pwm_f";
 664                                 bias-disable;
 665                         };
 666                 };
 667
 668                 pwm_f_x_pins: pwm_f_x {
 669                         mux {
 670                                 groups = "pwm_f_x";
 671                                 function = "pwm_f";
 672                                 bias-disable;
 673                         };
 674                 };
 675
 676                 hdmi_hpd_pins: hdmi_hpd {
 677                         mux {
 678                                 groups = "hdmi_hpd";
 679                                 function = "hdmi_hpd";
 680                                 bias-disable;
 681                         };
 682                 };
 683
 684                 hdmi_i2c_pins: hdmi_i2c {
 685                         mux {
 686                                 groups = "hdmi_sda", "hdmi_scl";
 687                                 function = "hdmi_i2c";
 688                                 bias-disable;
 689                         };
 690                 };
 691
 692                 i2s_am_clk_pins: i2s_am_clk {
 693                         mux {
 694                                 groups = "i2s_am_clk";
 695                                 function = "i2s_out";
 696                                 bias-disable;
 697                         };
 698                 };
 699
 700                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 701                         mux {
 702                                 groups = "i2s_out_ao_clk";
 703                                 function = "i2s_out";
 704                                 bias-disable;
 705                         };
 706                 };
 707
 708                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 709                         mux {
 710                                 groups = "i2s_out_lr_clk";
 711                                 function = "i2s_out";
 712                                 bias-disable;
 713                         };
 714                 };
 715
 716                 i2s_out_ch01_pins: i2s_out_ch01 {
 717                         mux {
 718                                 groups = "i2s_out_ch01";
 719                                 function = "i2s_out";
 720                                 bias-disable;
 721                         };
 722                 };
 723                 i2sout_ch23_z_pins: i2sout_ch23_z {
 724                         mux {
 725                                 groups = "i2sout_ch23_z";
 726                                 function = "i2s_out";
 727                                 bias-disable;
 728                         };
 729                 };
 730
 731                 i2sout_ch45_z_pins: i2sout_ch45_z {
 732                         mux {
 733                                 groups = "i2sout_ch45_z";
 734                                 function = "i2s_out";
 735                                 bias-disable;
 736                         };
 737                 };
 738
 739                 i2sout_ch67_z_pins: i2sout_ch67_z {
 740                         mux {
 741                                 groups = "i2sout_ch67_z";
 742                                 function = "i2s_out";
 743                                 bias-disable;
 744                         };
 745                 };
 746
 747                 spdif_out_h_pins: spdif_out_ao_h {
 748                         mux {
 749                                 groups = "spdif_out_h";
 750                                 function = "spdif_out";
 751                                 bias-disable;
 752                         };
 753                 };
 754         };
 755
 756         eth-phy-mux {
 757                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 758                 #address-cells = <1>;
 759                 #size-cells = <0>;
 760                 reg = <0x0 0x55c 0x0 0x4>;
 761                 mux-mask = <0xffffffff>;
 762                 mdio-parent-bus = <&mdio0>;
 763
 764                 internal_mdio: mdio@e40908ff {
 765                         reg = <0xe40908ff>;
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768
 769                         internal_phy: ethernet-phy@8 {
 770                                 compatible = "ethernet-phy-id0181.4400";
 771                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 772                                 reg = <8>;
 773                                 max-speed = <100>;
 774                         };
 775                 };
 776
 777                 external_mdio: mdio@2009087f {
 778                         reg = <0x2009087f>;
 779                         #address-cells = <1>;
 780                         #size-cells = <0>;
 781                 };
 782         };
 783 };
 784
 785 &pwrc_vpu {
 786         resets = <&reset RESET_VIU>,
 787                  <&reset RESET_VENC>,
 788                  <&reset RESET_VCBUS>,
 789                  <&reset RESET_BT656>,
 790                  <&reset RESET_DVIN_RESET>,
 791                  <&reset RESET_RDMA>,
 792                  <&reset RESET_VENCI>,
 793                  <&reset RESET_VENCP>,
 794                  <&reset RESET_VDAC>,
 795                  <&reset RESET_VDI6>,
 796                  <&reset RESET_VENCL>,
 797                  <&reset RESET_VID_LOCK>;
 798         clocks = <&clkc CLKID_VPU>,
 799                  <&clkc CLKID_VAPB>;
 800         clock-names = "vpu", "vapb";
 801         /*
 802          * VPU clocking is provided by two identical clock paths
 803          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 804          * free mux to safely change frequency while running.
 805          * Same for VAPB but with a final gate after the glitch free mux.
 806          */
 807         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 808                           <&clkc CLKID_VPU_0>,
 809                           <&clkc CLKID_VPU>, /* Glitch free mux */
 810                           <&clkc CLKID_VAPB_0_SEL>,
 811                           <&clkc CLKID_VAPB_0>,
 812                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 813         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 814                                  <0>, /* Do Nothing */
 815                                  <&clkc CLKID_VPU_0>,
 816                                  <&clkc CLKID_FCLK_DIV4>,
 817                                  <0>, /* Do Nothing */
 818                                  <&clkc CLKID_VAPB_0>;
 819         assigned-clock-rates = <0>, /* Do Nothing */
 820                                <666666666>,
 821                                <0>, /* Do Nothing */
 822                                <0>, /* Do Nothing */
 823                                <250000000>,
 824                                <0>; /* Do Nothing */
 825 };
 826
 827 &saradc {
 828         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 829         clocks = <&xtal>,
 830                  <&clkc CLKID_SAR_ADC>,
 831                  <&clkc CLKID_SAR_ADC_CLK>,
 832                  <&clkc CLKID_SAR_ADC_SEL>;
 833         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 834 };
 835
 836 &sd_emmc_a {
 837         clocks = <&clkc CLKID_SD_EMMC_A>,
 838                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 839                  <&clkc CLKID_FCLK_DIV2>;
 840         clock-names = "core", "clkin0", "clkin1";
 841         resets = <&reset RESET_SD_EMMC_A>;
 842 };
 843
 844 &sd_emmc_b {
 845         clocks = <&clkc CLKID_SD_EMMC_B>,
 846                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 847                  <&clkc CLKID_FCLK_DIV2>;
 848         clock-names = "core", "clkin0", "clkin1";
 849         resets = <&reset RESET_SD_EMMC_B>;
 850 };
 851
 852 &sd_emmc_c {
 853         clocks = <&clkc CLKID_SD_EMMC_C>,
 854                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 855                  <&clkc CLKID_FCLK_DIV2>;
 856         clock-names = "core", "clkin0", "clkin1";
 857         resets = <&reset RESET_SD_EMMC_C>;
 858 };
 859
 860 &simplefb_hdmi {
 861         clocks = <&clkc CLKID_HDMI_PCLK>,
 862                  <&clkc CLKID_CLK81>,
 863                  <&clkc CLKID_GCLK_VENCI_INT0>;
 864 };
 865
 866 &spicc {
 867         clocks = <&clkc CLKID_SPICC>;
 868         clock-names = "core";
 869         resets = <&reset RESET_PERIPHS_SPICC>;
 870         num-cs = <1>;
 871 };
 872
 873 &spifc {
 874         clocks = <&clkc CLKID_SPI>;
 875 };
 876
 877 &uart_A {
 878         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 879         clock-names = "xtal", "pclk", "baud";
 880 };
 881
 882 &uart_AO {
 883         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 884         clock-names = "xtal", "pclk", "baud";
 885 };
 886
 887 &uart_AO_B {
 888         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 889         clock-names = "xtal", "pclk", "baud";
 890 };
 891
 892 &uart_B {
 893         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 894         clock-names = "xtal", "pclk", "baud";
 895 };
 896
 897 &uart_C {
 898         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 899         clock-names = "xtal", "pclk", "baud";
 900 };
 901
 902 &vpu {
 903         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 904         power-domains = <&pwrc_vpu>;
 905 };
 906
 907 &vdec {
 908         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
 909         clocks = <&clkc CLKID_DOS_PARSER>,
 910                  <&clkc CLKID_DOS>,
 911                  <&clkc CLKID_VDEC_1>,
 912                  <&clkc CLKID_VDEC_HEVC>;
 913         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 914         resets = <&reset RESET_PARSER>;
 915         reset-names = "esparser";
 916 };