arch/arm/dts/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         reserved-memory {
  17                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
  18                 secmon_reserved_alt: secmon@5000000 {
  19                         reg = <0x0 0x05000000 0x0 0x300000>;
  20                         no-map;
  21                 };
  22         };
  23
  24         soc {
  25                 usb0: usb@c9000000 {
  26                         status = "disabled";
  27                         compatible = "amlogic,meson-gxl-dwc3";
  28                         #address-cells = <2>;
  29                         #size-cells = <2>;
  30                         ranges;
  31
  32                         clocks = <&clkc CLKID_USB>;
  33                         clock-names = "usb_general";
  34                         resets = <&reset RESET_USB_OTG>;
  35                         reset-names = "usb_otg";
  36
  37                         dwc3: dwc3@c9000000 {
  38                                 compatible = "snps,dwc3";
  39                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  40                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  41                                 dr_mode = "host";
  42                                 maximum-speed = "high-speed";
  43                                 snps,dis_u2_susphy_quirk;
  44                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  45                         };
  46                 };
  47         };
  48 };
  49
  50 &apb {
  51         usb2_phy0: phy@78000 {
  52                 compatible = "amlogic,meson-gxl-usb2-phy";
  53                 #phy-cells = <0>;
  54                 reg = <0x0 0x78000 0x0 0x20>;
  55                 clocks = <&clkc CLKID_USB>;
  56                 clock-names = "phy";
  57                 resets = <&reset RESET_USB_OTG>;
  58                 reset-names = "phy";
  59                 status = "okay";
  60         };
  61
  62         usb2_phy1: phy@78020 {
  63                 compatible = "amlogic,meson-gxl-usb2-phy";
  64                 #phy-cells = <0>;
  65                 reg = <0x0 0x78020 0x0 0x20>;
  66                 clocks = <&clkc CLKID_USB>;
  67                 clock-names = "phy";
  68                 resets = <&reset RESET_USB_OTG>;
  69                 reset-names = "phy";
  70                 status = "okay";
  71         };
  72
  73         usb3_phy: phy@78080 {
  74                 compatible = "amlogic,meson-gxl-usb3-phy";
  75                 #phy-cells = <0>;
  76                 reg = <0x0 0x78080 0x0 0x20>;
  77                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  78                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  79                 clock-names = "phy", "peripheral";
  80                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  81                 reset-names = "phy", "peripheral";
  82                 status = "okay";
  83         };
  84 };
  85
  86 &ethmac {
  87         reg = <0x0 0xc9410000 0x0 0x10000
  88                0x0 0xc8834540 0x0 0x4>;
  89
  90         clocks = <&clkc CLKID_ETH>,
  91                  <&clkc CLKID_FCLK_DIV2>,
  92                  <&clkc CLKID_MPLL2>;
  93         clock-names = "stmmaceth", "clkin0", "clkin1";
  94
  95         mdio0: mdio {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98                 compatible = "snps,dwmac-mdio";
  99         };
 100 };
 101
 102 &aobus {
 103         pinctrl_aobus: pinctrl@14 {
 104                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
 105                 #address-cells = <2>;
 106                 #size-cells = <2>;
 107                 ranges;
 108
 109                 gpio_ao: bank@14 {
 110                         reg = <0x0 0x00014 0x0 0x8>,
 111                               <0x0 0x0002c 0x0 0x4>,
 112                               <0x0 0x00024 0x0 0x8>;
 113                         reg-names = "mux", "pull", "gpio";
 114                         gpio-controller;
 115                         #gpio-cells = <2>;
 116                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 117                 };
 118
 119                 uart_ao_a_pins: uart_ao_a {
 120                         mux {
 121                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 122                                 function = "uart_ao";
 123                         };
 124                 };
 125
 126                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 127                         mux {
 128                                 groups = "uart_cts_ao_a",
 129                                        "uart_rts_ao_a";
 130                                 function = "uart_ao";
 131                         };
 132                 };
 133
 134                 uart_ao_b_pins: uart_ao_b {
 135                         mux {
 136                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 137                                 function = "uart_ao_b";
 138                         };
 139                 };
 140
 141                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 142                         mux {
 143                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 144                                 function = "uart_ao_b";
 145                         };
 146                 };
 147
 148                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 149                         mux {
 150                                 groups = "uart_cts_ao_b",
 151                                        "uart_rts_ao_b";
 152                                 function = "uart_ao_b";
 153                         };
 154                 };
 155
 156                 remote_input_ao_pins: remote_input_ao {
 157                         mux {
 158                                 groups = "remote_input_ao";
 159                                 function = "remote_input_ao";
 160                         };
 161                 };
 162
 163                 i2c_ao_pins: i2c_ao {
 164                         mux {
 165                                 groups = "i2c_sck_ao",
 166                                        "i2c_sda_ao";
 167                                 function = "i2c_ao";
 168                         };
 169                 };
 170
 171                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 172                         mux {
 173                                 groups = "pwm_ao_a_3";
 174                                 function = "pwm_ao_a";
 175                         };
 176                 };
 177
 178                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 179                         mux {
 180                                 groups = "pwm_ao_a_8";
 181                                 function = "pwm_ao_a";
 182                         };
 183                 };
 184
 185                 pwm_ao_b_pins: pwm_ao_b {
 186                         mux {
 187                                 groups = "pwm_ao_b";
 188                                 function = "pwm_ao_b";
 189                         };
 190                 };
 191
 192                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 193                         mux {
 194                                 groups = "pwm_ao_b_6";
 195                                 function = "pwm_ao_b";
 196                         };
 197                 };
 198
 199                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 200                         mux {
 201                                 groups = "i2s_out_ch23_ao";
 202                                 function = "i2s_out_ao";
 203                         };
 204                 };
 205
 206                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 207                         mux {
 208                                 groups = "i2s_out_ch45_ao";
 209                                 function = "i2s_out_ao";
 210                         };
 211                 };
 212
 213                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 214                         mux {
 215                                 groups = "spdif_out_ao_6";
 216                                 function = "spdif_out_ao";
 217                         };
 218                 };
 219
 220                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 221                         mux {
 222                                 groups = "spdif_out_ao_9";
 223                                 function = "spdif_out_ao";
 224                         };
 225                 };
 226
 227                 ao_cec_pins: ao_cec {
 228                         mux {
 229                                 groups = "ao_cec";
 230                                 function = "cec_ao";
 231                         };
 232                 };
 233
 234                 ee_cec_pins: ee_cec {
 235                         mux {
 236                                 groups = "ee_cec";
 237                                 function = "cec_ao";
 238                         };
 239                 };
 240         };
 241 };
 242
 243 &cec_AO {
 244         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 245         clock-names = "core";
 246 };
 247
 248 &clkc_AO {
 249         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 250 };
 251
 252 &gpio_intc {
 253         compatible = "amlogic,meson-gpio-intc",
 254                      "amlogic,meson-gxl-gpio-intc";
 255         status = "okay";
 256 };
 257
 258 &hdmi_tx {
 259         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 260         resets = <&reset RESET_HDMITX_CAPB3>,
 261                  <&reset RESET_HDMI_SYSTEM_RESET>,
 262                  <&reset RESET_HDMI_TX>;
 263         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 264         clocks = <&clkc CLKID_HDMI_PCLK>,
 265                  <&clkc CLKID_CLK81>,
 266                  <&clkc CLKID_GCLK_VENCI_INT0>;
 267         clock-names = "isfr", "iahb", "venci";
 268 };
 269
 270 &hiubus {
 271         clkc: clock-controller@0 {
 272                 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
 273                 #clock-cells = <1>;
 274                 reg = <0x0 0x0 0x0 0x3db>;
 275         };
 276 };
 277
 278 &i2c_A {
 279         clocks = <&clkc CLKID_I2C>;
 280 };
 281
 282 &i2c_AO {
 283         clocks = <&clkc CLKID_AO_I2C>;
 284 };
 285
 286 &i2c_B {
 287         clocks = <&clkc CLKID_I2C>;
 288 };
 289
 290 &i2c_C {
 291         clocks = <&clkc CLKID_I2C>;
 292 };
 293
 294 &periphs {
 295         pinctrl_periphs: pinctrl@4b0 {
 296                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 297                 #address-cells = <2>;
 298                 #size-cells = <2>;
 299                 ranges;
 300
 301                 gpio: bank@4b0 {
 302                         reg = <0x0 0x004b0 0x0 0x28>,
 303                               <0x0 0x004e8 0x0 0x14>,
 304                               <0x0 0x00520 0x0 0x14>,
 305                               <0x0 0x00430 0x0 0x40>;
 306                         reg-names = "mux", "pull", "pull-enable", "gpio";
 307                         gpio-controller;
 308                         #gpio-cells = <2>;
 309                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 310                 };
 311
 312                 emmc_pins: emmc {
 313                         mux {
 314                                 groups = "emmc_nand_d07",
 315                                        "emmc_cmd",
 316                                        "emmc_clk";
 317                                 function = "emmc";
 318                         };
 319                 };
 320
 321                 emmc_ds_pins: emmc-ds {
 322                         mux {
 323                                 groups = "emmc_ds";
 324                                 function = "emmc";
 325                         };
 326                 };
 327
 328                 emmc_clk_gate_pins: emmc_clk_gate {
 329                         mux {
 330                                 groups = "BOOT_8";
 331                                 function = "gpio_periphs";
 332                         };
 333                         cfg-pull-down {
 334                                 pins = "BOOT_8";
 335                                 bias-pull-down;
 336                         };
 337                 };
 338
 339                 nor_pins: nor {
 340                         mux {
 341                                 groups = "nor_d",
 342                                        "nor_q",
 343                                        "nor_c",
 344                                        "nor_cs";
 345                                 function = "nor";
 346                         };
 347                 };
 348
 349                 spi_pins: spi {
 350                         mux {
 351                                 groups = "spi_miso",
 352                                         "spi_mosi",
 353                                         "spi_sclk";
 354                                 function = "spi";
 355                         };
 356                 };
 357
 358                 spi_ss0_pins: spi-ss0 {
 359                         mux {
 360                                 groups = "spi_ss0";
 361                                 function = "spi";
 362                         };
 363                 };
 364
 365                 sdcard_pins: sdcard {
 366                         mux {
 367                                 groups = "sdcard_d0",
 368                                        "sdcard_d1",
 369                                        "sdcard_d2",
 370                                        "sdcard_d3",
 371                                        "sdcard_cmd",
 372                                        "sdcard_clk";
 373                                 function = "sdcard";
 374                         };
 375                 };
 376
 377                 sdcard_clk_gate_pins: sdcard_clk_gate {
 378                         mux {
 379                                 groups = "CARD_2";
 380                                 function = "gpio_periphs";
 381                         };
 382                         cfg-pull-down {
 383                                 pins = "CARD_2";
 384                                 bias-pull-down;
 385                         };
 386                 };
 387
 388                 sdio_pins: sdio {
 389                         mux {
 390                                 groups = "sdio_d0",
 391                                        "sdio_d1",
 392                                        "sdio_d2",
 393                                        "sdio_d3",
 394                                        "sdio_cmd",
 395                                        "sdio_clk";
 396                                 function = "sdio";
 397                         };
 398                 };
 399
 400                 sdio_clk_gate_pins: sdio_clk_gate {
 401                         mux {
 402                                 groups = "GPIOX_4";
 403                                 function = "gpio_periphs";
 404                         };
 405                         cfg-pull-down {
 406                                 pins = "GPIOX_4";
 407                                 bias-pull-down;
 408                         };
 409                 };
 410
 411                 sdio_irq_pins: sdio_irq {
 412                         mux {
 413                                 groups = "sdio_irq";
 414                                 function = "sdio";
 415                         };
 416                 };
 417
 418                 uart_a_pins: uart_a {
 419                         mux {
 420                                 groups = "uart_tx_a",
 421                                        "uart_rx_a";
 422                                 function = "uart_a";
 423                         };
 424                 };
 425
 426                 uart_a_cts_rts_pins: uart_a_cts_rts {
 427                         mux {
 428                                 groups = "uart_cts_a",
 429                                        "uart_rts_a";
 430                                 function = "uart_a";
 431                         };
 432                 };
 433
 434                 uart_b_pins: uart_b {
 435                         mux {
 436                                 groups = "uart_tx_b",
 437                                        "uart_rx_b";
 438                                 function = "uart_b";
 439                         };
 440                 };
 441
 442                 uart_b_cts_rts_pins: uart_b_cts_rts {
 443                         mux {
 444                                 groups = "uart_cts_b",
 445                                        "uart_rts_b";
 446                                 function = "uart_b";
 447                         };
 448                 };
 449
 450                 uart_c_pins: uart_c {
 451                         mux {
 452                                 groups = "uart_tx_c",
 453                                        "uart_rx_c";
 454                                 function = "uart_c";
 455                         };
 456                 };
 457
 458                 uart_c_cts_rts_pins: uart_c_cts_rts {
 459                         mux {
 460                                 groups = "uart_cts_c",
 461                                        "uart_rts_c";
 462                                 function = "uart_c";
 463                         };
 464                 };
 465
 466                 i2c_a_pins: i2c_a {
 467                         mux {
 468                                 groups = "i2c_sck_a",
 469                                      "i2c_sda_a";
 470                                 function = "i2c_a";
 471                         };
 472                 };
 473
 474                 i2c_b_pins: i2c_b {
 475                         mux {
 476                                 groups = "i2c_sck_b",
 477                                       "i2c_sda_b";
 478                                 function = "i2c_b";
 479                         };
 480                 };
 481
 482                 i2c_c_pins: i2c_c {
 483                         mux {
 484                                 groups = "i2c_sck_c",
 485                                       "i2c_sda_c";
 486                                 function = "i2c_c";
 487                         };
 488                 };
 489
 490                 eth_pins: eth_c {
 491                         mux {
 492                                 groups = "eth_mdio",
 493                                        "eth_mdc",
 494                                        "eth_clk_rx_clk",
 495                                        "eth_rx_dv",
 496                                        "eth_rxd0",
 497                                        "eth_rxd1",
 498                                        "eth_rxd2",
 499                                        "eth_rxd3",
 500                                        "eth_rgmii_tx_clk",
 501                                        "eth_tx_en",
 502                                        "eth_txd0",
 503                                        "eth_txd1",
 504                                        "eth_txd2",
 505                                        "eth_txd3";
 506                                 function = "eth";
 507                         };
 508                 };
 509
 510                 eth_link_led_pins: eth_link_led {
 511                         mux {
 512                                 groups = "eth_link_led";
 513                                 function = "eth_led";
 514                         };
 515                 };
 516
 517                 eth_act_led_pins: eth_act_led {
 518                         mux {
 519                                 groups = "eth_act_led";
 520                                 function = "eth_led";
 521                         };
 522                 };
 523
 524                 pwm_a_pins: pwm_a {
 525                         mux {
 526                                 groups = "pwm_a";
 527                                 function = "pwm_a";
 528                         };
 529                 };
 530
 531                 pwm_b_pins: pwm_b {
 532                         mux {
 533                                 groups = "pwm_b";
 534                                 function = "pwm_b";
 535                         };
 536                 };
 537
 538                 pwm_c_pins: pwm_c {
 539                         mux {
 540                                 groups = "pwm_c";
 541                                 function = "pwm_c";
 542                         };
 543                 };
 544
 545                 pwm_d_pins: pwm_d {
 546                         mux {
 547                                 groups = "pwm_d";
 548                                 function = "pwm_d";
 549                         };
 550                 };
 551
 552                 pwm_e_pins: pwm_e {
 553                         mux {
 554                                 groups = "pwm_e";
 555                                 function = "pwm_e";
 556                         };
 557                 };
 558
 559                 pwm_f_clk_pins: pwm_f_clk {
 560                         mux {
 561                                 groups = "pwm_f_clk";
 562                                 function = "pwm_f";
 563                         };
 564                 };
 565
 566                 pwm_f_x_pins: pwm_f_x {
 567                         mux {
 568                                 groups = "pwm_f_x";
 569                                 function = "pwm_f";
 570                         };
 571                 };
 572
 573                 hdmi_hpd_pins: hdmi_hpd {
 574                         mux {
 575                                 groups = "hdmi_hpd";
 576                                 function = "hdmi_hpd";
 577                         };
 578                 };
 579
 580                 hdmi_i2c_pins: hdmi_i2c {
 581                         mux {
 582                                 groups = "hdmi_sda", "hdmi_scl";
 583                                 function = "hdmi_i2c";
 584                         };
 585                 };
 586
 587                 i2s_am_clk_pins: i2s_am_clk {
 588                         mux {
 589                                 groups = "i2s_am_clk";
 590                                 function = "i2s_out";
 591                         };
 592                 };
 593
 594                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 595                         mux {
 596                                 groups = "i2s_out_ao_clk";
 597                                 function = "i2s_out";
 598                         };
 599                 };
 600
 601                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 602                         mux {
 603                                 groups = "i2s_out_lr_clk";
 604                                 function = "i2s_out";
 605                         };
 606                 };
 607
 608                 i2s_out_ch01_pins: i2s_out_ch01 {
 609                         mux {
 610                                 groups = "i2s_out_ch01";
 611                                 function = "i2s_out";
 612                         };
 613                 };
 614                 i2sout_ch23_z_pins: i2sout_ch23_z {
 615                         mux {
 616                                 groups = "i2sout_ch23_z";
 617                                 function = "i2s_out";
 618                         };
 619                 };
 620
 621                 i2sout_ch45_z_pins: i2sout_ch45_z {
 622                         mux {
 623                                 groups = "i2sout_ch45_z";
 624                                 function = "i2s_out";
 625                         };
 626                 };
 627
 628                 i2sout_ch67_z_pins: i2sout_ch67_z {
 629                         mux {
 630                                 groups = "i2sout_ch67_z";
 631                                 function = "i2s_out";
 632                         };
 633                 };
 634
 635                 spdif_out_h_pins: spdif_out_ao_h {
 636                         mux {
 637                                 groups = "spdif_out_h";
 638                                 function = "spdif_out";
 639                         };
 640                 };
 641         };
 642
 643         eth-phy-mux {
 644                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 reg = <0x0 0x55c 0x0 0x4>;
 648                 mux-mask = <0xffffffff>;
 649                 mdio-parent-bus = <&mdio0>;
 650
 651                 internal_mdio: mdio@e40908ff {
 652                         reg = <0xe40908ff>;
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655
 656                         internal_phy: ethernet-phy@8 {
 657                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 658                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 659                                 reg = <8>;
 660                                 max-speed = <100>;
 661                         };
 662                 };
 663
 664                 external_mdio: mdio@2009087f {
 665                         reg = <0x2009087f>;
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                 };
 669         };
 670 };
 671
 672 &pwrc_vpu {
 673         resets = <&reset RESET_VIU>,
 674                  <&reset RESET_VENC>,
 675                  <&reset RESET_VCBUS>,
 676                  <&reset RESET_BT656>,
 677                  <&reset RESET_DVIN_RESET>,
 678                  <&reset RESET_RDMA>,
 679                  <&reset RESET_VENCI>,
 680                  <&reset RESET_VENCP>,
 681                  <&reset RESET_VDAC>,
 682                  <&reset RESET_VDI6>,
 683                  <&reset RESET_VENCL>,
 684                  <&reset RESET_VID_LOCK>;
 685         clocks = <&clkc CLKID_VPU>,
 686                  <&clkc CLKID_VAPB>;
 687         clock-names = "vpu", "vapb";
 688         /*
 689          * VPU clocking is provided by two identical clock paths
 690          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 691          * free mux to safely change frequency while running.
 692          * Same for VAPB but with a final gate after the glitch free mux.
 693          */
 694         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 695                           <&clkc CLKID_VPU_0>,
 696                           <&clkc CLKID_VPU>, /* Glitch free mux */
 697                           <&clkc CLKID_VAPB_0_SEL>,
 698                           <&clkc CLKID_VAPB_0>,
 699                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 700         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 701                                  <0>, /* Do Nothing */
 702                                  <&clkc CLKID_VPU_0>,
 703                                  <&clkc CLKID_FCLK_DIV4>,
 704                                  <0>, /* Do Nothing */
 705                                  <&clkc CLKID_VAPB_0>;
 706         assigned-clock-rates = <0>, /* Do Nothing */
 707                                <666666666>,
 708                                <0>, /* Do Nothing */
 709                                <0>, /* Do Nothing */
 710                                <250000000>,
 711                                <0>; /* Do Nothing */
 712 };
 713
 714 &saradc {
 715         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 716         clocks = <&xtal>,
 717                  <&clkc CLKID_SAR_ADC>,
 718                  <&clkc CLKID_SAR_ADC_CLK>,
 719                  <&clkc CLKID_SAR_ADC_SEL>;
 720         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 721 };
 722
 723 &sd_emmc_a {
 724         clocks = <&clkc CLKID_SD_EMMC_A>,
 725                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 726                  <&clkc CLKID_FCLK_DIV2>;
 727         clock-names = "core", "clkin0", "clkin1";
 728 };
 729
 730 &sd_emmc_b {
 731         clocks = <&clkc CLKID_SD_EMMC_B>,
 732                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 733                  <&clkc CLKID_FCLK_DIV2>;
 734        clock-names = "core", "clkin0", "clkin1";
 735 };
 736
 737 &sd_emmc_c {
 738         clocks = <&clkc CLKID_SD_EMMC_C>,
 739                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 740                  <&clkc CLKID_FCLK_DIV2>;
 741         clock-names = "core", "clkin0", "clkin1";
 742 };
 743
 744 &spicc {
 745         clocks = <&clkc CLKID_SPICC>;
 746         clock-names = "core";
 747         resets = <&reset RESET_PERIPHS_SPICC>;
 748         num-cs = <1>;
 749 };
 750
 751 &spifc {
 752         clocks = <&clkc CLKID_SPI>;
 753 };
 754
 755 &uart_A {
 756         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 757         clock-names = "xtal", "pclk", "baud";
 758 };
 759
 760 &uart_AO {
 761         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 762         clock-names = "xtal", "pclk", "baud";
 763 };
 764
 765 &uart_AO_B {
 766         clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
 767         clock-names = "xtal", "pclk", "baud";
 768 };
 769
 770 &uart_B {
 771         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 772         clock-names = "xtal", "pclk", "baud";
 773 };
 774
 775 &uart_C {
 776         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 777         clock-names = "xtal", "pclk", "baud";
 778 };
 779
 780 &vpu {
 781         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 782         power-domains = <&pwrc_vpu>;
 783 };