1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
19 compatible = "amlogic,meson-gxl-dwc3";
24 clocks = <&clkc CLKID_USB>;
25 clock-names = "usb_general";
26 resets = <&reset RESET_USB_OTG>;
27 reset-names = "usb_otg";
30 compatible = "snps,dwc3";
31 reg = <0x0 0xc9000000 0x0 0x100000>;
32 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
34 maximum-speed = "high-speed";
35 snps,dis_u2_susphy_quirk;
36 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
43 usb2_phy0: phy@78000 {
44 compatible = "amlogic,meson-gxl-usb2-phy";
46 reg = <0x0 0x78000 0x0 0x20>;
47 clocks = <&clkc CLKID_USB>;
49 resets = <&reset RESET_USB_OTG>;
54 usb2_phy1: phy@78020 {
55 compatible = "amlogic,meson-gxl-usb2-phy";
57 reg = <0x0 0x78020 0x0 0x20>;
58 clocks = <&clkc CLKID_USB>;
60 resets = <&reset RESET_USB_OTG>;
66 compatible = "amlogic,meson-gxl-usb3-phy";
68 reg = <0x0 0x78080 0x0 0x20>;
69 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71 clock-names = "phy", "peripheral";
72 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73 reset-names = "phy", "peripheral";
79 clocks = <&clkc CLKID_EFUSE>;
83 reg = <0x0 0xc9410000 0x0 0x10000
84 0x0 0xc8834540 0x0 0x4>;
86 clocks = <&clkc CLKID_ETH>,
87 <&clkc CLKID_FCLK_DIV2>,
89 clock-names = "stmmaceth", "clkin0", "clkin1";
94 compatible = "snps,dwmac-mdio";
99 pinctrl_aobus: pinctrl@14 {
100 compatible = "amlogic,meson-gxl-aobus-pinctrl";
101 #address-cells = <2>;
106 reg = <0x0 0x00014 0x0 0x8>,
107 <0x0 0x0002c 0x0 0x4>,
108 <0x0 0x00024 0x0 0x8>;
109 reg-names = "mux", "pull", "gpio";
112 gpio-ranges = <&pinctrl_aobus 0 0 14>;
115 uart_ao_a_pins: uart_ao_a {
117 groups = "uart_tx_ao_a", "uart_rx_ao_a";
118 function = "uart_ao";
123 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
125 groups = "uart_cts_ao_a",
127 function = "uart_ao";
132 uart_ao_b_pins: uart_ao_b {
134 groups = "uart_tx_ao_b", "uart_rx_ao_b";
135 function = "uart_ao_b";
140 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
142 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
143 function = "uart_ao_b";
148 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
150 groups = "uart_cts_ao_b",
152 function = "uart_ao_b";
157 remote_input_ao_pins: remote_input_ao {
159 groups = "remote_input_ao";
160 function = "remote_input_ao";
165 i2c_ao_pins: i2c_ao {
167 groups = "i2c_sck_ao",
174 pwm_ao_a_3_pins: pwm_ao_a_3 {
176 groups = "pwm_ao_a_3";
177 function = "pwm_ao_a";
182 pwm_ao_a_8_pins: pwm_ao_a_8 {
184 groups = "pwm_ao_a_8";
185 function = "pwm_ao_a";
190 pwm_ao_b_pins: pwm_ao_b {
193 function = "pwm_ao_b";
198 pwm_ao_b_6_pins: pwm_ao_b_6 {
200 groups = "pwm_ao_b_6";
201 function = "pwm_ao_b";
206 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
208 groups = "i2s_out_ch23_ao";
209 function = "i2s_out_ao";
214 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
216 groups = "i2s_out_ch45_ao";
217 function = "i2s_out_ao";
222 spdif_out_ao_6_pins: spdif_out_ao_6 {
224 groups = "spdif_out_ao_6";
225 function = "spdif_out_ao";
230 spdif_out_ao_9_pins: spdif_out_ao_9 {
232 groups = "spdif_out_ao_9";
233 function = "spdif_out_ao";
238 ao_cec_pins: ao_cec {
246 ee_cec_pins: ee_cec {
257 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
258 clock-names = "core";
262 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
263 clocks = <&xtal>, <&clkc CLKID_CLK81>;
264 clock-names = "xtal", "mpeg-clk";
268 compatible = "amlogic,meson-gpio-intc",
269 "amlogic,meson-gxl-gpio-intc";
274 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
275 resets = <&reset RESET_HDMITX_CAPB3>,
276 <&reset RESET_HDMI_SYSTEM_RESET>,
277 <&reset RESET_HDMI_TX>;
278 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
279 clocks = <&clkc CLKID_HDMI_PCLK>,
281 <&clkc CLKID_GCLK_VENCI_INT0>;
282 clock-names = "isfr", "iahb", "venci";
286 clkc: clock-controller {
287 compatible = "amlogic,gxl-clkc";
290 clock-names = "xtal";
295 clocks = <&clkc CLKID_I2C>;
299 clocks = <&clkc CLKID_AO_I2C>;
303 clocks = <&clkc CLKID_I2C>;
307 clocks = <&clkc CLKID_I2C>;
311 pinctrl_periphs: pinctrl@4b0 {
312 compatible = "amlogic,meson-gxl-periphs-pinctrl";
313 #address-cells = <2>;
318 reg = <0x0 0x004b0 0x0 0x28>,
319 <0x0 0x004e8 0x0 0x14>,
320 <0x0 0x00520 0x0 0x14>,
321 <0x0 0x00430 0x0 0x40>;
322 reg-names = "mux", "pull", "pull-enable", "gpio";
325 gpio-ranges = <&pinctrl_periphs 0 0 100>;
330 groups = "emmc_nand_d07",
338 emmc_ds_pins: emmc-ds {
346 emmc_clk_gate_pins: emmc_clk_gate {
349 function = "gpio_periphs";
375 spi_ss0_pins: spi-ss0 {
383 sdcard_pins: sdcard {
385 groups = "sdcard_d0",
396 sdcard_clk_gate_pins: sdcard_clk_gate {
399 function = "gpio_periphs";
417 sdio_clk_gate_pins: sdio_clk_gate {
420 function = "gpio_periphs";
425 sdio_irq_pins: sdio_irq {
433 uart_a_pins: uart_a {
435 groups = "uart_tx_a",
442 uart_a_cts_rts_pins: uart_a_cts_rts {
444 groups = "uart_cts_a",
451 uart_b_pins: uart_b {
453 groups = "uart_tx_b",
460 uart_b_cts_rts_pins: uart_b_cts_rts {
462 groups = "uart_cts_b",
469 uart_c_pins: uart_c {
471 groups = "uart_tx_c",
478 uart_c_cts_rts_pins: uart_c_cts_rts {
480 groups = "uart_cts_c",
489 groups = "i2c_sck_a",
498 groups = "i2c_sck_b",
507 groups = "i2c_sck_c",
535 eth_link_led_pins: eth_link_led {
537 groups = "eth_link_led";
538 function = "eth_led";
543 eth_act_led_pins: eth_act_led {
545 groups = "eth_act_led";
546 function = "eth_led";
590 pwm_f_clk_pins: pwm_f_clk {
592 groups = "pwm_f_clk";
598 pwm_f_x_pins: pwm_f_x {
606 hdmi_hpd_pins: hdmi_hpd {
609 function = "hdmi_hpd";
614 hdmi_i2c_pins: hdmi_i2c {
616 groups = "hdmi_sda", "hdmi_scl";
617 function = "hdmi_i2c";
622 i2s_am_clk_pins: i2s_am_clk {
624 groups = "i2s_am_clk";
625 function = "i2s_out";
630 i2s_out_ao_clk_pins: i2s_out_ao_clk {
632 groups = "i2s_out_ao_clk";
633 function = "i2s_out";
638 i2s_out_lr_clk_pins: i2s_out_lr_clk {
640 groups = "i2s_out_lr_clk";
641 function = "i2s_out";
646 i2s_out_ch01_pins: i2s_out_ch01 {
648 groups = "i2s_out_ch01";
649 function = "i2s_out";
653 i2sout_ch23_z_pins: i2sout_ch23_z {
655 groups = "i2sout_ch23_z";
656 function = "i2s_out";
661 i2sout_ch45_z_pins: i2sout_ch45_z {
663 groups = "i2sout_ch45_z";
664 function = "i2s_out";
669 i2sout_ch67_z_pins: i2sout_ch67_z {
671 groups = "i2sout_ch67_z";
672 function = "i2s_out";
677 spdif_out_h_pins: spdif_out_ao_h {
679 groups = "spdif_out_h";
680 function = "spdif_out";
687 compatible = "mdio-mux-mmioreg", "mdio-mux";
688 #address-cells = <1>;
690 reg = <0x0 0x55c 0x0 0x4>;
691 mux-mask = <0xffffffff>;
692 mdio-parent-bus = <&mdio0>;
694 internal_mdio: mdio@e40908ff {
696 #address-cells = <1>;
699 internal_phy: ethernet-phy@8 {
700 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
701 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
707 external_mdio: mdio@2009087f {
709 #address-cells = <1>;
716 resets = <&reset RESET_VIU>,
718 <&reset RESET_VCBUS>,
719 <&reset RESET_BT656>,
720 <&reset RESET_DVIN_RESET>,
722 <&reset RESET_VENCI>,
723 <&reset RESET_VENCP>,
726 <&reset RESET_VENCL>,
727 <&reset RESET_VID_LOCK>;
728 clocks = <&clkc CLKID_VPU>,
730 clock-names = "vpu", "vapb";
732 * VPU clocking is provided by two identical clock paths
733 * VPU_0 and VPU_1 muxed to a single clock by a glitch
734 * free mux to safely change frequency while running.
735 * Same for VAPB but with a final gate after the glitch free mux.
737 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
739 <&clkc CLKID_VPU>, /* Glitch free mux */
740 <&clkc CLKID_VAPB_0_SEL>,
741 <&clkc CLKID_VAPB_0>,
742 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
743 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
744 <0>, /* Do Nothing */
746 <&clkc CLKID_FCLK_DIV4>,
747 <0>, /* Do Nothing */
748 <&clkc CLKID_VAPB_0>;
749 assigned-clock-rates = <0>, /* Do Nothing */
751 <0>, /* Do Nothing */
752 <0>, /* Do Nothing */
754 <0>; /* Do Nothing */
758 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
760 <&clkc CLKID_SAR_ADC>,
761 <&clkc CLKID_SAR_ADC_CLK>,
762 <&clkc CLKID_SAR_ADC_SEL>;
763 clock-names = "clkin", "core", "adc_clk", "adc_sel";
767 clocks = <&clkc CLKID_SD_EMMC_A>,
768 <&clkc CLKID_SD_EMMC_A_CLK0>,
769 <&clkc CLKID_FCLK_DIV2>;
770 clock-names = "core", "clkin0", "clkin1";
771 resets = <&reset RESET_SD_EMMC_A>;
775 clocks = <&clkc CLKID_SD_EMMC_B>,
776 <&clkc CLKID_SD_EMMC_B_CLK0>,
777 <&clkc CLKID_FCLK_DIV2>;
778 clock-names = "core", "clkin0", "clkin1";
779 resets = <&reset RESET_SD_EMMC_B>;
783 clocks = <&clkc CLKID_SD_EMMC_C>,
784 <&clkc CLKID_SD_EMMC_C_CLK0>,
785 <&clkc CLKID_FCLK_DIV2>;
786 clock-names = "core", "clkin0", "clkin1";
787 resets = <&reset RESET_SD_EMMC_C>;
791 clocks = <&clkc CLKID_SPICC>;
792 clock-names = "core";
793 resets = <&reset RESET_PERIPHS_SPICC>;
798 clocks = <&clkc CLKID_SPI>;
802 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
803 clock-names = "xtal", "pclk", "baud";
807 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
808 clock-names = "xtal", "pclk", "baud";
812 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
813 clock-names = "xtal", "pclk", "baud";
817 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
818 clock-names = "xtal", "pclk", "baud";
822 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
823 clock-names = "xtal", "pclk", "baud";
827 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
828 power-domains = <&pwrc_vpu>;