arch/arm/dts/meson-g12a-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2019 BayLibre, SAS.
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  */
   6
   7 / {
   8         soc {
   9                 ethmac: ethernet@ff3f0000 {
  10                         compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
  11                                      "snps,dwmac";
  12                         reg = <0x0 0xff3f0000 0x0 0x10000
  13                                0x0 0xff634540 0x0 0x8>;
  14                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  15                         interrupt-names = "macirq";
  16                         clocks = <&clkc CLKID_ETH>,
  17                                  <&clkc CLKID_FCLK_DIV2>,
  18                                  <&clkc CLKID_MPLL2>;
  19                         clock-names = "stmmaceth", "clkin0", "clkin1";
  20                         status = "disabled";
  21
  22                         mdio0: mdio {
  23                                 #address-cells = <1>;
  24                                 #size-cells = <0>;
  25                                 compatible = "snps,dwmac-mdio";
  26                         };
  27                 };
  28
  29                 sd_emmc_a: sd@ffe03000 {
  30                         compatible = "amlogic,meson-axg-mmc";
  31                         reg = <0x0 0xffe03000 0x0 0x800>;
  32                         interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
  33                         status = "disabled";
  34                         clocks = <&clkc CLKID_SD_EMMC_A>,
  35                                  <&clkc CLKID_SD_EMMC_A_CLK0>,
  36                                  <&clkc CLKID_FCLK_DIV2>;
  37                         clock-names = "core", "clkin0", "clkin1";
  38                         resets = <&reset RESET_SD_EMMC_A>;
  39                 };
  40
  41                 sd_emmc_b: sd@ffe05000 {
  42                         compatible = "amlogic,meson-axg-mmc";
  43                         reg = <0x0 0xffe05000 0x0 0x800>;
  44                         interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
  45                         status = "disabled";
  46                         clocks = <&clkc CLKID_SD_EMMC_B>,
  47                                  <&clkc CLKID_SD_EMMC_B_CLK0>,
  48                                  <&clkc CLKID_FCLK_DIV2>;
  49                         clock-names = "core", "clkin0", "clkin1";
  50                         resets = <&reset RESET_SD_EMMC_B>;
  51                 };
  52
  53                 sd_emmc_c: mmc@ffe07000 {
  54                         compatible = "amlogic,meson-axg-mmc";
  55                         reg = <0x0 0xffe07000 0x0 0x800>;
  56                         interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
  57                         status = "disabled";
  58                         clocks = <&clkc CLKID_SD_EMMC_C>,
  59                                  <&clkc CLKID_SD_EMMC_C_CLK0>,
  60                                  <&clkc CLKID_FCLK_DIV2>;
  61                         clock-names = "core", "clkin0", "clkin1";
  62                         resets = <&reset RESET_SD_EMMC_C>;
  63                 };
  64         };
  65 };
  66
  67 &periphs_pinctrl {
  68         emmc_pins: emmc {
  69                 mux {
  70                         groups = "emmc_nand_d0",
  71                                  "emmc_nand_d1",
  72                                  "emmc_nand_d2",
  73                                  "emmc_nand_d3",
  74                                  "emmc_nand_d4",
  75                                  "emmc_nand_d5",
  76                                  "emmc_nand_d6",
  77                                  "emmc_nand_d7",
  78                                  "emmc_clk",
  79                                  "emmc_cmd";
  80                         function = "emmc";
  81                         bias-pull-up;
  82                 };
  83         };
  84
  85         emmc_ds_pins: emmc-ds {
  86                 mux {
  87                         groups = "emmc_nand_ds";
  88                         function = "emmc";
  89                         bias-pull-down;
  90                 };
  91         };
  92
  93         emmc_clk_gate_pins: emmc_clk_gate {
  94                 mux {
  95                         groups = "BOOT_8";
  96                         function = "gpio_periphs";
  97                         bias-pull-down;
  98                 };
  99         };
 100
 101         eth_leds_pins: eth-leds {
 102                 mux {
 103                         groups = "eth_link_led",
 104                                  "eth_act_led";
 105                         function = "eth";
 106                         bias-disable;
 107                 };
 108         };
 109
 110         eth_rmii_pins: eth-rmii {
 111                 mux {
 112                         groups = "eth_mdio",
 113                                  "eth_mdc",
 114                                  "eth_rgmii_rx_clk",
 115                                  "eth_rx_dv",
 116                                  "eth_rxd0",
 117                                  "eth_rxd1",
 118                                  "eth_txen",
 119                                  "eth_txd0",
 120                                  "eth_txd1";
 121                         function = "eth";
 122                         bias-disable;
 123                 };
 124         };
 125
 126         eth_rgmii_pins: eth-rgmii {
 127                 mux {
 128                         groups = "eth_rxd2_rgmii",
 129                                  "eth_rxd3_rgmii",
 130                                  "eth_rgmii_tx_clk",
 131                                  "eth_txd2_rgmii",
 132                                  "eth_txd3_rgmii";
 133                         function = "eth";
 134                         bias-disable;
 135                 };
 136         };
 137
 138         sdcard_c_pins: sdcard_c {
 139                 mux {
 140                         groups = "sdcard_d0_c",
 141                                  "sdcard_d1_c",
 142                                  "sdcard_d2_c",
 143                                  "sdcard_d3_c",
 144                                  "sdcard_cmd_c",
 145                                  "sdcard_clk_c";
 146                         function = "sdcard";
 147                         bias-pull-up;
 148                 };
 149         };
 150
 151         sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
 152                 mux {
 153                         groups = "GPIOC_4";
 154                         function = "gpio_periphs";
 155                         bias-pull-down;
 156                 };
 157         };
 158
 159         sdcard_z_pins: sdcard_z {
 160                 mux {
 161                         groups = "sdcard_d0_z",
 162                                  "sdcard_d1_z",
 163                                  "sdcard_d2_z",
 164                                  "sdcard_d3_z",
 165                                  "sdcard_cmd_z",
 166                                  "sdcard_clk_z";
 167                         function = "sdcard";
 168                         bias-pull-up;
 169                 };
 170         };
 171
 172         sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
 173                 mux {
 174                         groups = "GPIOZ_6";
 175                         function = "gpio_periphs";
 176                         bias-pull-down;
 177                 };
 178         };
 179 };
 180
 181 &periphs {
 182         eth_phy: mdio-multiplexer@4c000 {
 183                 compatible = "amlogic,g12a-mdio-mux";
 184                 reg = <0x0 0x4c000 0x0 0xa4>;
 185                 clocks = <&clkc CLKID_ETH_PHY>,
 186                          <&xtal>,
 187                          <&clkc CLKID_MPLL_5OM>;
 188                 clock-names = "pclk", "clkin0", "clkin1";
 189                 mdio-parent-bus = <&mdio0>;
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192
 193                 ext_mdio: mdio@0 {
 194                         reg = <0>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                 };
 198
 199                 int_mdio: mdio@1 {
 200                         reg = <1>;
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203
 204                         internal_ephy: ethernet_phy@8 {
 205                                 compatible = "ethernet-phy-id0180.3300",
 206                                              "ethernet-phy-ieee802.3-c22";
 207                                 reg = <8>;
 208                                 max-speed = <100>;
 209
 210                                 /* FIXME: Add irq support */
 211                         };
 212                 };
 213         };
 214 };
 215
 216