arch/arm/dts/ls1021a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale ls1021a SOC common device tree source
   4  *
   5  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   6  * Copyright 2021 NXP
   7  */
   8
   9 #include "skeleton.dtsi"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "fsl,ls1021a";
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &lpuart0;
  18                 serial1 = &lpuart1;
  19                 serial2 = &lpuart2;
  20                 serial3 = &lpuart3;
  21                 serial4 = &lpuart4;
  22                 serial5 = &lpuart5;
  23                 sysclk = &sysclk;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@f00 {
  31                         compatible = "arm,cortex-a7";
  32                         device_type = "cpu";
  33                         reg = <0xf00>;
  34                         clocks = <&clockgen 1 0>;
  35                 };
  36
  37                 cpu@f01 {
  38                         compatible = "arm,cortex-a7";
  39                         device_type = "cpu";
  40                         reg = <0xf01>;
  41                         clocks = <&clockgen 1 0>;
  42                 };
  43         };
  44
  45         sysclk: sysclk {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 clock-frequency = <100000000>;
  49                 clock-output-names = "sysclk";
  50         };
  51
  52         timer {
  53                 compatible = "arm,armv7-timer";
  54                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  55                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  56                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  57                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  58         };
  59
  60         pmu {
  61                 compatible = "arm,cortex-a7-pmu";
  62                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  63                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  64         };
  65
  66         soc {
  67                 compatible = "simple-bus";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 device_type = "soc";
  71                 interrupt-parent = <&gic>;
  72                 ranges;
  73
  74                 gic: interrupt-controller@1400000 {
  75                         compatible = "arm,cortex-a7-gic";
  76                         #interrupt-cells = <3>;
  77                         interrupt-controller;
  78                         reg = <0x1401000 0x1000>,
  79                               <0x1402000 0x1000>,
  80                               <0x1404000 0x2000>,
  81                               <0x1406000 0x2000>;
  82                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  83
  84                 };
  85
  86                 ifc: ifc@1530000 {
  87                         compatible = "fsl,ifc", "simple-bus";
  88                         reg = <0x1530000 0x10000>;
  89                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  90                 };
  91
  92                 sfp: efuse@1e80000 {
  93                         compatible = "fsl,ls1021a-sfp";
  94                         reg = <0x0 0x1e80000 0x0 0x10000>;
  95                         clocks = <&clockgen 4 3>;
  96                         clock-names = "sfp";
  97                 };
  98
  99                 dcfg: dcfg@1ee0000 {
 100                         compatible = "fsl,ls1021a-dcfg", "syscon";
 101                         reg = <0x1ee0000 0x10000>;
 102                         big-endian;
 103                 };
 104
 105                 esdhc: esdhc@1560000 {
 106                         compatible = "fsl,esdhc";
 107                         reg = <0x1560000 0x10000>;
 108                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 109                         clock-frequency = <0>;
 110                         voltage-ranges = <1800 1800 3300 3300>;
 111                         sdhci,auto-cmd12;
 112                         big-endian;
 113                         bus-width = <4>;
 114                 };
 115
 116                 gpio0: gpio@2300000 {
 117                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 118                         reg = <0x2300000 0x10000>;
 119                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 120                         gpio-controller;
 121                         #gpio-cells = <2>;
 122                         interrupt-controller;
 123                         #interrupt-cells = <2>;
 124                 };
 125
 126                 gpio1: gpio@2310000 {
 127                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 128                         reg = <0x2310000 0x10000>;
 129                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 130                         gpio-controller;
 131                         #gpio-cells = <2>;
 132                         interrupt-controller;
 133                         #interrupt-cells = <2>;
 134                 };
 135
 136                 gpio2: gpio@2320000 {
 137                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 138                         reg = <0x2320000 0x10000>;
 139                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 140                         gpio-controller;
 141                         #gpio-cells = <2>;
 142                         interrupt-controller;
 143                         #interrupt-cells = <2>;
 144                 };
 145
 146                 gpio3: gpio@2330000 {
 147                         compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
 148                         reg = <0x2330000 0x10000>;
 149                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                         interrupt-controller;
 153                         #interrupt-cells = <2>;
 154                 };
 155
 156                 scfg: scfg@1570000 {
 157                         compatible = "fsl,ls1021a-scfg", "syscon";
 158                         reg = <0x1570000 0x10000>;
 159                         big-endian;
 160                 };
 161
 162                 crypto: crypto@1700000 {
 163                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 164                         fsl,sec-era = <7>;
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         reg              = <0x1700000 0x100000>;
 168                         ranges           = <0x0 0x1700000 0x100000>;
 169                         interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 170
 171                         sec_jr0: jr@10000 {
 172                                 compatible = "fsl,sec-v5.0-job-ring",
 173                                      "fsl,sec-v4.0-job-ring";
 174                                 reg = <0x10000 0x10000>;
 175                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 176                         };
 177
 178                         sec_jr1: jr@20000 {
 179                                 compatible = "fsl,sec-v5.0-job-ring",
 180                                      "fsl,sec-v4.0-job-ring";
 181                                 reg = <0x20000 0x10000>;
 182                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 183                         };
 184
 185                         sec_jr2: jr@30000 {
 186                                 compatible = "fsl,sec-v5.0-job-ring",
 187                                      "fsl,sec-v4.0-job-ring";
 188                                 reg = <0x30000 0x10000>;
 189                                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 190                         };
 191
 192                         sec_jr3: jr@40000 {
 193                                 compatible = "fsl,sec-v5.0-job-ring",
 194                                      "fsl,sec-v4.0-job-ring";
 195                                 reg = <0x40000 0x10000>;
 196                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 197                         };
 198
 199                 };
 200
 201                 clockgen: clocking@1ee1000 {
 202                         compatible = "fsl,ls1021a-clockgen";
 203                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 204                         #clock-cells = <2>;
 205                         clocks = <&sysclk>;
 206                 };
 207
 208                 dspi0: dspi@2100000 {
 209                         compatible = "fsl,vf610-dspi";
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         reg = <0x2100000 0x10000>;
 213                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 214                         clock-names = "dspi";
 215                         clocks = <&clockgen 4 1>;
 216                         spi-num-chipselects = <6>;
 217                         big-endian;
 218                         status = "disabled";
 219                 };
 220
 221                 dspi1: dspi@2110000 {
 222                         compatible = "fsl,vf610-dspi";
 223                         #address-cells = <1>;
 224                         #size-cells = <0>;
 225                         reg = <0x2110000 0x10000>;
 226                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 227                         clock-names = "dspi";
 228                         clocks = <&clockgen 4 1>;
 229                         spi-num-chipselects = <6>;
 230                         big-endian;
 231                         status = "disabled";
 232                 };
 233
 234                 qspi: quadspi@1550000 {
 235                         compatible = "fsl,ls1021a-qspi";
 236                         #address-cells = <1>;
 237                         #size-cells = <0>;
 238                         reg = <0x1550000 0x10000>,
 239                                 <0x40000000 0x1000000>;
 240                         reg-names = "QuadSPI", "QuadSPI-memory";
 241                         status = "disabled";
 242                 };
 243
 244                 i2c0: i2c@2180000 {
 245                         compatible = "fsl,vf610-i2c";
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         reg = <0x2180000 0x10000>;
 249                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 250                         clock-names = "i2c";
 251                         clocks = <&clockgen 4 1>;
 252                         status = "disabled";
 253                 };
 254
 255                 i2c1: i2c@2190000 {
 256                         compatible = "fsl,vf610-i2c";
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259                         reg = <0x2190000 0x10000>;
 260                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 261                         clock-names = "i2c";
 262                         clocks = <&clockgen 4 1>;
 263                         status = "disabled";
 264                 };
 265
 266                 i2c2: i2c@21a0000 {
 267                         compatible = "fsl,vf610-i2c";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         reg = <0x21a0000 0x10000>;
 271                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 272                         clock-names = "i2c";
 273                         clocks = <&clockgen 4 1>;
 274                         status = "disabled";
 275                 };
 276
 277                 uart0: serial@21c0500 {
 278                         compatible = "fsl,16550-FIFO64", "ns16550a";
 279                         reg = <0x21c0500 0x100>;
 280                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 281                         fifo-size = <15>;
 282                         status = "disabled";
 283                 };
 284
 285                 uart1: serial@21c0600 {
 286                         compatible = "fsl,16550-FIFO64", "ns16550a";
 287                         reg = <0x21c0600 0x100>;
 288                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 289                         fifo-size = <15>;
 290                         status = "disabled";
 291                 };
 292
 293                 uart2: serial@21d0500 {
 294                         compatible = "fsl,16550-FIFO64", "ns16550a";
 295                         reg = <0x21d0500 0x100>;
 296                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 297                         fifo-size = <15>;
 298                         status = "disabled";
 299                 };
 300
 301                 uart3: serial@21d0600 {
 302                         compatible = "fsl,16550-FIFO64", "ns16550a";
 303                         reg = <0x21d0600 0x100>;
 304                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 305                         fifo-size = <15>;
 306                         status = "disabled";
 307                 };
 308
 309                 lpuart0: serial@2950000 {
 310                         compatible = "fsl,ls1021a-lpuart";
 311                         reg = <0x2950000 0x1000>;
 312                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&sysclk>;
 314                         clock-names = "ipg";
 315                         status = "disabled";
 316                 };
 317
 318                 lpuart1: serial@2960000 {
 319                         compatible = "fsl,ls1021a-lpuart";
 320                         reg = <0x2960000 0x1000>;
 321                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&clockgen 4 1>;
 323                         clock-names = "ipg";
 324                         status = "disabled";
 325                 };
 326
 327                 lpuart2: serial@2970000 {
 328                         compatible = "fsl,ls1021a-lpuart";
 329                         reg = <0x2970000 0x1000>;
 330                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&clockgen 4 1>;
 332                         clock-names = "ipg";
 333                         status = "disabled";
 334                 };
 335
 336                 lpuart3: serial@2980000 {
 337                         compatible = "fsl,ls1021a-lpuart";
 338                         reg = <0x2980000 0x1000>;
 339                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&clockgen 4 1>;
 341                         clock-names = "ipg";
 342                         status = "disabled";
 343                 };
 344
 345                 lpuart4: serial@2990000 {
 346                         compatible = "fsl,ls1021a-lpuart";
 347                         reg = <0x2990000 0x1000>;
 348                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 349                         clocks = <&clockgen 4 1>;
 350                         clock-names = "ipg";
 351                         status = "disabled";
 352                 };
 353
 354                 lpuart5: serial@29a0000 {
 355                         compatible = "fsl,ls1021a-lpuart";
 356                         reg = <0x29a0000 0x1000>;
 357                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 358                         clocks = <&clockgen 4 1>;
 359                         clock-names = "ipg";
 360                         status = "disabled";
 361                 };
 362
 363                 wdog0: watchdog@2ad0000 {
 364                         compatible = "fsl,imx21-wdt";
 365                         reg = <0x2ad0000 0x10000>;
 366                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 367                         clocks = <&clockgen 4 1>;
 368                         clock-names = "wdog-en";
 369                         big-endian;
 370                 };
 371
 372                 sai1: sai@2b50000 {
 373                         compatible = "fsl,vf610-sai";
 374                         reg = <0x2b50000 0x10000>;
 375                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&clockgen 4 1>;
 377                         clock-names = "sai";
 378                         dma-names = "tx", "rx";
 379                         dmas = <&edma0 1 47>,
 380                                <&edma0 1 46>;
 381                         big-endian;
 382                         status = "disabled";
 383                 };
 384
 385                 sai2: sai@2b60000 {
 386                         compatible = "fsl,vf610-sai";
 387                         reg = <0x2b60000 0x10000>;
 388                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&clockgen 4 1>;
 390                         clock-names = "sai";
 391                         dma-names = "tx", "rx";
 392                         dmas = <&edma0 1 45>,
 393                                <&edma0 1 44>;
 394                         big-endian;
 395                         status = "disabled";
 396                 };
 397
 398                 edma0: edma@2c00000 {
 399                         #dma-cells = <2>;
 400                         compatible = "fsl,vf610-edma";
 401                         reg = <0x2c00000 0x10000>,
 402                               <0x2c10000 0x10000>,
 403                               <0x2c20000 0x10000>;
 404                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 405                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 406                         interrupt-names = "edma-tx", "edma-err";
 407                         dma-channels = <32>;
 408                         big-endian;
 409                         clock-names = "dmamux0", "dmamux1";
 410                         clocks = <&clockgen 4 1>,
 411                                  <&clockgen 4 1>;
 412                 };
 413
 414                 enet0: ethernet@2d10000 {
 415                         compatible = "fsl,etsec2";
 416                         reg = <0x2d10000 0x1000>;
 417                         status = "disabled";
 418                 };
 419
 420                 enet1: ethernet@2d50000 {
 421                         compatible = "fsl,etsec2";
 422                         reg = <0x2d50000 0x1000>;
 423                         status = "disabled";
 424                 };
 425
 426                 enet2: ethernet@2d90000 {
 427                         compatible = "fsl,etsec2";
 428                         reg = <0x2d90000 0x1000>;
 429                         status = "disabled";
 430                 };
 431
 432                 mdio0: mdio@2d24000 {
 433                         compatible = "fsl,etsec2-mdio";
 434                         reg = <0x2d24000 0x4000>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                 };
 438
 439                 mdio1: mdio@2d64000 {
 440                         compatible = "fsl,etsec2-mdio";
 441                         reg = <0x2d64000 0x4000>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                 };
 445
 446                 usb@8600000 {
 447                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 448                         reg = <0x8600000 0x1000>;
 449                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 450                         dr_mode = "host";
 451                         phy_type = "ulpi";
 452                 };
 453
 454                 usb3@3100000 {
 455                         compatible = "fsl,layerscape-dwc3";
 456                         reg = <0x3100000 0x10000>;
 457                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 458                         dr_mode = "host";
 459                 };
 460
 461                 pcie@3400000 {
 462                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 463                         reg = <0x03400000 0x20000   /* dbi registers */
 464                                0x01570000 0x10000   /* pf controls registers */
 465                                0x24000000 0x20000>; /* configuration space */
 466                         reg-names = "dbi", "ctrl", "config";
 467                         big-endian;
 468                         #address-cells = <3>;
 469                         #size-cells = <2>;
 470                         device_type = "pci";
 471                         bus-range = <0x0 0xff>;
 472                         ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000   /* downstream I/O */
 473                                   0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
 474                 };
 475
 476                 pcie@3500000 {
 477                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 478                         reg = <0x03500000 0x10000    /* dbi registers */
 479                                0x01570000 0x10000    /* pf controls registers */
 480                                0x34000000 0x20000>;  /* configuration space */
 481                         reg-names = "dbi", "ctrl", "config";
 482                         big-endian;
 483                         #address-cells = <3>;
 484                         #size-cells = <2>;
 485                         device_type = "pci";
 486                         num-lanes = <2>;
 487                         bus-range = <0x0 0xff>;
 488                         ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
 489                                   0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
 490                 };
 491
 492                 sata: sata@3200000 {
 493                         compatible = "fsl,ls1021a-ahci";
 494                         reg = <0x3200000 0x10000 0x20220520 0x4>;
 495                         reg-names = "ahci", "sata-ecc";
 496                         interrupts = <0 101 4>;
 497                         status = "disabled";
 498                 };
 499         };
 500 };