2 * Freescale ls1021a QDS board device tree source
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include "ls1021a.dtsi"
13 model = "LS1021A QDS Board";
16 enet0_rgmii_phy = &rgmii_phy1;
17 enet1_rgmii_phy = &rgmii_phy2;
18 enet2_rgmii_phy = &rgmii_phy3;
19 enet0_sgmii_phy = &sgmii_phy1c;
20 enet1_sgmii_phy = &sgmii_phy1d;
28 dspiflash: at45db021d@0 {
31 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
32 spi-max-frequency = <16000000>;
53 compatible = "dallas,ds3232";
55 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
65 compatible = "ti,ina220";
67 shunt-resistor = <1000>;
71 compatible = "ti,ina220";
73 shunt-resistor = <1000>;
83 compatible = "atmel,24c512";
88 compatible = "atmel,24c512";
93 compatible = "adi,adt7461a";
101 #address-cells = <2>;
103 /* NOR, NAND Flashes and FPGA on board */
104 ranges = <0x0 0x0 0x60000000 0x08000000
105 0x2 0x0 0x7e800000 0x00010000
106 0x3 0x0 0x7fb00000 0x00000100>;
110 #address-cells = <1>;
112 compatible = "cfi-flash";
113 reg = <0x0 0x0 0x8000000>;
118 fpga: board-control@3,0 {
119 #address-cells = <1>;
121 compatible = "simple-bus";
122 reg = <0x3 0x0 0x0000100>;
125 ranges = <0 3 0 0x100>;
128 compatible = "mdio-mux-mmioreg";
129 mdio-parent-bus = <&mdio0>;
130 #address-cells = <1>;
132 reg = <0x54 1>; /* BRDCFG4 */
133 mux-mask = <0xe0>; /* EMI1[2:0] */
136 ls1021amdio0: mdio@0 {
138 #address-cells = <1>;
140 rgmii_phy1: ethernet-phy@1 {
145 ls1021amdio1: mdio@20 {
147 #address-cells = <1>;
149 rgmii_phy2: ethernet-phy@2 {
154 ls1021amdio2: mdio@40 {
156 #address-cells = <1>;
158 rgmii_phy3: ethernet-phy@3 {
163 ls1021amdio3: mdio@60 {
165 #address-cells = <1>;
167 sgmii_phy1c: ethernet-phy@1c {
172 ls1021amdio4: mdio@80 {
174 #address-cells = <1>;
176 sgmii_phy1d: ethernet-phy@1d {
191 device_type = "tbi-phy";