arch/arm/dts/ls1021a-qds.dts

   1 /*
   2  * Freescale ls1021a QDS board device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /dts-v1/;
  10 #include "ls1021a.dtsi"
  11
  12 / {
  13         model = "LS1021A QDS Board";
  14
  15         aliases {
  16                 enet0_rgmii_phy = &rgmii_phy1;
  17                 enet1_rgmii_phy = &rgmii_phy2;
  18                 enet2_rgmii_phy = &rgmii_phy3;
  19                 enet0_sgmii_phy = &sgmii_phy1c;
  20                 enet1_sgmii_phy = &sgmii_phy1d;
  21                 spi0 = &qspi;
  22                 spi1 = &dspi0;
  23         };
  24 };
  25
  26 &dspi0 {
  27         bus-num = <0>;
  28         status = "okay";
  29
  30         dspiflash: at45db021d@0 {
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 compatible = "atmel,dataflash";
  34                 spi-max-frequency = <16000000>;
  35                 spi-cpol;
  36                 spi-cpha;
  37                 reg = <0>;
  38         };
  39 };
  40
  41 &qspi {
  42         bus-num = <0>;
  43         status = "okay";
  44
  45         qflash0: s25fl128s@0 {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "spi-flash";
  49                 spi-max-frequency = <20000000>;
  50                 reg = <0>;
  51         };
  52 };
  53
  54 &i2c0 {
  55         status = "okay";
  56
  57         pca9547: mux@77 {
  58                 reg = <0x77>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 i2c@0 {
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65                         reg = <0x0>;
  66
  67                         ds3232: rtc@68 {
  68                                 compatible = "dallas,ds3232";
  69                                 reg = <0x68>;
  70                                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  71                         };
  72                 };
  73
  74                 i2c@2 {
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         reg = <0x2>;
  78
  79                         ina220@40 {
  80                                 compatible = "ti,ina220";
  81                                 reg = <0x40>;
  82                                 shunt-resistor = <1000>;
  83                         };
  84
  85                         ina220@41 {
  86                                 compatible = "ti,ina220";
  87                                 reg = <0x41>;
  88                                 shunt-resistor = <1000>;
  89                         };
  90                 };
  91
  92                 i2c@3 {
  93                         #address-cells = <1>;
  94                         #size-cells = <0>;
  95                         reg = <0x3>;
  96
  97                         eeprom@56 {
  98                                 compatible = "atmel,24c512";
  99                                 reg = <0x56>;
 100                         };
 101
 102                         eeprom@57 {
 103                                 compatible = "atmel,24c512";
 104                                 reg = <0x57>;
 105                         };
 106
 107                         adt7461a@4c {
 108                                 compatible = "adi,adt7461a";
 109                                 reg = <0x4c>;
 110                         };
 111                 };
 112         };
 113 };
 114
 115 &ifc {
 116         #address-cells = <2>;
 117         #size-cells = <1>;
 118         /* NOR, NAND Flashes and FPGA on board */
 119         ranges = <0x0 0x0 0x60000000 0x08000000
 120                   0x2 0x0 0x7e800000 0x00010000
 121                   0x3 0x0 0x7fb00000 0x00000100>;
 122         status = "okay";
 123
 124         nor@0,0 {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 compatible = "cfi-flash";
 128                 reg = <0x0 0x0 0x8000000>;
 129                 bank-width = <2>;
 130                 device-width = <1>;
 131         };
 132
 133         fpga: board-control@3,0 {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 compatible = "simple-bus";
 137                 reg = <0x3 0x0 0x0000100>;
 138                 bank-width = <1>;
 139                 device-width = <1>;
 140                 ranges = <0 3 0 0x100>;
 141
 142                 mdio-mux-emi1 {
 143                         compatible = "mdio-mux-mmioreg";
 144                         mdio-parent-bus = <&mdio0>;
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         reg = <0x54 1>; /* BRDCFG4 */
 148                         mux-mask = <0xe0>; /* EMI1[2:0] */
 149
 150                         /* Onboard PHYs */
 151                         ls1021amdio0: mdio@0 {
 152                                 reg = <0>;
 153                                 #address-cells = <1>;
 154                                 #size-cells = <0>;
 155                                 rgmii_phy1: ethernet-phy@1 {
 156                                         reg = <0x1>;
 157                                 };
 158                         };
 159
 160                         ls1021amdio1: mdio@20 {
 161                                 reg = <0x20>;
 162                                 #address-cells = <1>;
 163                                 #size-cells = <0>;
 164                                 rgmii_phy2: ethernet-phy@2 {
 165                                         reg = <0x2>;
 166                                 };
 167                         };
 168
 169                         ls1021amdio2: mdio@40 {
 170                                 reg = <0x40>;
 171                                 #address-cells = <1>;
 172                                 #size-cells = <0>;
 173                                 rgmii_phy3: ethernet-phy@3 {
 174                                         reg = <0x3>;
 175                                 };
 176                         };
 177
 178                         ls1021amdio3: mdio@60 {
 179                                 reg = <0x60>;
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182                                 sgmii_phy1c: ethernet-phy@1c {
 183                                         reg = <0x1c>;
 184                                 };
 185                         };
 186
 187                         ls1021amdio4: mdio@80 {
 188                                 reg = <0x80>;
 189                                 #address-cells = <1>;
 190                                 #size-cells = <0>;
 191                                 sgmii_phy1d: ethernet-phy@1d {
 192                                         reg = <0x1d>;
 193                                 };
 194                         };
 195                 };
 196         };
 197 };
 198
 199 &lpuart0 {
 200         status = "okay";
 201 };
 202
 203 &mdio0 {
 204         tbi0: tbi-phy@8 {
 205                 reg = <0x8>;
 206                 device_type = "tbi-phy";
 207         };
 208 };
 209
 210 &uart0 {
 211         status = "okay";
 212 };
 213
 214 &uart1 {
 215         status = "okay";
 216 };