1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
9 #include "skeleton.dtsi"
12 model = "Texas Instruments Keystone 2 SoC";
15 interrupt-parent = <&gic>;
32 reg = <0x80000000 0x40000000>;
35 gic: interrupt-controller {
36 compatible = "arm,cortex-a15-gic";
37 #interrupt-cells = <3>;
39 reg = <0x02561000 0x1000>,
43 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
44 IRQ_TYPE_LEVEL_HIGH)>;
48 compatible = "arm,armv7-timer";
51 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
53 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
55 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
57 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
61 compatible = "arm,cortex-a15-pmu";
62 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
63 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
64 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
65 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
71 compatible = "ti,keystone","simple-bus";
72 interrupt-parent = <&gic>;
75 pllctrl: pll-controller@02310000 {
76 compatible = "ti,keystone-pllctrl", "syscon";
77 reg = <0x02310000 0x200>;
80 devctrl: device-state-control@02620000 {
81 compatible = "ti,keystone-devctrl", "syscon";
82 reg = <0x02620000 0x1000>;
85 rstctrl: reset-controller {
86 compatible = "ti,keystone-reset";
87 ti,syscon-pll = <&pllctrl 0xe4>;
88 ti,syscon-dev = <&devctrl 0x328>;
92 /include/ "keystone-clocks.dtsi"
94 uart0: serial@02530c00 {
95 compatible = "ns16550a";
96 current-speed = <115200>;
99 reg = <0x02530c00 0x100>;
100 clocks = <&clkuart0>;
101 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
104 uart1: serial@02531000 {
105 compatible = "ns16550a";
106 current-speed = <115200>;
109 reg = <0x02531000 0x100>;
110 clocks = <&clkuart1>;
111 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
115 compatible = "ti,davinci-i2c";
116 reg = <0x02530000 0x400>;
117 clock-frequency = <100000>;
119 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
120 #address-cells = <1>;
125 compatible = "ti,davinci-i2c";
126 reg = <0x02530400 0x400>;
127 clock-frequency = <100000>;
129 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
130 #address-cells = <1>;
135 compatible = "ti,davinci-i2c";
136 reg = <0x02530800 0x400>;
137 clock-frequency = <100000>;
139 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
140 #address-cells = <1>;
145 compatible = "ti,dm6441-spi";
146 reg = <0x21000400 0x200>;
148 ti,davinci-spi-intr-line = <0>;
149 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
151 #address-cells = <1>;
156 compatible = "ti,dm6441-spi";
157 reg = <0x21000600 0x200>;
159 ti,davinci-spi-intr-line = <0>;
160 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
162 #address-cells = <1>;
167 compatible = "ti,dm6441-spi";
168 reg = <0x21000800 0x200>;
170 ti,davinci-spi-intr-line = <0>;
171 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
173 #address-cells = <1>;
177 usb_phy: usb_phy@2620738 {
178 compatible = "ti,keystone-usbphy";
179 #address-cells = <1>;
181 reg = <0x2620738 24>;
186 compatible = "ti,keystone-dwc3";
187 #address-cells = <1>;
189 reg = <0x2680000 0x10000>;
192 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
199 compatible = "synopsys,dwc3";
200 reg = <0x2690000 0x70000>;
201 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
202 usb-phy = <&usb_phy>, <&usb_phy>;
207 compatible = "ti,keystone-wdt","ti,davinci-wdt";
208 reg = <0x022f0080 0x80>;
209 clocks = <&clkwdtimer0>;
212 clock_event: timer@22f0000 {
213 compatible = "ti,keystone-timer";
214 reg = <0x022f0000 0x80>;
215 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
216 clocks = <&clktimer15>;
219 gpio0: gpio@260bf00 {
220 compatible = "ti,keystone-gpio";
221 reg = <0x0260bf00 0x100>;
224 /* HW Interrupts mapped to GPIO pins */
225 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
226 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
227 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
228 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
229 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
230 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
231 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
232 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
233 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
234 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
235 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
236 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
237 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
238 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
239 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
240 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
241 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
242 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
243 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
244 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
245 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
246 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
247 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
249 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
250 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
251 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
252 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
254 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
256 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
258 clock-names = "gpio";
260 ti,davinci-gpio-unbanked = <32>;
263 aemif: aemif@21000A00 {
264 compatible = "ti,keystone-aemif", "ti,davinci-aemif";
265 #address-cells = <2>;
267 clocks = <&clkaemif>;
268 clock-names = "aemif";
271 reg = <0x21000A00 0x00000100>;
272 ranges = <0 0 0x30000000 0x10000000
273 1 0 0x21000A00 0x00000100>;
276 kirq0: keystone_irq@26202a0 {
277 compatible = "ti,keystone-irq";
278 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
279 interrupt-controller;
280 #interrupt-cells = <1>;
281 ti,syscon-dev = <&devctrl 0x2a0>;
284 pcie0: pcie@21800000 {
285 compatible = "ti,keystone-pcie", "snps,dw-pcie";
287 clock-names = "pcie";
288 #address-cells = <3>;
290 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
291 ranges = <0x81000000 0 0 0x23250000 0 0x4000
292 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
298 #interrupt-cells = <1>;
299 interrupt-map-mask = <0 0 0 7>;
300 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
301 <0 0 0 2 &pcie_intc0 1>, /* INT B */
302 <0 0 0 3 &pcie_intc0 2>, /* INT C */
303 <0 0 0 4 &pcie_intc0 3>; /* INT D */
305 pcie_msi_intc0: msi-interrupt-controller {
306 interrupt-controller;
307 #interrupt-cells = <1>;
308 interrupt-parent = <&gic>;
309 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
310 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
311 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
313 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
314 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
315 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
316 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
319 pcie_intc0: legacy-interrupt-controller {
320 interrupt-controller;
321 #interrupt-cells = <1>;
322 interrupt-parent = <&gic>;
323 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
325 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
326 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;