1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Edison SoC specific device tree
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
9 mainpllclk: mainpllclk@2310110 {
11 compatible = "ti,keystone,main-pll-clock";
12 clocks = <&refclksys>;
13 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
14 reg-names = "control", "multiplier", "post-divider";
17 papllclk: papllclk@2620358 {
19 compatible = "ti,keystone,pll-clock";
20 clocks = <&refclkpass>;
21 clock-output-names = "papllclk";
23 reg-names = "control";
26 ddr3apllclk: ddr3apllclk@2620360 {
28 compatible = "ti,keystone,pll-clock";
29 clocks = <&refclkddr3a>;
30 clock-output-names = "ddr-3a-pll-clk";
32 reg-names = "control";
37 compatible = "ti,keystone,psc-clock";
38 clocks = <&chipclk16>;
39 clock-output-names = "usb1";
40 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
41 reg-names = "control", "domain";
45 clkhyperlink0: clkhyperlink0 {
47 compatible = "ti,keystone,psc-clock";
48 clocks = <&chipclk12>;
49 clock-output-names = "hyperlink-0";
50 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
51 reg-names = "control", "domain";
57 compatible = "ti,keystone,psc-clock";
58 clocks = <&chipclk12>;
59 clock-output-names = "pcie1";
60 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
61 reg-names = "control", "domain";
67 compatible = "ti,keystone,psc-clock";
68 clocks = <&chipclk13>;
69 clock-output-names = "xge";
70 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
71 reg-names = "control", "domain";