arch/arm/dts/k3-j721e-r5-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j721e.dtsi"
   9 #include "k3-j721e-ddr-sk-lp4-4266.dtsi"
  10 #include "k3-j721e-ddr.dtsi"
  11
  12 / {
  13         model = "Texas Instruments J721E SK R5";
  14
  15         aliases {
  16                 remoteproc0 = &sysctrler;
  17                 remoteproc1 = &a72_0;
  18         };
  19
  20         chosen {
  21                 stdout-path = "serial2:115200n8";
  22                 tick-timer = &timer1;
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 /* 4G RAM */
  28                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  29                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  30         };
  31
  32         reserved_memory: reserved-memory {
  33                 #address-cells = <2>;
  34                 #size-cells = <2>;
  35                 ranges;
  36
  37                 secure_ddr: optee@9e800000 {
  38                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  39                         alignment = <0x1000>;
  40                         no-map;
  41                 };
  42
  43                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x00 0xa0000000 0x00 0x100000>;
  46                         no-map;
  47                 };
  48
  49                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  50                         compatible = "shared-dma-pool";
  51                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  52                         no-map;
  53                 };
  54
  55                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  56                         compatible = "shared-dma-pool";
  57                         reg = <0x00 0xa1000000 0x00 0x100000>;
  58                         no-map;
  59                 };
  60
  61                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  62                         compatible = "shared-dma-pool";
  63                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  64                         no-map;
  65                 };
  66
  67                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  68                         compatible = "shared-dma-pool";
  69                         reg = <0x00 0xa2000000 0x00 0x100000>;
  70                         no-map;
  71                 };
  72
  73                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  74                         compatible = "shared-dma-pool";
  75                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  76                         no-map;
  77                 };
  78
  79                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  80                         compatible = "shared-dma-pool";
  81                         reg = <0x00 0xa3000000 0x00 0x100000>;
  82                         no-map;
  83                 };
  84
  85                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  86                         compatible = "shared-dma-pool";
  87                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  88                         no-map;
  89                 };
  90
  91                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
  92                         compatible = "shared-dma-pool";
  93                         reg = <0x00 0xa4000000 0x00 0x100000>;
  94                         no-map;
  95                 };
  96
  97                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
  98                         compatible = "shared-dma-pool";
  99                         reg = <0x00 0xa4100000 0x00 0xf00000>;
 100                         no-map;
 101                 };
 102
 103                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
 104                         compatible = "shared-dma-pool";
 105                         reg = <0x00 0xa5000000 0x00 0x100000>;
 106                         no-map;
 107                 };
 108
 109                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
 110                         compatible = "shared-dma-pool";
 111                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 112                         no-map;
 113                 };
 114
 115                 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
 116                         compatible = "shared-dma-pool";
 117                         reg = <0x00 0xa6000000 0x00 0x100000>;
 118                         no-map;
 119                 };
 120
 121                 c66_0_memory_region: c66-memory@a6100000 {
 122                         compatible = "shared-dma-pool";
 123                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 124                         no-map;
 125                 };
 126
 127                 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
 128                         compatible = "shared-dma-pool";
 129                         reg = <0x00 0xa7000000 0x00 0x100000>;
 130                         no-map;
 131                 };
 132
 133                 c66_1_memory_region: c66-memory@a7100000 {
 134                         compatible = "shared-dma-pool";
 135                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 136                         no-map;
 137                 };
 138
 139                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 140                         compatible = "shared-dma-pool";
 141                         reg = <0x00 0xa8000000 0x00 0x100000>;
 142                         no-map;
 143                 };
 144
 145                 c71_0_memory_region: c71-memory@a8100000 {
 146                         compatible = "shared-dma-pool";
 147                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 148                         no-map;
 149                 };
 150
 151                 rtos_ipc_memory_region: ipc-memories@aa000000 {
 152                         reg = <0x00 0xaa000000 0x00 0x01c00000>;
 153                         alignment = <0x1000>;
 154                         no-map;
 155                 };
 156         };
 157
 158         a72_0: a72@0 {
 159                 compatible = "ti,am654-rproc";
 160                 reg = <0x0 0x00a90000 0x0 0x10>;
 161                 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
 162                                 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
 163                                 <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
 164                 resets = <&k3_reset 202 0>;
 165                 clocks = <&k3_clks 61 1>;
 166                 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
 167                 assigned-clock-rates = <2000000000>, <200000000>;
 168                 ti,sci = <&dmsc>;
 169                 ti,sci-proc-id = <32>;
 170                 ti,sci-host-id = <10>;
 171                 bootph-pre-ram;
 172         };
 173
 174         clk_200mhz: dummy_clock_200mhz {
 175                 compatible = "fixed-clock";
 176                 #clock-cells = <0>;
 177                 clock-frequency = <200000000>;
 178                 bootph-pre-ram;
 179         };
 180
 181         clk_19_2mhz: dummy_clock_19_2mhz {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <19200000>;
 185                 bootph-pre-ram;
 186         };
 187 };
 188
 189 &cbass_mcu_wakeup {
 190         mcu_secproxy: secproxy@28380000 {
 191                 bootph-pre-ram;
 192                 compatible = "ti,am654-secure-proxy";
 193                 reg = <0x0 0x2a380000 0x0 0x80000>,
 194                       <0x0 0x2a400000 0x0 0x80000>,
 195                       <0x0 0x2a480000 0x0 0x80000>;
 196                 reg-names = "rt", "scfg", "target_data";
 197                 #mbox-cells = <1>;
 198         };
 199
 200         sysctrler: sysctrler {
 201                 bootph-pre-ram;
 202                 compatible = "ti,am654-system-controller";
 203                 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
 204                 mbox-names = "tx", "rx";
 205         };
 206
 207         wkup_vtm0: wkup_vtm@42040000 {
 208                 compatible = "ti,am654-vtm", "ti,j721e-avs";
 209                 reg = <0x0 0x42040000 0x0 0x330>;
 210                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 211                 #thermal-sensor-cells = <1>;
 212         };
 213
 214         dm_tifs: dm-tifs {
 215                 compatible = "ti,j721e-dm-sci";
 216                 ti,host-id = <3>;
 217                 ti,secure-host;
 218                 mbox-names = "rx", "tx";
 219                 mboxes= <&mcu_secproxy 21>,
 220                                 <&mcu_secproxy 23>;
 221                 bootph-pre-ram;
 222         };
 223 };
 224
 225 &cbass_main {
 226         main_esm: esm@700000 {
 227                 compatible = "ti,j721e-esm";
 228                 reg = <0x0 0x700000 0x0 0x1000>;
 229                 ti,esm-pins = <344>, <345>;
 230                 bootph-pre-ram;
 231         };
 232 };
 233
 234 &dmsc {
 235         mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
 236         mbox-names = "tx", "rx", "notify";
 237         ti,host-id = <4>;
 238         ti,secure-host;
 239 };
 240
 241 &wkup_pmx0 {
 242         wkup_uart0_pins_default: wkup_uart0_pins_default {
 243                 bootph-pre-ram;
 244                 pinctrl-single,pins = <
 245                         J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
 246                         J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
 247                 >;
 248         };
 249
 250         mcu_uart0_pins_default: mcu_uart0_pins_default {
 251                 bootph-pre-ram;
 252                 pinctrl-single,pins = <
 253                         J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
 254                         J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
 255                         J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
 256                         J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
 257                 >;
 258         };
 259
 260         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
 261                 pinctrl-single,pins = <
 262                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
 263                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
 264                 >;
 265         };
 266
 267         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
 268                 pinctrl-single,pins = <
 269                         J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
 270                         J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
 271                         J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
 272                         J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
 273                         J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
 274                         J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
 275                         J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
 276                         J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
 277                         J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
 278                         J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
 279                         J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
 280                 >;
 281         };
 282
 283         mcu_i2c0_pins_default: mcu_i2c0_pins_default {
 284                 pinctrl-single,pins = <
 285                         J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
 286                         J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
 287                 >;
 288         };
 289 };
 290
 291 &main_pmx0 {
 292         main_uart0_pins_default: main_uart0_pins_default {
 293                 bootph-pre-ram;
 294                 pinctrl-single,pins = <
 295                         J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
 296                         J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
 297                         J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
 298                         J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
 299                 >;
 300         };
 301
 302         main_usbss0_pins_default: main_usbss0_pins_default {
 303                 pinctrl-single,pins = <
 304                         J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
 305                         J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 306                 >;
 307         };
 308
 309         main_usbss1_pins_default: main-usbss1-pins-default {
 310                 pinctrl-single,pins = <
 311                         J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
 312                 >;
 313         };
 314
 315         main_mmc1_pins_default: main_mmc1_pins_default {
 316                 pinctrl-single,pins = <
 317                         J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
 318                         J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
 319                         J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
 320                         J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
 321                         J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
 322                         J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
 323                         J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
 324                         J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
 325                 >;
 326         };
 327
 328         main_i2c0_pins_default: main-i2c0-pins-default {
 329                 pinctrl-single,pins = <
 330                         J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
 331                         J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
 332                 >;
 333         };
 334
 335         main_i2c1_pins_default: main-i2c1-pins-default {
 336                 pinctrl-single,pins = <
 337                         J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
 338                         J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
 339                 >;
 340         };
 341
 342         main_i2c2_pins_default: main-i2c2-pins-default {
 343                 pinctrl-single,pins = <
 344                         J721E_IOPAD(0x158, PIN_INPUT_PULLUP, 2) /* (U23) RGMII5_TX_CTL.I2C2_SCL */
 345                         J721E_IOPAD(0x15c, PIN_INPUT_PULLUP, 2) /* (U26) RGMII5_RX_CTL.I2C2_SDA */
 346                 >;
 347         };
 348
 349         main_i2c3_pins_default: main-i2c3-pins-default {
 350                 pinctrl-single,pins = <
 351                         J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
 352                         J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
 353                 >;
 354         };
 355
 356         main_i2c5_pins_default: main-i2c5-pins-default {
 357                 pinctrl-single,pins = <
 358                         J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
 359                         J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
 360                 >;
 361         };
 362 };
 363
 364 &wkup_uart0 {
 365         bootph-pre-ram;
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&wkup_uart0_pins_default>;
 368         status = "okay";
 369 };
 370
 371 &mcu_uart0 {
 372         /delete-property/ power-domains;
 373         /delete-property/ clocks;
 374         /delete-property/ clock-names;
 375         pinctrl-names = "default";
 376         pinctrl-0 = <&mcu_uart0_pins_default>;
 377         status = "okay";
 378         clock-frequency = <48000000>;
 379 };
 380
 381 &main_uart0 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&main_uart0_pins_default>;
 384         status = "okay";
 385         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 386 };
 387
 388 &main_sdhci0 {
 389         status = "disabled";
 390 };
 391
 392 &main_sdhci1 {
 393         /delete-property/ power-domains;
 394         /delete-property/ assigned-clocks;
 395         /delete-property/ assigned-clock-parents;
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&main_mmc1_pins_default>;
 398         clock-names = "clk_xin";
 399         clocks = <&clk_200mhz>;
 400         ti,driver-strength-ohm = <50>;
 401 };
 402
 403 &wkup_i2c0 {
 404         bootph-pre-ram;
 405         tps659412: tps659412@48 {
 406                 reg = <0x48>;
 407                 compatible = "ti,tps659412";
 408                 bootph-pre-ram;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&wkup_i2c0_pins_default>;
 411                 clock-frequency = <400000>;
 412
 413                 regulators: regulators {
 414                         bootph-pre-ram;
 415                         /* 3 Phase Buck */
 416                         buck123_reg: buck123 {
 417                                 /* VDD_CPU */
 418                                 regulator-name = "buck123";
 419                                 regulator-min-microvolt = <800000>;
 420                                 regulator-max-microvolt = <1250000>;
 421                                 regulator-always-on;
 422                                 regulator-boot-on;
 423                                 bootph-pre-ram;
 424                         };
 425                 };
 426         };
 427 };
 428
 429 &wkup_vtm0 {
 430         vdd-supply-2 = <&buck123_reg>;
 431         bootph-pre-ram;
 432 };
 433
 434 &usbss0 {
 435         /delete-property/ power-domains;
 436         /delete-property/ assigned-clocks;
 437         /delete-property/ assigned-clock-parents;
 438         clocks = <&clk_19_2mhz>;
 439         clock-names = "usb2_refclk";
 440         pinctrl-names = "default";
 441         pinctrl-0 = <&main_usbss0_pins_default>;
 442         ti,vbus-divider;
 443 };
 444
 445 &usbss1 {
 446         /delete-property/ power-domains;
 447         /delete-property/ assigned-clocks;
 448         /delete-property/ assigned-clock-parents;
 449         clocks = <&clk_19_2mhz>;
 450         clock-names = "usb2_refclk";
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&main_usbss1_pins_default>;
 453 };
 454
 455 &main_i2c0 {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&main_i2c0_pins_default>;
 458         clock-frequency = <400000>;
 459 };
 460
 461 &ospi0 {
 462         pinctrl-names = "default";
 463         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 464
 465         reg = <0x0 0x47040000 0x0 0x100>,
 466               <0x0 0x50000000 0x0 0x8000000>;
 467
 468         flash@0{
 469                 compatible = "jedec,spi-nor";
 470                 reg = <0x0>;
 471                 spi-tx-bus-width = <8>;
 472                 spi-rx-bus-width = <8>;
 473                 spi-max-frequency = <25000000>;
 474                 cdns,tshsl-ns = <60>;
 475                 cdns,tsd2d-ns = <60>;
 476                 cdns,tchsh-ns = <60>;
 477                 cdns,tslch-ns = <60>;
 478                 cdns,read-delay = <4>;
 479                 cdns,phy-mode;
 480                 #address-cells = <1>;
 481                 #size-cells = <1>;
 482         };
 483 };
 484
 485 &ospi1 {
 486         status = "disabled";
 487 };
 488
 489 &mcu_ringacc {
 490         ti,sci = <&dm_tifs>;
 491 };
 492
 493 &mcu_udmap {
 494         ti,sci = <&dm_tifs>;
 495 };
 496
 497 &mailbox0_cluster0 {
 498         interrupts = <436>;
 499
 500         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 501                 ti,mbox-rx = <0 0 0>;
 502                 ti,mbox-tx = <1 0 0>;
 503         };
 504
 505         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 506                 ti,mbox-rx = <2 0 0>;
 507                 ti,mbox-tx = <3 0 0>;
 508         };
 509 };
 510
 511 &mailbox0_cluster1 {
 512         interrupts = <432>;
 513
 514         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 515                 ti,mbox-rx = <0 0 0>;
 516                 ti,mbox-tx = <1 0 0>;
 517         };
 518
 519         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 520                 ti,mbox-rx = <2 0 0>;
 521                 ti,mbox-tx = <3 0 0>;
 522         };
 523 };
 524
 525 &mailbox0_cluster2 {
 526         interrupts = <428>;
 527
 528         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 529                 ti,mbox-rx = <0 0 0>;
 530                 ti,mbox-tx = <1 0 0>;
 531         };
 532
 533         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 534                 ti,mbox-rx = <2 0 0>;
 535                 ti,mbox-tx = <3 0 0>;
 536         };
 537 };
 538
 539 &mailbox0_cluster3 {
 540         interrupts = <424>;
 541
 542         mbox_c66_0: mbox-c66-0 {
 543                 ti,mbox-rx = <0 0 0>;
 544                 ti,mbox-tx = <1 0 0>;
 545         };
 546
 547         mbox_c66_1: mbox-c66-1 {
 548                 ti,mbox-rx = <2 0 0>;
 549                 ti,mbox-tx = <3 0 0>;
 550         };
 551 };
 552
 553 &mailbox0_cluster4 {
 554         interrupts = <420>;
 555
 556         mbox_c71_0: mbox-c71-0 {
 557                 ti,mbox-rx = <0 0 0>;
 558                 ti,mbox-tx = <1 0 0>;
 559         };
 560 };
 561
 562 &mailbox0_cluster5 {
 563         status = "disabled";
 564 };
 565
 566 &mailbox0_cluster6 {
 567         status = "disabled";
 568 };
 569
 570 &mailbox0_cluster7 {
 571         status = "disabled";
 572 };
 573
 574 &mailbox0_cluster8 {
 575         status = "disabled";
 576 };
 577
 578 &mailbox0_cluster9 {
 579         status = "disabled";
 580 };
 581
 582 &mailbox0_cluster10 {
 583         status = "disabled";
 584 };
 585
 586 &mailbox0_cluster11 {
 587         status = "disabled";
 588 };
 589
 590 &mcu_r5fss0_core0 {
 591         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 592         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 593                         <&mcu_r5fss0_core0_memory_region>;
 594 };
 595
 596 &mcu_r5fss0_core1 {
 597         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 598         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 599                         <&mcu_r5fss0_core1_memory_region>;
 600 };
 601
 602 &main_r5fss0_core0 {
 603         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 604         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 605                         <&main_r5fss0_core0_memory_region>;
 606 };
 607
 608 &main_r5fss0_core1 {
 609         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 610         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 611                         <&main_r5fss0_core1_memory_region>;
 612 };
 613
 614 &main_r5fss1_core0 {
 615         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 616         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 617                         <&main_r5fss1_core0_memory_region>;
 618 };
 619
 620 &main_r5fss1_core1 {
 621         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 622         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 623                         <&main_r5fss1_core1_memory_region>;
 624 };
 625
 626 &c66_0 {
 627         mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 628         memory-region = <&c66_0_dma_memory_region>,
 629                         <&c66_0_memory_region>;
 630 };
 631
 632 &c66_1 {
 633         mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 634         memory-region = <&c66_1_dma_memory_region>,
 635                         <&c66_1_memory_region>;
 636 };
 637
 638 &c71_0 {
 639         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 640         memory-region = <&c71_0_dma_memory_region>,
 641                         <&c71_0_memory_region>;
 642 };
 643
 644 /* EEPROM might be read before SYSFW is available */
 645 &wkup_i2c0 {
 646         /delete-property/ power-domains;
 647 };