arch/arm/dts/k3-j721e-mcu-wakeup.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 &cbass_mcu_wakeup {
   9         dmsc: dmsc@44083000 {
  10                 compatible = "ti,k2g-sci";
  11                 ti,host-id = <12>;
  12
  13                 mbox-names = "rx", "tx";
  14
  15                 mboxes= <&secure_proxy_main 11>,
  16                         <&secure_proxy_main 13>;
  17
  18                 reg-names = "debug_messages";
  19                 reg = <0x00 0x44083000 0x0 0x1000>;
  20
  21                 k3_pds: power-controller {
  22                         compatible = "ti,sci-pm-domain";
  23                         #power-domain-cells = <2>;
  24                 };
  25
  26                 k3_clks: clocks {
  27                         compatible = "ti,k2g-sci-clk";
  28                         #clock-cells = <2>;
  29                         ti,scan-clocks-from-dt;
  30                 };
  31
  32                 k3_reset: reset-controller {
  33                         compatible = "ti,sci-reset";
  34                         #reset-cells = <2>;
  35                 };
  36         };
  37
  38         mcu_conf: syscon@40f00000 {
  39                 compatible = "syscon", "simple-mfd";
  40                 reg = <0x0 0x40f00000 0x0 0x20000>;
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 ranges = <0x0 0x0 0x40f00000 0x20000>;
  44
  45                 phy_gmii_sel: phy@4040 {
  46                         compatible = "ti,am654-phy-gmii-sel";
  47                         reg = <0x4040 0x4>;
  48                         #phy-cells = <1>;
  49                 };
  50         };
  51
  52         wkup_pmx0: pinmux@4301c000 {
  53                 compatible = "pinctrl-single";
  54                 /* Proxy 0 addressing */
  55                 reg = <0x00 0x4301c000 0x00 0x178>;
  56                 #pinctrl-cells = <1>;
  57                 pinctrl-single,register-width = <32>;
  58                 pinctrl-single,function-mask = <0xffffffff>;
  59         };
  60
  61         wkup_uart0: serial@42300000 {
  62                 compatible = "ti,j721e-uart", "ti,am654-uart";
  63                 reg = <0x00 0x42300000 0x00 0x100>;
  64                 reg-shift = <2>;
  65                 reg-io-width = <4>;
  66                 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  67                 clock-frequency = <48000000>;
  68                 current-speed = <115200>;
  69                 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  70                 clocks = <&k3_clks 287 0>;
  71                 clock-names = "fclk";
  72         };
  73
  74         wkup_i2c0: i2c@42120000 {
  75                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  76                 reg = <0x0 0x42120000 0x0 0x100>;
  77                 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
  78                 #address-cells = <1>;
  79                 #size-cells = <0>;
  80                 clock-names = "fck";
  81                 clocks = <&k3_clks 197 0>;
  82                 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
  83         };
  84
  85         mcu_uart0: serial@40a00000 {
  86                 compatible = "ti,j721e-uart", "ti,am654-uart";
  87                 reg = <0x00 0x40a00000 0x00 0x100>;
  88                 reg-shift = <2>;
  89                 reg-io-width = <4>;
  90                 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  91                 clock-frequency = <96000000>;
  92                 current-speed = <115200>;
  93                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  94                 clocks = <&k3_clks 149 0>;
  95                 clock-names = "fclk";
  96         };
  97
  98         mcu_r5fss0: r5fss@41000000 {
  99                 compatible = "ti,j721e-r5fss";
 100                 lockstep-mode = <1>;
 101                 #address-cells = <1>;
 102                 #size-cells = <1>;
 103                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
 104                          <0x41400000 0x00 0x41400000 0x20000>;
 105                 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 106
 107                 mcu_r5fss0_core0: r5f@41000000 {
 108                         compatible = "ti,j721e-r5f";
 109                         reg = <0x41000000 0x00008000>,
 110                               <0x41010000 0x00008000>;
 111                         reg-names = "atcm", "btcm";
 112                         ti,sci = <&dmsc>;
 113                         ti,sci-dev-id = <250>;
 114                         ti,sci-proc-ids = <0x01 0xFF>;
 115                         resets = <&k3_reset 250 1>;
 116                         atcm-enable = <1>;
 117                         btcm-enable = <1>;
 118                         loczrama = <1>;
 119                 };
 120
 121                 mcu_r5fss0_core1: r5f@41400000 {
 122                         compatible = "ti,j721e-r5f";
 123                         reg = <0x41400000 0x00008000>,
 124                               <0x41410000 0x00008000>;
 125                         reg-names = "atcm", "btcm";
 126                         ti,sci = <&dmsc>;
 127                         ti,sci-dev-id = <251>;
 128                         ti,sci-proc-ids = <0x02 0xFF>;
 129                         resets = <&k3_reset 251 1>;
 130                         atcm-enable = <1>;
 131                         btcm-enable = <1>;
 132                         loczrama = <1>;
 133                 };
 134         };
 135
 136         fss: fss@47000000 {
 137                 compatible = "syscon", "simple-mfd";
 138                 reg = <0x0 0x47000000 0x0 0x100>;
 139                 #address-cells = <2>;
 140                 #size-cells = <2>;
 141                 ranges;
 142
 143                 hbmc_mux: hbmc-mux {
 144                         compatible = "mmio-mux";
 145                         #mux-control-cells = <1>;
 146                         mux-reg-masks = <0x4 0x2>; /* HBMC select */
 147                 };
 148
 149                 hbmc: hyperbus@47034000 {
 150                         compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
 151                         reg = <0x0 0x47034000 0x0 0x100>,
 152                                 <0x5 0x00000000 0x1 0x0000000>;
 153                         power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 154                         #address-cells = <2>;
 155                         #size-cells = <1>;
 156                         mux-controls = <&hbmc_mux 0>;
 157                         assigned-clocks = <&k3_clks 102 0>;
 158                         assigned-clock-rates = <250000000>;
 159                 };
 160
 161                 ospi0: spi@47040000 {
 162                         compatible = "ti,am654-ospi";
 163                         reg = <0x0 0x47040000 0x0 0x100>,
 164                                 <0x5 0x00000000 0x1 0x0000000>;
 165                         interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
 166                         cdns,fifo-depth = <256>;
 167                         cdns,fifo-width = <4>;
 168                         cdns,trigger-address = <0x0>;
 169                         clocks = <&k3_clks 103 0>;
 170                         assigned-clocks = <&k3_clks 103 0>;
 171                         assigned-clock-parents = <&k3_clks 103 2>;
 172                         assigned-clock-rates = <166666666>;
 173                         power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                 };
 177
 178                 ospi1: spi@47050000 {
 179                         compatible = "ti,am654-ospi";
 180                         reg = <0x0 0x47050000 0x0 0x100>,
 181                                 <0x7 0x00000000 0x1 0x00000000>;
 182                         interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
 183                         cdns,fifo-depth = <256>;
 184                         cdns,fifo-width = <4>;
 185                         cdns,trigger-address = <0x0>;
 186                         clocks = <&k3_clks 104 0>;
 187                         assigned-clocks = <&k3_clks 104 0>;
 188                         assigned-clock-rates = <133333333>;
 189                         power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                 };
 193         };
 194
 195         mcu_i2c0: i2c@40b00000 {
 196                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 197                 reg = <0x0 0x40b00000 0x0 0x100>;
 198                 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
 199                 #address-cells = <1>;
 200                 #size-cells = <0>;
 201                 clock-names = "fck";
 202                 clocks = <&k3_clks 194 0>;
 203                 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
 204         };
 205
 206         mcu_i2c1: i2c@40b10000 {
 207                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 208                 reg = <0x0 0x40b10000 0x0 0x100>;
 209                 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 clock-names = "fck";
 213                 clocks = <&k3_clks 195 0>;
 214                 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
 215         };
 216
 217         mcu_navss {
 218                 compatible = "simple-mfd";
 219                 #address-cells = <2>;
 220                 #size-cells = <2>;
 221                 ranges;
 222                 dma-coherent;
 223                 dma-ranges;
 224
 225                 ti,sci-dev-id = <232>;
 226
 227                 mcu_ringacc: ringacc@2b800000 {
 228                         compatible = "ti,am654-navss-ringacc";
 229                         reg =   <0x0 0x2b800000 0x0 0x400000>,
 230                                 <0x0 0x2b000000 0x0 0x400000>,
 231                                 <0x0 0x28590000 0x0 0x100>,
 232                                 <0x0 0x2a500000 0x0 0x40000>;
 233                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 234                         ti,num-rings = <286>;
 235                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 236                         ti,sci = <&dmsc>;
 237                         ti,sci-dev-id = <235>;
 238                 };
 239
 240                 mcu_udmap: dma-controller@285c0000 {
 241                         compatible = "ti,j721e-navss-mcu-udmap";
 242                         reg =   <0x0 0x285c0000 0x0 0x100>,
 243                                 <0x0 0x2a800000 0x0 0x40000>,
 244                                 <0x0 0x2aa00000 0x0 0x40000>;
 245                         reg-names = "gcfg", "rchanrt", "tchanrt";
 246                         #dma-cells = <1>;
 247
 248                         ti,sci = <&dmsc>;
 249                         ti,sci-dev-id = <236>;
 250                         ti,ringacc = <&mcu_ringacc>;
 251
 252                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 253                                                 <0x0f>; /* TX_HCHAN */
 254                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 255                                                 <0x0b>; /* RX_HCHAN */
 256                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 257                 };
 258         };
 259
 260         mcu_cpsw: ethernet@46000000 {
 261                 compatible = "ti,j721e-cpsw-nuss";
 262                 #address-cells = <2>;
 263                 #size-cells = <2>;
 264                 reg = <0x0 0x46000000 0x0 0x200000>;
 265                 reg-names = "cpsw_nuss";
 266                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 267                 dma-coherent;
 268                 clocks = <&k3_clks 18 22>;
 269                 clock-names = "fck";
 270                 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
 271
 272                 dmas = <&mcu_udmap 0xf000>,
 273                        <&mcu_udmap 0xf001>,
 274                        <&mcu_udmap 0xf002>,
 275                        <&mcu_udmap 0xf003>,
 276                        <&mcu_udmap 0xf004>,
 277                        <&mcu_udmap 0xf005>,
 278                        <&mcu_udmap 0xf006>,
 279                        <&mcu_udmap 0xf007>,
 280                        <&mcu_udmap 0x7000>;
 281                 dma-names = "tx0", "tx1", "tx2", "tx3",
 282                             "tx4", "tx5", "tx6", "tx7",
 283                             "rx";
 284
 285                 ethernet-ports {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288
 289                         cpsw_port1: port@1 {
 290                                 reg = <1>;
 291                                 ti,mac-only;
 292                                 label = "port1";
 293                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 294                                 phys = <&phy_gmii_sel 1>;
 295                         };
 296                 };
 297
 298                 davinci_mdio: mdio@f00 {
 299                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 300                         reg = <0x0 0xf00 0x0 0x100>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         clocks = <&k3_clks 18 22>;
 304                         clock-names = "fck";
 305                         bus_freq = <1000000>;
 306                 };
 307
 308                 cpts@3d000 {
 309                         compatible = "ti,am65-cpts";
 310                         reg = <0x0 0x3d000 0x0 0x400>;
 311                         clocks = <&k3_clks 18 2>;
 312                         clock-names = "cpts";
 313                         interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 314                         interrupt-names = "cpts";
 315                         ti,cpts-ext-ts-inputs = <4>;
 316                         ti,cpts-periodic-outputs = <2>;
 317                 };
 318         };
 319
 320         chipid: chipid@43000014 {
 321                 compatible = "ti,am654-chipid";
 322                 reg = <0x0 0x43000014 0x0 0x4>;
 323         };
 324 };