1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 msmc_ram: sram@70000000 {
13 compatible = "mmio-sram";
14 reg = <0x0 0x70000000 0x0 0x800000>;
17 ranges = <0x0 0x0 0x70000000 0x800000>;
24 scm_conf: scm-conf@100000 {
25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
29 ranges = <0x0 0x0 0x00100000 0x1c000>;
31 pcie0_ctrl: syscon@4070 {
32 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
33 reg = <0x00004070 0x4>;
36 ranges = <0x4070 0x4070 0x4>;
39 pcie1_ctrl: syscon@4074 {
40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
41 reg = <0x00004074 0x4>;
44 ranges = <0x4074 0x4074 0x4>;
47 pcie2_ctrl: syscon@4078 {
48 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
49 reg = <0x00004078 0x4>;
52 ranges = <0x4078 0x4078 0x4>;
55 pcie3_ctrl: syscon@407c {
56 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
57 reg = <0x0000407c 0x4>;
60 ranges = <0x407c 0x407c 0x4>;
63 serdes_ln_ctrl: mux@4080 {
64 compatible = "mmio-mux";
65 reg = <0x00004080 0x50>;
66 #mux-control-cells = <1>;
67 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
68 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
69 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
70 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
71 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
72 /* SERDES4 lane0/1/2/3 select */
73 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
74 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
75 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
76 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
77 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
78 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
81 usb_serdes_mux: mux-controller@4000 {
82 compatible = "mmio-mux";
83 #mux-control-cells = <1>;
84 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
85 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
89 gic500: interrupt-controller@1800000 {
90 compatible = "arm,gic-v3";
94 #interrupt-cells = <3>;
96 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
97 <0x00 0x01900000 0x00 0x100000>; /* GICR */
99 /* vcpumntirq: virtual CPU interface maintenance interrupt */
100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
102 gic_its: msi-controller@1820000 {
103 compatible = "arm,gic-v3-its";
104 reg = <0x00 0x01820000 0x00 0x10000>;
105 socionext,synquacer-pre-its = <0x1000000 0x400000>;
111 main_gpio_intr: interrupt-controller0 {
112 compatible = "ti,sci-intr";
113 ti,intr-trigger-type = <1>;
114 interrupt-controller;
115 interrupt-parent = <&gic500>;
116 #interrupt-cells = <1>;
118 ti,sci-dev-id = <131>;
119 ti,interrupt-ranges = <8 392 56>;
123 compatible = "simple-mfd";
124 #address-cells = <2>;
130 ti,sci-dev-id = <199>;
132 main_navss_intr: interrupt-controller1 {
133 compatible = "ti,sci-intr";
134 ti,intr-trigger-type = <4>;
135 interrupt-controller;
136 interrupt-parent = <&gic500>;
137 #interrupt-cells = <1>;
139 ti,sci-dev-id = <213>;
140 ti,interrupt-ranges = <0 64 64>,
145 main_udmass_inta: interrupt-controller@33d00000 {
146 compatible = "ti,sci-inta";
147 reg = <0x0 0x33d00000 0x0 0x100000>;
148 interrupt-controller;
149 interrupt-parent = <&main_navss_intr>;
151 #interrupt-cells = <0>;
153 ti,sci-dev-id = <209>;
154 ti,interrupt-ranges = <0 0 256>;
157 secure_proxy_main: mailbox@32c00000 {
158 compatible = "ti,am654-secure-proxy";
160 reg-names = "target_data", "rt", "scfg";
161 reg = <0x00 0x32c00000 0x00 0x100000>,
162 <0x00 0x32400000 0x00 0x100000>,
163 <0x00 0x32800000 0x00 0x100000>;
164 interrupt-names = "rx_011";
165 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
168 smmu0: iommu@36600000 {
169 compatible = "arm,smmu-v3";
170 reg = <0x0 0x36600000 0x0 0x100000>;
171 interrupt-parent = <&gic500>;
172 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
173 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
174 interrupt-names = "eventq", "gerror";
178 hwspinlock: spinlock@30e00000 {
179 compatible = "ti,am654-hwspinlock";
180 reg = <0x00 0x30e00000 0x00 0x1000>;
184 mailbox0_cluster0: mailbox@31f80000 {
185 compatible = "ti,am654-mailbox";
186 reg = <0x00 0x31f80000 0x00 0x200>;
188 ti,mbox-num-users = <4>;
189 ti,mbox-num-fifos = <16>;
190 interrupt-parent = <&main_navss_intr>;
193 mailbox0_cluster1: mailbox@31f81000 {
194 compatible = "ti,am654-mailbox";
195 reg = <0x00 0x31f81000 0x00 0x200>;
197 ti,mbox-num-users = <4>;
198 ti,mbox-num-fifos = <16>;
199 interrupt-parent = <&main_navss_intr>;
202 mailbox0_cluster2: mailbox@31f82000 {
203 compatible = "ti,am654-mailbox";
204 reg = <0x00 0x31f82000 0x00 0x200>;
206 ti,mbox-num-users = <4>;
207 ti,mbox-num-fifos = <16>;
208 interrupt-parent = <&main_navss_intr>;
211 mailbox0_cluster3: mailbox@31f83000 {
212 compatible = "ti,am654-mailbox";
213 reg = <0x00 0x31f83000 0x00 0x200>;
215 ti,mbox-num-users = <4>;
216 ti,mbox-num-fifos = <16>;
217 interrupt-parent = <&main_navss_intr>;
220 mailbox0_cluster4: mailbox@31f84000 {
221 compatible = "ti,am654-mailbox";
222 reg = <0x00 0x31f84000 0x00 0x200>;
224 ti,mbox-num-users = <4>;
225 ti,mbox-num-fifos = <16>;
226 interrupt-parent = <&main_navss_intr>;
229 mailbox0_cluster5: mailbox@31f85000 {
230 compatible = "ti,am654-mailbox";
231 reg = <0x00 0x31f85000 0x00 0x200>;
233 ti,mbox-num-users = <4>;
234 ti,mbox-num-fifos = <16>;
235 interrupt-parent = <&main_navss_intr>;
238 mailbox0_cluster6: mailbox@31f86000 {
239 compatible = "ti,am654-mailbox";
240 reg = <0x00 0x31f86000 0x00 0x200>;
242 ti,mbox-num-users = <4>;
243 ti,mbox-num-fifos = <16>;
244 interrupt-parent = <&main_navss_intr>;
247 mailbox0_cluster7: mailbox@31f87000 {
248 compatible = "ti,am654-mailbox";
249 reg = <0x00 0x31f87000 0x00 0x200>;
251 ti,mbox-num-users = <4>;
252 ti,mbox-num-fifos = <16>;
253 interrupt-parent = <&main_navss_intr>;
256 mailbox0_cluster8: mailbox@31f88000 {
257 compatible = "ti,am654-mailbox";
258 reg = <0x00 0x31f88000 0x00 0x200>;
260 ti,mbox-num-users = <4>;
261 ti,mbox-num-fifos = <16>;
262 interrupt-parent = <&main_navss_intr>;
265 mailbox0_cluster9: mailbox@31f89000 {
266 compatible = "ti,am654-mailbox";
267 reg = <0x00 0x31f89000 0x00 0x200>;
269 ti,mbox-num-users = <4>;
270 ti,mbox-num-fifos = <16>;
271 interrupt-parent = <&main_navss_intr>;
274 mailbox0_cluster10: mailbox@31f8a000 {
275 compatible = "ti,am654-mailbox";
276 reg = <0x00 0x31f8a000 0x00 0x200>;
278 ti,mbox-num-users = <4>;
279 ti,mbox-num-fifos = <16>;
280 interrupt-parent = <&main_navss_intr>;
283 mailbox0_cluster11: mailbox@31f8b000 {
284 compatible = "ti,am654-mailbox";
285 reg = <0x00 0x31f8b000 0x00 0x200>;
287 ti,mbox-num-users = <4>;
288 ti,mbox-num-fifos = <16>;
289 interrupt-parent = <&main_navss_intr>;
292 main_ringacc: ringacc@3c000000 {
293 compatible = "ti,am654-navss-ringacc";
294 reg = <0x0 0x3c000000 0x0 0x400000>,
295 <0x0 0x38000000 0x0 0x400000>,
296 <0x0 0x31120000 0x0 0x100>,
297 <0x0 0x33000000 0x0 0x40000>;
298 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
299 ti,num-rings = <1024>;
300 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
302 ti,sci-dev-id = <211>;
303 msi-parent = <&main_udmass_inta>;
306 main_udmap: dma-controller@31150000 {
307 compatible = "ti,j721e-navss-main-udmap";
308 reg = <0x0 0x31150000 0x0 0x100>,
309 <0x0 0x34000000 0x0 0x100000>,
310 <0x0 0x35000000 0x0 0x100000>;
311 reg-names = "gcfg", "rchanrt", "tchanrt";
312 msi-parent = <&main_udmass_inta>;
316 ti,sci-dev-id = <212>;
317 ti,ringacc = <&main_ringacc>;
319 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
320 <0x0f>, /* TX_HCHAN */
321 <0x10>; /* TX_UHCHAN */
322 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
323 <0x0b>, /* RX_HCHAN */
324 <0x0c>; /* RX_UHCHAN */
325 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
329 compatible = "ti,j721e-cpts";
330 reg = <0x0 0x310d0000 0x0 0x400>;
332 clocks = <&k3_clks 201 1>;
333 clock-names = "cpts";
334 interrupts-extended = <&main_navss_intr 391>;
335 interrupt-names = "cpts";
336 ti,cpts-periodic-outputs = <6>;
337 ti,cpts-ext-ts-inputs = <8>;
341 main_crypto: crypto@4e00000 {
342 compatible = "ti,j721e-sa2ul";
343 reg = <0x0 0x4e00000 0x0 0x1200>;
344 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
345 #address-cells = <2>;
347 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
349 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
350 <&main_udmap 0x4001>;
351 dma-names = "tx", "rx1", "rx2";
355 compatible = "inside-secure,safexcel-eip76";
356 reg = <0x0 0x4e10000 0x0 0x7d>;
357 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&k3_clks 264 1>;
362 main_pmx0: pinctrl@11c000 {
363 compatible = "pinctrl-single";
364 /* Proxy 0 addressing */
365 reg = <0x0 0x11c000 0x0 0x2b4>;
366 #pinctrl-cells = <1>;
367 pinctrl-single,register-width = <32>;
368 pinctrl-single,function-mask = <0xffffffff>;
371 dummy_cmn_refclk: dummy-cmn-refclk {
373 compatible = "fixed-clock";
374 clock-frequency = <100000000>;
377 dummy_cmn_refclk1: dummy-cmn-refclk1 {
379 compatible = "fixed-clock";
380 clock-frequency = <100000000>;
383 serdes_wiz0: wiz@5000000 {
384 compatible = "ti,j721e-wiz-16g";
385 #address-cells = <1>;
387 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
388 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
389 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
390 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
391 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
394 ranges = <0x5000000 0x0 0x5000000 0x10000>;
396 wiz0_pll0_refclk: pll0-refclk {
397 clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
399 assigned-clocks = <&wiz0_pll0_refclk>;
400 assigned-clock-parents = <&k3_clks 292 11>;
403 wiz0_pll1_refclk: pll1-refclk {
404 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
406 assigned-clocks = <&wiz0_pll1_refclk>;
407 assigned-clock-parents = <&k3_clks 292 0>;
410 wiz0_refclk_dig: refclk-dig {
411 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
413 assigned-clocks = <&wiz0_refclk_dig>;
414 assigned-clock-parents = <&k3_clks 292 11>;
417 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
418 clocks = <&wiz0_refclk_dig>;
422 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
423 clocks = <&wiz0_pll1_refclk>;
427 serdes0: serdes@5000000 {
428 compatible = "ti,sierra-phy-t0";
429 reg-names = "serdes";
430 reg = <0x5000000 0x10000>;
431 #address-cells = <1>;
433 resets = <&serdes_wiz0 0>;
434 reset-names = "sierra_reset";
435 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
436 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
440 serdes_wiz1: wiz@5010000 {
441 compatible = "ti,j721e-wiz-16g";
442 #address-cells = <1>;
444 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
445 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
446 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
447 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
448 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
451 ranges = <0x5010000 0x0 0x5010000 0x10000>;
453 wiz1_pll0_refclk: pll0-refclk {
454 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
456 assigned-clocks = <&wiz1_pll0_refclk>;
457 assigned-clock-parents = <&k3_clks 293 13>;
460 wiz1_pll1_refclk: pll1-refclk {
461 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
463 assigned-clocks = <&wiz1_pll1_refclk>;
464 assigned-clock-parents = <&k3_clks 293 0>;
467 wiz1_refclk_dig: refclk-dig {
468 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
470 assigned-clocks = <&wiz1_refclk_dig>;
471 assigned-clock-parents = <&k3_clks 293 13>;
474 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
475 clocks = <&wiz1_refclk_dig>;
479 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
480 clocks = <&wiz1_pll1_refclk>;
484 serdes1: serdes@5010000 {
485 compatible = "ti,sierra-phy-t0";
486 reg-names = "serdes";
487 reg = <0x5010000 0x10000>;
488 #address-cells = <1>;
490 resets = <&serdes_wiz1 0>;
491 reset-names = "sierra_reset";
492 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
493 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
497 serdes_wiz2: wiz@5020000 {
498 compatible = "ti,j721e-wiz-16g";
499 #address-cells = <1>;
501 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
502 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
503 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
504 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
505 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
508 ranges = <0x5020000 0x0 0x5020000 0x10000>;
510 wiz2_pll0_refclk: pll0-refclk {
511 clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
513 assigned-clocks = <&wiz2_pll0_refclk>;
514 assigned-clock-parents = <&k3_clks 294 11>;
517 wiz2_pll1_refclk: pll1-refclk {
518 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
520 assigned-clocks = <&wiz2_pll1_refclk>;
521 assigned-clock-parents = <&k3_clks 294 0>;
524 wiz2_refclk_dig: refclk-dig {
525 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
527 assigned-clocks = <&wiz2_refclk_dig>;
528 assigned-clock-parents = <&k3_clks 294 11>;
531 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
532 clocks = <&wiz2_refclk_dig>;
536 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
537 clocks = <&wiz2_pll1_refclk>;
541 serdes2: serdes@5020000 {
542 compatible = "ti,sierra-phy-t0";
543 reg-names = "serdes";
544 reg = <0x5020000 0x10000>;
545 #address-cells = <1>;
547 resets = <&serdes_wiz2 0>;
548 reset-names = "sierra_reset";
549 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
550 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
554 serdes_wiz3: wiz@5030000 {
555 compatible = "ti,j721e-wiz-16g";
556 #address-cells = <1>;
558 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
559 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
560 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
561 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
562 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
565 ranges = <0x5030000 0x0 0x5030000 0x10000>;
567 wiz3_pll0_refclk: pll0-refclk {
568 clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
570 assigned-clocks = <&wiz3_pll0_refclk>;
571 assigned-clock-parents = <&k3_clks 295 9>;
574 wiz3_pll1_refclk: pll1-refclk {
575 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
577 assigned-clocks = <&wiz3_pll1_refclk>;
578 assigned-clock-parents = <&k3_clks 295 0>;
581 wiz3_refclk_dig: refclk-dig {
582 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
584 assigned-clocks = <&wiz3_refclk_dig>;
585 assigned-clock-parents = <&k3_clks 295 9>;
588 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
589 clocks = <&wiz3_refclk_dig>;
593 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
594 clocks = <&wiz3_pll1_refclk>;
598 serdes3: serdes@5030000 {
599 compatible = "ti,sierra-phy-t0";
600 reg-names = "serdes";
601 reg = <0x5030000 0x10000>;
602 #address-cells = <1>;
604 resets = <&serdes_wiz3 0>;
605 reset-names = "sierra_reset";
606 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
607 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
611 pcie0_rc: pcie@2900000 {
612 compatible = "ti,j721e-pcie-host";
613 reg = <0x00 0x02900000 0x00 0x1000>,
614 <0x00 0x02907000 0x00 0x400>,
615 <0x00 0x0d000000 0x00 0x00800000>,
616 <0x00 0x10000000 0x00 0x00001000>;
617 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
618 interrupt-names = "link_state";
619 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
621 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
622 max-link-speed = <3>;
624 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
625 clocks = <&k3_clks 239 1>;
627 #address-cells = <3>;
629 bus-range = <0x0 0xf>;
630 vendor-id = <0x104c>;
631 device-id = <0xb00d>;
632 msi-map = <0x0 &gic_its 0x0 0x10000>;
634 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
635 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
636 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
639 pcie0_ep: pcie-ep@2900000 {
640 compatible = "ti,j721e-pcie-ep";
641 reg = <0x00 0x02900000 0x00 0x1000>,
642 <0x00 0x02907000 0x00 0x400>,
643 <0x00 0x0d000000 0x00 0x00800000>,
644 <0x00 0x10000000 0x00 0x08000000>;
645 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
646 interrupt-names = "link_state";
647 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
648 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
649 max-link-speed = <3>;
651 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
652 clocks = <&k3_clks 239 1>;
654 cdns,max-outbound-regions = <16>;
655 max-functions = /bits/ 8 <6>;
656 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
660 pcie1_rc: pcie@2910000 {
661 compatible = "ti,j721e-pcie-host";
662 reg = <0x00 0x02910000 0x00 0x1000>,
663 <0x00 0x02917000 0x00 0x400>,
664 <0x00 0x0d800000 0x00 0x00800000>,
665 <0x00 0x18000000 0x00 0x00001000>;
666 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
667 interrupt-names = "link_state";
668 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
670 ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
671 max-link-speed = <3>;
673 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
674 clocks = <&k3_clks 240 1>;
676 #address-cells = <3>;
678 bus-range = <0x0 0xf>;
679 vendor-id = <0x104c>;
680 device-id = <0xb00d>;
681 msi-map = <0x0 &gic_its 0x10000 0x10000>;
683 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
684 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
685 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
688 pcie1_ep: pcie-ep@2910000 {
689 compatible = "ti,j721e-pcie-ep";
690 reg = <0x00 0x02910000 0x00 0x1000>,
691 <0x00 0x02917000 0x00 0x400>,
692 <0x00 0x0d800000 0x00 0x00800000>,
693 <0x00 0x18000000 0x00 0x08000000>;
694 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
695 interrupt-names = "link_state";
696 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
697 ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
698 max-link-speed = <3>;
700 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
701 clocks = <&k3_clks 240 1>;
703 cdns,max-outbound-regions = <16>;
704 max-functions = /bits/ 8 <6>;
705 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
709 pcie2_rc: pcie@2920000 {
710 compatible = "ti,j721e-pcie-host";
711 reg = <0x00 0x02920000 0x00 0x1000>,
712 <0x00 0x02927000 0x00 0x400>,
713 <0x00 0x0e000000 0x00 0x00800000>,
714 <0x44 0x00000000 0x00 0x00001000>;
715 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
716 interrupt-names = "link_state";
717 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
719 ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
720 max-link-speed = <3>;
722 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
723 clocks = <&k3_clks 241 1>;
725 #address-cells = <3>;
727 bus-range = <0x0 0xf>;
728 vendor-id = <0x104c>;
729 device-id = <0xb00d>;
730 msi-map = <0x0 &gic_its 0x20000 0x10000>;
732 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
733 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
734 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
737 pcie2_ep: pcie-ep@2920000 {
738 compatible = "ti,j721e-pcie-ep";
739 reg = <0x00 0x02920000 0x00 0x1000>,
740 <0x00 0x02927000 0x00 0x400>,
741 <0x00 0x0e000000 0x00 0x00800000>,
742 <0x44 0x00000000 0x00 0x08000000>;
743 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
744 interrupt-names = "link_state";
745 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
746 ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
747 max-link-speed = <3>;
749 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
750 clocks = <&k3_clks 241 1>;
752 cdns,max-outbound-regions = <16>;
753 max-functions = /bits/ 8 <6>;
754 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
758 pcie3_rc: pcie@2930000 {
759 compatible = "ti,j721e-pcie-host";
760 reg = <0x00 0x02930000 0x00 0x1000>,
761 <0x00 0x02937000 0x00 0x400>,
762 <0x00 0x0e800000 0x00 0x00800000>,
763 <0x44 0x10000000 0x00 0x00001000>;
764 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
765 interrupt-names = "link_state";
766 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
768 ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
769 max-link-speed = <3>;
771 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
772 clocks = <&k3_clks 242 1>;
774 #address-cells = <3>;
776 bus-range = <0x0 0xf>;
777 vendor-id = <0x104c>;
778 device-id = <0xb00d>;
779 msi-map = <0x0 &gic_its 0x30000 0x10000>;
781 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
782 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
783 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
786 pcie3_ep: pcie-ep@2930000 {
787 compatible = "ti,j721e-pcie-ep";
788 reg = <0x00 0x02930000 0x00 0x1000>,
789 <0x00 0x02937000 0x00 0x400>,
790 <0x00 0x0e800000 0x00 0x00800000>,
791 <0x44 0x10000000 0x00 0x08000000>;
792 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
793 interrupt-names = "link_state";
794 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
795 ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
796 max-link-speed = <3>;
798 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
799 clocks = <&k3_clks 242 1>;
801 cdns,max-outbound-regions = <16>;
802 max-functions = /bits/ 8 <6>;
803 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
805 #address-cells = <2>;
809 main_uart0: serial@2800000 {
810 compatible = "ti,j721e-uart", "ti,am654-uart";
811 reg = <0x00 0x02800000 0x00 0x100>;
814 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
815 clock-frequency = <48000000>;
816 current-speed = <115200>;
817 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
818 clocks = <&k3_clks 146 0>;
819 clock-names = "fclk";
822 main_uart1: serial@2810000 {
823 compatible = "ti,j721e-uart", "ti,am654-uart";
824 reg = <0x00 0x02810000 0x00 0x100>;
827 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
828 clock-frequency = <48000000>;
829 current-speed = <115200>;
830 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
831 clocks = <&k3_clks 278 0>;
832 clock-names = "fclk";
835 main_uart2: serial@2820000 {
836 compatible = "ti,j721e-uart", "ti,am654-uart";
837 reg = <0x00 0x02820000 0x00 0x100>;
840 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
841 clock-frequency = <48000000>;
842 current-speed = <115200>;
843 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
844 clocks = <&k3_clks 279 0>;
845 clock-names = "fclk";
848 main_uart3: serial@2830000 {
849 compatible = "ti,j721e-uart", "ti,am654-uart";
850 reg = <0x00 0x02830000 0x00 0x100>;
853 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
854 clock-frequency = <48000000>;
855 current-speed = <115200>;
856 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
857 clocks = <&k3_clks 280 0>;
858 clock-names = "fclk";
861 main_uart4: serial@2840000 {
862 compatible = "ti,j721e-uart", "ti,am654-uart";
863 reg = <0x00 0x02840000 0x00 0x100>;
866 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
867 clock-frequency = <48000000>;
868 current-speed = <115200>;
869 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
870 clocks = <&k3_clks 281 0>;
871 clock-names = "fclk";
874 main_uart5: serial@2850000 {
875 compatible = "ti,j721e-uart", "ti,am654-uart";
876 reg = <0x00 0x02850000 0x00 0x100>;
879 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
880 clock-frequency = <48000000>;
881 current-speed = <115200>;
882 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
883 clocks = <&k3_clks 282 0>;
884 clock-names = "fclk";
887 main_uart6: serial@2860000 {
888 compatible = "ti,j721e-uart", "ti,am654-uart";
889 reg = <0x00 0x02860000 0x00 0x100>;
892 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
893 clock-frequency = <48000000>;
894 current-speed = <115200>;
895 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
896 clocks = <&k3_clks 283 0>;
897 clock-names = "fclk";
900 main_uart7: serial@2870000 {
901 compatible = "ti,j721e-uart", "ti,am654-uart";
902 reg = <0x00 0x02870000 0x00 0x100>;
905 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
906 clock-frequency = <48000000>;
907 current-speed = <115200>;
908 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
909 clocks = <&k3_clks 284 0>;
910 clock-names = "fclk";
913 main_uart8: serial@2880000 {
914 compatible = "ti,j721e-uart", "ti,am654-uart";
915 reg = <0x00 0x02880000 0x00 0x100>;
918 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
919 clock-frequency = <48000000>;
920 current-speed = <115200>;
921 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
922 clocks = <&k3_clks 285 0>;
923 clock-names = "fclk";
926 main_uart9: serial@2890000 {
927 compatible = "ti,j721e-uart", "ti,am654-uart";
928 reg = <0x00 0x02890000 0x00 0x100>;
931 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
932 clock-frequency = <48000000>;
933 current-speed = <115200>;
934 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
935 clocks = <&k3_clks 286 0>;
936 clock-names = "fclk";
939 main_gpio0: gpio@600000 {
940 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
941 reg = <0x0 0x00600000 0x0 0x100>;
944 interrupt-parent = <&main_gpio_intr>;
945 interrupts = <256>, <257>, <258>, <259>,
946 <260>, <261>, <262>, <263>;
947 interrupt-controller;
948 #interrupt-cells = <2>;
950 ti,davinci-gpio-unbanked = <0>;
951 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
952 clocks = <&k3_clks 105 0>;
953 clock-names = "gpio";
956 main_gpio1: gpio@601000 {
957 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
958 reg = <0x0 0x00601000 0x0 0x100>;
961 interrupt-parent = <&main_gpio_intr>;
962 interrupts = <288>, <289>, <290>;
963 interrupt-controller;
964 #interrupt-cells = <2>;
966 ti,davinci-gpio-unbanked = <0>;
967 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
968 clocks = <&k3_clks 106 0>;
969 clock-names = "gpio";
972 main_gpio2: gpio@610000 {
973 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
974 reg = <0x0 0x00610000 0x0 0x100>;
977 interrupt-parent = <&main_gpio_intr>;
978 interrupts = <264>, <265>, <266>, <267>,
979 <268>, <269>, <270>, <271>;
980 interrupt-controller;
981 #interrupt-cells = <2>;
983 ti,davinci-gpio-unbanked = <0>;
984 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
985 clocks = <&k3_clks 107 0>;
986 clock-names = "gpio";
989 main_gpio3: gpio@611000 {
990 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
991 reg = <0x0 0x00611000 0x0 0x100>;
994 interrupt-parent = <&main_gpio_intr>;
995 interrupts = <292>, <293>, <294>;
996 interrupt-controller;
997 #interrupt-cells = <2>;
999 ti,davinci-gpio-unbanked = <0>;
1000 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1001 clocks = <&k3_clks 108 0>;
1002 clock-names = "gpio";
1005 main_gpio4: gpio@620000 {
1006 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1007 reg = <0x0 0x00620000 0x0 0x100>;
1010 interrupt-parent = <&main_gpio_intr>;
1011 interrupts = <272>, <273>, <274>, <275>,
1012 <276>, <277>, <278>, <279>;
1013 interrupt-controller;
1014 #interrupt-cells = <2>;
1016 ti,davinci-gpio-unbanked = <0>;
1017 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1018 clocks = <&k3_clks 109 0>;
1019 clock-names = "gpio";
1022 main_gpio5: gpio@621000 {
1023 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1024 reg = <0x0 0x00621000 0x0 0x100>;
1027 interrupt-parent = <&main_gpio_intr>;
1028 interrupts = <296>, <297>, <298>;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1032 ti,davinci-gpio-unbanked = <0>;
1033 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1034 clocks = <&k3_clks 110 0>;
1035 clock-names = "gpio";
1038 main_gpio6: gpio@630000 {
1039 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1040 reg = <0x0 0x00630000 0x0 0x100>;
1043 interrupt-parent = <&main_gpio_intr>;
1044 interrupts = <280>, <281>, <282>, <283>,
1045 <284>, <285>, <286>, <287>;
1046 interrupt-controller;
1047 #interrupt-cells = <2>;
1049 ti,davinci-gpio-unbanked = <0>;
1050 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1051 clocks = <&k3_clks 111 0>;
1052 clock-names = "gpio";
1055 main_gpio7: gpio@631000 {
1056 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1057 reg = <0x0 0x00631000 0x0 0x100>;
1060 interrupt-parent = <&main_gpio_intr>;
1061 interrupts = <300>, <301>, <302>;
1062 interrupt-controller;
1063 #interrupt-cells = <2>;
1065 ti,davinci-gpio-unbanked = <0>;
1066 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1067 clocks = <&k3_clks 112 0>;
1068 clock-names = "gpio";
1071 main_sdhci0: sdhci@4f80000 {
1072 compatible = "ti,j721e-sdhci-8bit";
1073 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1074 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1075 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1076 clock-names = "clk_xin", "clk_ahb";
1077 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
1078 assigned-clocks = <&k3_clks 91 1>;
1079 assigned-clock-parents = <&k3_clks 91 2>;
1083 ti,otap-del-sel-legacy = <0xf>;
1084 ti,otap-del-sel-mmc-hs = <0xf>;
1085 ti,otap-del-sel-ddr52 = <0x5>;
1086 ti,otap-del-sel-hs200 = <0x6>;
1087 ti,itap-del-sel-legacy = <0x10>;
1088 ti,itap-del-sel-mmc-hs = <0xa>;
1089 ti,itap-del-sel-ddr52 = <0x3>;
1094 main_sdhci1: sdhci@4fb0000 {
1095 compatible = "ti,j721e-sdhci-4bit";
1096 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1097 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1099 clock-names = "clk_xin", "clk_ahb";
1100 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
1101 assigned-clocks = <&k3_clks 92 0>;
1102 assigned-clock-parents = <&k3_clks 92 1>;
1103 ti,otap-del-sel-legacy = <0x0>;
1104 ti,otap-del-sel-sd-hs = <0x0>;
1105 ti,otap-del-sel-sdr12 = <0xf>;
1106 ti,otap-del-sel-sdr25 = <0xf>;
1107 ti,otap-del-sel-sdr50 = <0xc>;
1108 ti,otap-del-sel-ddr50 = <0xc>;
1109 ti,itap-del-sel-legacy = <0x0>;
1110 ti,itap-del-sel-sd-hs = <0x0>;
1111 ti,itap-del-sel-sdr12 = <0x0>;
1112 ti,itap-del-sel-sdr25 = <0x0>;
1113 ti,itap-del-sel-ddr50 = <0x2>;
1115 ti,clkbuf-sel = <0x7>;
1117 sdhci-caps-mask = <0x2 0x0>;
1120 main_sdhci2: sdhci@4f98000 {
1121 compatible = "ti,j721e-sdhci-4bit";
1122 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1123 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1124 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1125 clock-names = "clk_xin", "clk_ahb";
1126 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
1127 assigned-clocks = <&k3_clks 93 0>;
1128 assigned-clock-parents = <&k3_clks 93 1>;
1129 ti,otap-del-sel-legacy = <0x0>;
1130 ti,otap-del-sel-sd-hs = <0x0>;
1131 ti,otap-del-sel-sdr12 = <0xf>;
1132 ti,otap-del-sel-sdr25 = <0xf>;
1133 ti,otap-del-sel-sdr50 = <0xc>;
1134 ti,otap-del-sel-ddr50 = <0xc>;
1135 ti,itap-del-sel-legacy = <0x0>;
1136 ti,itap-del-sel-sd-hs = <0x0>;
1137 ti,itap-del-sel-sdr12 = <0x0>;
1138 ti,itap-del-sel-sdr25 = <0x0>;
1139 ti,itap-del-sel-ddr50 = <0x2>;
1141 ti,clkbuf-sel = <0x7>;
1143 sdhci-caps-mask = <0x2 0x0>;
1146 usbss0: cdns-usb@4104000 {
1147 compatible = "ti,j721e-usb";
1148 reg = <0x00 0x4104000 0x00 0x100>;
1150 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1151 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1152 clock-names = "ref", "lpm";
1153 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1154 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1155 #address-cells = <2>;
1160 compatible = "cdns,usb3";
1161 reg = <0x00 0x6000000 0x00 0x10000>,
1162 <0x00 0x6010000 0x00 0x10000>,
1163 <0x00 0x6020000 0x00 0x10000>;
1164 reg-names = "otg", "xhci", "dev";
1165 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1166 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1167 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1168 interrupt-names = "host",
1171 maximum-speed = "super-speed";
1176 usbss1: cdns-usb@4114000 {
1177 compatible = "ti,j721e-usb";
1178 reg = <0x00 0x4114000 0x00 0x100>;
1180 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1181 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1182 clock-names = "ref", "lpm";
1183 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1184 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1185 #address-cells = <2>;
1190 compatible = "cdns,usb3";
1191 reg = <0x00 0x6400000 0x00 0x10000>,
1192 <0x00 0x6410000 0x00 0x10000>,
1193 <0x00 0x6420000 0x00 0x10000>;
1194 reg-names = "otg", "xhci", "dev";
1195 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1196 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1197 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1198 interrupt-names = "host",
1201 maximum-speed = "super-speed";
1206 main_i2c0: i2c@2000000 {
1207 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1208 reg = <0x0 0x2000000 0x0 0x100>;
1209 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1210 #address-cells = <1>;
1212 clock-names = "fck";
1213 clocks = <&k3_clks 187 0>;
1214 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1217 main_i2c1: i2c@2010000 {
1218 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1219 reg = <0x0 0x2010000 0x0 0x100>;
1220 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1221 #address-cells = <1>;
1223 clock-names = "fck";
1224 clocks = <&k3_clks 188 0>;
1225 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1228 main_i2c2: i2c@2020000 {
1229 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1230 reg = <0x0 0x2020000 0x0 0x100>;
1231 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1232 #address-cells = <1>;
1234 clock-names = "fck";
1235 clocks = <&k3_clks 189 0>;
1236 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1239 main_i2c3: i2c@2030000 {
1240 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1241 reg = <0x0 0x2030000 0x0 0x100>;
1242 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1243 #address-cells = <1>;
1245 clock-names = "fck";
1246 clocks = <&k3_clks 190 0>;
1247 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1250 main_i2c4: i2c@2040000 {
1251 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1252 reg = <0x0 0x2040000 0x0 0x100>;
1253 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1254 #address-cells = <1>;
1256 clock-names = "fck";
1257 clocks = <&k3_clks 191 0>;
1258 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1261 main_i2c5: i2c@2050000 {
1262 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1263 reg = <0x0 0x2050000 0x0 0x100>;
1264 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1265 #address-cells = <1>;
1267 clock-names = "fck";
1268 clocks = <&k3_clks 192 0>;
1269 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1272 main_i2c6: i2c@2060000 {
1273 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1274 reg = <0x0 0x2060000 0x0 0x100>;
1275 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1276 #address-cells = <1>;
1278 clock-names = "fck";
1279 clocks = <&k3_clks 193 0>;
1280 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1283 ufs_wrapper: ufs-wrapper@4e80000 {
1284 compatible = "ti,j721e-ufs";
1285 reg = <0x0 0x4e80000 0x0 0x100>;
1286 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1287 clocks = <&k3_clks 277 1>;
1288 assigned-clocks = <&k3_clks 277 1>;
1289 assigned-clock-parents = <&k3_clks 277 4>;
1291 #address-cells = <2>;
1295 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1296 reg = <0x0 0x4e84000 0x0 0x10000>;
1297 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1298 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1299 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1300 clock-names = "core_clk", "phy_clk", "ref_clk";
1306 compatible = "ti,j721e-dss";
1308 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1309 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1310 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1311 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1313 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1314 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1315 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1316 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1318 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1319 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1320 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1321 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1323 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1324 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1325 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1326 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1327 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1329 reg-names = "common_m", "common_s0",
1330 "common_s1", "common_s2",
1331 "vidl1", "vidl2","vid1","vid2",
1332 "ovr1", "ovr2", "ovr3", "ovr4",
1333 "vp1", "vp2", "vp3", "vp4",
1336 clocks = <&k3_clks 152 0>,
1341 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1343 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1345 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1349 interrupt-names = "common_m",
1355 #address-cells = <1>;
1360 mcasp0: mcasp@2b00000 {
1361 compatible = "ti,am33xx-mcasp-audio";
1362 reg = <0x0 0x02b00000 0x0 0x2000>,
1363 <0x0 0x02b08000 0x0 0x1000>;
1364 reg-names = "mpu","dat";
1365 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1367 interrupt-names = "tx", "rx";
1369 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1370 dma-names = "tx", "rx";
1372 clocks = <&k3_clks 174 1>;
1373 clock-names = "fck";
1374 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1377 mcasp1: mcasp@2b10000 {
1378 compatible = "ti,am33xx-mcasp-audio";
1379 reg = <0x0 0x02b10000 0x0 0x2000>,
1380 <0x0 0x02b18000 0x0 0x1000>;
1381 reg-names = "mpu","dat";
1382 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1384 interrupt-names = "tx", "rx";
1386 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1387 dma-names = "tx", "rx";
1389 clocks = <&k3_clks 175 1>;
1390 clock-names = "fck";
1391 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1394 mcasp2: mcasp@2b20000 {
1395 compatible = "ti,am33xx-mcasp-audio";
1396 reg = <0x0 0x02b20000 0x0 0x2000>,
1397 <0x0 0x02b28000 0x0 0x1000>;
1398 reg-names = "mpu","dat";
1399 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1401 interrupt-names = "tx", "rx";
1403 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1404 dma-names = "tx", "rx";
1406 clocks = <&k3_clks 176 1>;
1407 clock-names = "fck";
1408 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1411 mcasp3: mcasp@2b30000 {
1412 compatible = "ti,am33xx-mcasp-audio";
1413 reg = <0x0 0x02b30000 0x0 0x2000>,
1414 <0x0 0x02b38000 0x0 0x1000>;
1415 reg-names = "mpu","dat";
1416 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1418 interrupt-names = "tx", "rx";
1420 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1421 dma-names = "tx", "rx";
1423 clocks = <&k3_clks 177 1>;
1424 clock-names = "fck";
1425 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1428 mcasp4: mcasp@2b40000 {
1429 compatible = "ti,am33xx-mcasp-audio";
1430 reg = <0x0 0x02b40000 0x0 0x2000>,
1431 <0x0 0x02b48000 0x0 0x1000>;
1432 reg-names = "mpu","dat";
1433 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1435 interrupt-names = "tx", "rx";
1437 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1438 dma-names = "tx", "rx";
1440 clocks = <&k3_clks 178 1>;
1441 clock-names = "fck";
1442 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1445 mcasp5: mcasp@2b50000 {
1446 compatible = "ti,am33xx-mcasp-audio";
1447 reg = <0x0 0x02b50000 0x0 0x2000>,
1448 <0x0 0x02b58000 0x0 0x1000>;
1449 reg-names = "mpu","dat";
1450 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-names = "tx", "rx";
1454 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1455 dma-names = "tx", "rx";
1457 clocks = <&k3_clks 179 1>;
1458 clock-names = "fck";
1459 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1462 mcasp6: mcasp@2b60000 {
1463 compatible = "ti,am33xx-mcasp-audio";
1464 reg = <0x0 0x02b60000 0x0 0x2000>,
1465 <0x0 0x02b68000 0x0 0x1000>;
1466 reg-names = "mpu","dat";
1467 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1469 interrupt-names = "tx", "rx";
1471 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1472 dma-names = "tx", "rx";
1474 clocks = <&k3_clks 180 1>;
1475 clock-names = "fck";
1476 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1479 mcasp7: mcasp@2b70000 {
1480 compatible = "ti,am33xx-mcasp-audio";
1481 reg = <0x0 0x02b70000 0x0 0x2000>,
1482 <0x0 0x02b78000 0x0 0x1000>;
1483 reg-names = "mpu","dat";
1484 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1486 interrupt-names = "tx", "rx";
1488 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1489 dma-names = "tx", "rx";
1491 clocks = <&k3_clks 181 1>;
1492 clock-names = "fck";
1493 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1496 mcasp8: mcasp@2b80000 {
1497 compatible = "ti,am33xx-mcasp-audio";
1498 reg = <0x0 0x02b80000 0x0 0x2000>,
1499 <0x0 0x02b88000 0x0 0x1000>;
1500 reg-names = "mpu","dat";
1501 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1503 interrupt-names = "tx", "rx";
1505 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1506 dma-names = "tx", "rx";
1508 clocks = <&k3_clks 182 1>;
1509 clock-names = "fck";
1510 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1513 mcasp9: mcasp@2b90000 {
1514 compatible = "ti,am33xx-mcasp-audio";
1515 reg = <0x0 0x02b90000 0x0 0x2000>,
1516 <0x0 0x02b98000 0x0 0x1000>;
1517 reg-names = "mpu","dat";
1518 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1520 interrupt-names = "tx", "rx";
1522 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1523 dma-names = "tx", "rx";
1525 clocks = <&k3_clks 183 1>;
1526 clock-names = "fck";
1527 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1530 mcasp10: mcasp@2ba0000 {
1531 compatible = "ti,am33xx-mcasp-audio";
1532 reg = <0x0 0x02ba0000 0x0 0x2000>,
1533 <0x0 0x02ba8000 0x0 0x1000>;
1534 reg-names = "mpu","dat";
1535 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1537 interrupt-names = "tx", "rx";
1539 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1540 dma-names = "tx", "rx";
1542 clocks = <&k3_clks 184 1>;
1543 clock-names = "fck";
1544 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1547 mcasp11: mcasp@2bb0000 {
1548 compatible = "ti,am33xx-mcasp-audio";
1549 reg = <0x0 0x02bb0000 0x0 0x2000>,
1550 <0x0 0x02bb8000 0x0 0x1000>;
1551 reg-names = "mpu","dat";
1552 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
1554 interrupt-names = "tx", "rx";
1556 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1557 dma-names = "tx", "rx";
1559 clocks = <&k3_clks 185 1>;
1560 clock-names = "fck";
1561 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1564 watchdog0: watchdog@2200000 {
1565 compatible = "ti,j7-rti-wdt";
1566 reg = <0x0 0x2200000 0x0 0x100>;
1567 clocks = <&k3_clks 252 1>;
1568 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1569 assigned-clocks = <&k3_clks 252 1>;
1570 assigned-clock-parents = <&k3_clks 252 5>;
1573 watchdog1: watchdog@2210000 {
1574 compatible = "ti,j7-rti-wdt";
1575 reg = <0x0 0x2210000 0x0 0x100>;
1576 clocks = <&k3_clks 253 1>;
1577 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1578 assigned-clocks = <&k3_clks 253 1>;
1579 assigned-clock-parents = <&k3_clks 253 5>;
1582 main_r5fss0: r5fss@5c00000 {
1583 compatible = "ti,j721e-r5fss";
1584 ti,cluster-mode = <1>;
1585 #address-cells = <1>;
1587 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1588 <0x5d00000 0x00 0x5d00000 0x20000>;
1589 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1591 main_r5fss0_core0: r5f@5c00000 {
1592 compatible = "ti,j721e-r5f";
1593 reg = <0x5c00000 0x00008000>,
1594 <0x5c10000 0x00008000>;
1595 reg-names = "atcm", "btcm";
1597 ti,sci-dev-id = <245>;
1598 ti,sci-proc-ids = <0x06 0xff>;
1599 resets = <&k3_reset 245 1>;
1600 firmware-name = "j7-main-r5f0_0-fw";
1601 ti,atcm-enable = <1>;
1602 ti,btcm-enable = <1>;
1606 main_r5fss0_core1: r5f@5d00000 {
1607 compatible = "ti,j721e-r5f";
1608 reg = <0x5d00000 0x00008000>,
1609 <0x5d10000 0x00008000>;
1610 reg-names = "atcm", "btcm";
1612 ti,sci-dev-id = <246>;
1613 ti,sci-proc-ids = <0x07 0xff>;
1614 resets = <&k3_reset 246 1>;
1615 firmware-name = "j7-main-r5f0_1-fw";
1616 ti,atcm-enable = <1>;
1617 ti,btcm-enable = <1>;
1622 main_r5fss1: r5fss@5e00000 {
1623 compatible = "ti,j721e-r5fss";
1624 ti,cluster-mode = <1>;
1625 #address-cells = <1>;
1627 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1628 <0x5f00000 0x00 0x5f00000 0x20000>;
1629 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
1631 main_r5fss1_core0: r5f@5e00000 {
1632 compatible = "ti,j721e-r5f";
1633 reg = <0x5e00000 0x00008000>,
1634 <0x5e10000 0x00008000>;
1635 reg-names = "atcm", "btcm";
1637 ti,sci-dev-id = <247>;
1638 ti,sci-proc-ids = <0x08 0xff>;
1639 resets = <&k3_reset 247 1>;
1640 firmware-name = "j7-main-r5f1_0-fw";
1641 ti,atcm-enable = <1>;
1642 ti,btcm-enable = <1>;
1646 main_r5fss1_core1: r5f@5f00000 {
1647 compatible = "ti,j721e-r5f";
1648 reg = <0x5f00000 0x00008000>,
1649 <0x5f10000 0x00008000>;
1650 reg-names = "atcm", "btcm";
1652 ti,sci-dev-id = <248>;
1653 ti,sci-proc-ids = <0x09 0xff>;
1654 resets = <&k3_reset 248 1>;
1655 firmware-name = "j7-main-r5f1_1-fw";
1656 ti,atcm-enable = <1>;
1657 ti,btcm-enable = <1>;
1662 c66_0: dsp@4d80800000 {
1663 compatible = "ti,j721e-c66-dsp";
1664 reg = <0x4d 0x80800000 0x00 0x00048000>,
1665 <0x4d 0x80e00000 0x00 0x00008000>,
1666 <0x4d 0x80f00000 0x00 0x00008000>;
1667 reg-names = "l2sram", "l1pram", "l1dram";
1669 ti,sci-dev-id = <142>;
1670 ti,sci-proc-ids = <0x03 0xff>;
1671 resets = <&k3_reset 142 1>;
1672 firmware-name = "j7-c66_0-fw";
1675 c66_1: dsp@4d81800000 {
1676 compatible = "ti,j721e-c66-dsp";
1677 reg = <0x4d 0x81800000 0x00 0x00048000>,
1678 <0x4d 0x81e00000 0x00 0x00008000>,
1679 <0x4d 0x81f00000 0x00 0x00008000>;
1680 reg-names = "l2sram", "l1pram", "l1dram";
1682 ti,sci-dev-id = <143>;
1683 ti,sci-proc-ids = <0x04 0xff>;
1684 resets = <&k3_reset 143 1>;
1685 firmware-name = "j7-c66_1-fw";
1688 c71_0: dsp@64800000 {
1689 compatible = "ti,j721e-c71-dsp";
1690 reg = <0x00 0x64800000 0x00 0x00080000>,
1691 <0x00 0x64e00000 0x00 0x0000c000>;
1692 reg-names = "l2sram", "l1dram";
1694 ti,sci-dev-id = <15>;
1695 ti,sci-proc-ids = <0x30 0xff>;
1696 resets = <&k3_reset 15 1>;
1697 firmware-name = "j7-c71_0-fw";