arch/arm/dts/k3-j721e-common-proc-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j721e-som-p0.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/net/ti-dp83867.h>
  12 #include <dt-bindings/phy/phy-cadence.h>
  13
  14 / {
  15         chosen {
  16                 stdout-path = "serial2:115200n8";
  17                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  18         };
  19
  20         gpio_keys: gpio-keys {
  21                 compatible = "gpio-keys";
  22                 autorepeat;
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
  25
  26                 sw10: sw10 {
  27                         label = "GPIO Key USER1";
  28                         linux,code = <BTN_0>;
  29                         gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
  30                 };
  31
  32                 sw11: sw11 {
  33                         label = "GPIO Key USER2";
  34                         linux,code = <BTN_1>;
  35                         gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
  36                 };
  37         };
  38
  39         evm_12v0: fixedregulator-evm12v0 {
  40                 /* main supply */
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "evm_12v0";
  43                 regulator-min-microvolt = <12000000>;
  44                 regulator-max-microvolt = <12000000>;
  45                 regulator-always-on;
  46                 regulator-boot-on;
  47         };
  48
  49         vsys_3v3: fixedregulator-vsys3v3 {
  50                 /* Output of LMS140 */
  51                 compatible = "regulator-fixed";
  52                 regulator-name = "vsys_3v3";
  53                 regulator-min-microvolt = <3300000>;
  54                 regulator-max-microvolt = <3300000>;
  55                 vin-supply = <&evm_12v0>;
  56                 regulator-always-on;
  57                 regulator-boot-on;
  58         };
  59
  60         vsys_5v0: fixedregulator-vsys5v0 {
  61                 /* Output of LM5140 */
  62                 compatible = "regulator-fixed";
  63                 regulator-name = "vsys_5v0";
  64                 regulator-min-microvolt = <5000000>;
  65                 regulator-max-microvolt = <5000000>;
  66                 vin-supply = <&evm_12v0>;
  67                 regulator-always-on;
  68                 regulator-boot-on;
  69         };
  70
  71         vdd_mmc1: fixedregulator-sd {
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "vdd_mmc1";
  74                 regulator-min-microvolt = <3300000>;
  75                 regulator-max-microvolt = <3300000>;
  76                 regulator-boot-on;
  77                 enable-active-high;
  78                 vin-supply = <&vsys_3v3>;
  79                 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
  80         };
  81
  82         vdd_sd_dv_alt: gpio-regulator-TLV71033 {
  83                 compatible = "regulator-gpio";
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
  86                 regulator-name = "tlv71033";
  87                 regulator-min-microvolt = <1800000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 regulator-boot-on;
  90                 vin-supply = <&vsys_5v0>;
  91                 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
  92                 states = <1800000 0x0>,
  93                          <3300000 0x1>;
  94         };
  95
  96         sound0: sound@0 {
  97                 compatible = "ti,j721e-cpb-audio";
  98                 model = "j721e-cpb";
  99
 100                 ti,cpb-mcasp = <&mcasp10>;
 101                 ti,cpb-codec = <&pcm3168a_1>;
 102
 103                 clocks = <&k3_clks 184 1>,
 104                          <&k3_clks 184 2>, <&k3_clks 184 4>,
 105                          <&k3_clks 157 371>,
 106                          <&k3_clks 157 400>, <&k3_clks 157 401>;
 107                 clock-names = "cpb-mcasp-auxclk",
 108                               "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
 109                               "cpb-codec-scki",
 110                               "cpb-codec-scki-48000", "cpb-codec-scki-44100";
 111         };
 112 };
 113
 114 &main_pmx0 {
 115         sw10_button_pins_default: sw10-button-pins-default {
 116                 pinctrl-single,pins = <
 117                         J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
 118                 >;
 119         };
 120
 121         main_mmc1_pins_default: main-mmc1-pins-default {
 122                 pinctrl-single,pins = <
 123                         J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
 124                         J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
 125                         J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
 126                         J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
 127                         J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
 128                         J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
 129                         J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
 130                         J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
 131                         J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
 132                 >;
 133         };
 134
 135         vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
 136                 pinctrl-single,pins = <
 137                         J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
 138                 >;
 139         };
 140
 141         main_usbss0_pins_default: main-usbss0-pins-default {
 142                 pinctrl-single,pins = <
 143                         J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
 144                         J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 145                 >;
 146         };
 147
 148         main_usbss1_pins_default: main-usbss1-pins-default {
 149                 pinctrl-single,pins = <
 150                         J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
 151                 >;
 152         };
 153
 154         main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
 155                 pinctrl-single,pins = <
 156                         J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
 157                 >;
 158         };
 159
 160         main_i2c0_pins_default: main-i2c0-pins-default {
 161                 pinctrl-single,pins = <
 162                         J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
 163                         J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
 164                 >;
 165         };
 166
 167         main_i2c1_pins_default: main-i2c1-pins-default {
 168                 pinctrl-single,pins = <
 169                         J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
 170                         J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
 171                 >;
 172         };
 173
 174         main_i2c3_pins_default: main-i2c3-pins-default {
 175                 pinctrl-single,pins = <
 176                         J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
 177                         J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
 178                 >;
 179         };
 180
 181         main_i2c6_pins_default: main-i2c6-pins-default {
 182                 pinctrl-single,pins = <
 183                         J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
 184                         J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
 185                 >;
 186         };
 187
 188         mcasp10_pins_default: mcasp10-pins-default {
 189                 pinctrl-single,pins = <
 190                         J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
 191                         J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
 192                         J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
 193                         J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
 194                         J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
 195                         J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
 196                         J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
 197                         J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
 198                         J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
 199                 >;
 200         };
 201
 202         audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
 203                 pinctrl-single,pins = <
 204                         J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
 205                 >;
 206         };
 207 };
 208
 209 &wkup_pmx0 {
 210         sw11_button_pins_default: sw11-button-pins-default {
 211                 pinctrl-single,pins = <
 212                         J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
 213                 >;
 214         };
 215
 216         wkup_gpio_pins_default: wkup-gpio-pins-default {
 217                 pinctrl-single,pins = <
 218                         J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
 219                 >;
 220         };
 221
 222         mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
 223                 pinctrl-single,pins = <
 224                         J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
 225                         J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
 226                         J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
 227                         J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
 228                         J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
 229                         J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
 230                         J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
 231                         J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
 232                 >;
 233         };
 234
 235         mcu_cpsw_pins_default: mcu-cpsw-pins-default {
 236                 pinctrl-single,pins = <
 237                         J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
 238                         J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
 239                         J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
 240                         J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
 241                         J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
 242                         J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
 243                         J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
 244                         J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
 245                         J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
 246                         J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
 247                         J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
 248                         J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
 249                 >;
 250         };
 251
 252         mcu_mdio_pins_default: mcu-mdio1-pins-default {
 253                 pinctrl-single,pins = <
 254                         J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
 255                         J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
 256                 >;
 257         };
 258 };
 259
 260 &wkup_uart0 {
 261         /* Wakeup UART is used by System firmware */
 262         status = "reserved";
 263 };
 264
 265 &main_uart0 {
 266         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 267 };
 268
 269 &main_uart3 {
 270         /* UART not brought out */
 271         status = "disabled";
 272 };
 273
 274 &main_uart5 {
 275         /* UART not brought out */
 276         status = "disabled";
 277 };
 278
 279 &main_uart6 {
 280         /* UART not brought out */
 281         status = "disabled";
 282 };
 283
 284 &main_uart7 {
 285         /* UART not brought out */
 286         status = "disabled";
 287 };
 288
 289 &main_uart8 {
 290         /* UART not brought out */
 291         status = "disabled";
 292 };
 293
 294 &main_uart9 {
 295         /* UART not brought out */
 296         status = "disabled";
 297 };
 298
 299 &main_gpio2 {
 300         status = "disabled";
 301 };
 302
 303 &main_gpio3 {
 304         status = "disabled";
 305 };
 306
 307 &main_gpio4 {
 308         status = "disabled";
 309 };
 310
 311 &main_gpio5 {
 312         status = "disabled";
 313 };
 314
 315 &main_gpio6 {
 316         status = "disabled";
 317 };
 318
 319 &main_gpio7 {
 320         status = "disabled";
 321 };
 322
 323 &wkup_gpio1 {
 324         status = "disabled";
 325 };
 326
 327 &main_sdhci0 {
 328         /* eMMC */
 329         non-removable;
 330         ti,driver-strength-ohm = <50>;
 331         disable-wp;
 332 };
 333
 334 &main_sdhci1 {
 335         /* SD/MMC */
 336         vmmc-supply = <&vdd_mmc1>;
 337         vqmmc-supply = <&vdd_sd_dv_alt>;
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&main_mmc1_pins_default>;
 340         ti,driver-strength-ohm = <50>;
 341         disable-wp;
 342 };
 343
 344 &main_sdhci2 {
 345         /* Unused */
 346         status = "disabled";
 347 };
 348
 349 &usb_serdes_mux {
 350         idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
 351 };
 352
 353 &serdes_ln_ctrl {
 354         idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
 355                       <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
 356                       <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
 357                       <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
 358                       <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 359                       <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 360 };
 361
 362 &serdes_wiz3 {
 363         typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
 364         typec-dir-debounce-ms = <700>;  /* TUSB321, tCCB_DEFAULT 133 ms */
 365 };
 366
 367 &serdes3 {
 368         serdes3_usb_link: phy@0 {
 369                 reg = <0>;
 370                 cdns,num-lanes = <2>;
 371                 #phy-cells = <0>;
 372                 cdns,phy-type = <PHY_TYPE_USB3>;
 373                 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
 374         };
 375 };
 376
 377 &usbss0 {
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&main_usbss0_pins_default>;
 380         ti,vbus-divider;
 381 };
 382
 383 &usb0 {
 384         dr_mode = "otg";
 385         maximum-speed = "super-speed";
 386         phys = <&serdes3_usb_link>;
 387         phy-names = "cdns3,usb3-phy";
 388 };
 389
 390 &wkup_gpio0 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&wkup_gpio_pins_default>;
 393 };
 394
 395 &usbss1 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&main_usbss1_pins_default>;
 398         ti,usb2-only;
 399 };
 400
 401 &usb1 {
 402         dr_mode = "host";
 403         maximum-speed = "high-speed";
 404 };
 405
 406 &ospi1 {
 407         pinctrl-names = "default";
 408         pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
 409
 410         flash@0{
 411                 compatible = "jedec,spi-nor";
 412                 reg = <0x0>;
 413                 spi-tx-bus-width = <1>;
 414                 spi-rx-bus-width = <4>;
 415                 spi-max-frequency = <40000000>;
 416                 cdns,tshsl-ns = <60>;
 417                 cdns,tsd2d-ns = <60>;
 418                 cdns,tchsh-ns = <60>;
 419                 cdns,tslch-ns = <60>;
 420                 cdns,read-delay = <2>;
 421                 #address-cells = <1>;
 422                 #size-cells = <1>;
 423         };
 424 };
 425
 426 &tscadc0 {
 427         adc {
 428                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 429         };
 430 };
 431
 432 &tscadc1 {
 433         adc {
 434                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 435         };
 436 };
 437
 438 &main_i2c0 {
 439         pinctrl-names = "default";
 440         pinctrl-0 = <&main_i2c0_pins_default>;
 441         clock-frequency = <400000>;
 442
 443         exp1: gpio@20 {
 444                 compatible = "ti,tca6416";
 445                 reg = <0x20>;
 446                 gpio-controller;
 447                 #gpio-cells = <2>;
 448         };
 449
 450         exp2: gpio@22 {
 451                 compatible = "ti,tca6424";
 452                 reg = <0x22>;
 453                 gpio-controller;
 454                 #gpio-cells = <2>;
 455
 456                 p09-hog {
 457                         /* P11 - MCASP/TRACE_MUX_S0 */
 458                         gpio-hog;
 459                         gpios = <9 GPIO_ACTIVE_HIGH>;
 460                         output-low;
 461                         line-name = "MCASP/TRACE_MUX_S0";
 462                 };
 463
 464                 p10-hog {
 465                         /* P12 - MCASP/TRACE_MUX_S1 */
 466                         gpio-hog;
 467                         gpios = <10 GPIO_ACTIVE_HIGH>;
 468                         output-high;
 469                         line-name = "MCASP/TRACE_MUX_S1";
 470                 };
 471         };
 472 };
 473
 474 &main_i2c1 {
 475         pinctrl-names = "default";
 476         pinctrl-0 = <&main_i2c1_pins_default>;
 477         clock-frequency = <400000>;
 478
 479         exp4: gpio@20 {
 480                 compatible = "ti,tca6408";
 481                 reg = <0x20>;
 482                 gpio-controller;
 483                 #gpio-cells = <2>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
 486                 interrupt-parent = <&main_gpio1>;
 487                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 488                 interrupt-controller;
 489                 #interrupt-cells = <2>;
 490         };
 491 };
 492
 493 &k3_clks {
 494         /* Confiure AUDIO_EXT_REFCLK2 pin as output */
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&audi_ext_refclk2_pins_default>;
 497 };
 498
 499 &main_i2c3 {
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&main_i2c3_pins_default>;
 502         clock-frequency = <400000>;
 503
 504         exp3: gpio@20 {
 505                 compatible = "ti,tca6408";
 506                 reg = <0x20>;
 507                 gpio-controller;
 508                 #gpio-cells = <2>;
 509         };
 510
 511         pcm3168a_1: audio-codec@44 {
 512                 compatible = "ti,pcm3168a";
 513                 reg = <0x44>;
 514
 515                 #sound-dai-cells = <1>;
 516
 517                 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
 518
 519                 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
 520                 clocks = <&k3_clks 157 371>;
 521                 clock-names = "scki";
 522
 523                 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
 524                 assigned-clocks = <&k3_clks 157 371>;
 525                 assigned-clock-parents = <&k3_clks 157 400>;
 526                 assigned-clock-rates = <24576000>; /* for 48KHz */
 527
 528                 VDD1-supply = <&vsys_3v3>;
 529                 VDD2-supply = <&vsys_3v3>;
 530                 VCCAD1-supply = <&vsys_5v0>;
 531                 VCCAD2-supply = <&vsys_5v0>;
 532                 VCCDA1-supply = <&vsys_5v0>;
 533                 VCCDA2-supply = <&vsys_5v0>;
 534         };
 535 };
 536
 537 &main_i2c6 {
 538         pinctrl-names = "default";
 539         pinctrl-0 = <&main_i2c6_pins_default>;
 540         clock-frequency = <400000>;
 541
 542         exp5: gpio@20 {
 543                 compatible = "ti,tca6408";
 544                 reg = <0x20>;
 545                 gpio-controller;
 546                 #gpio-cells = <2>;
 547         };
 548 };
 549
 550 &mcu_cpsw {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 553 };
 554
 555 &davinci_mdio {
 556         phy0: ethernet-phy@0 {
 557                 reg = <0>;
 558                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 559                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 560         };
 561 };
 562
 563 &cpsw_port1 {
 564         phy-mode = "rgmii-rxid";
 565         phy-handle = <&phy0>;
 566 };
 567
 568 &dss {
 569         /*
 570          * These clock assignments are chosen to enable the following outputs:
 571          *
 572          * VP0 - DisplayPort SST
 573          * VP1 - DPI0
 574          * VP2 - DSI
 575          * VP3 - DPI1
 576          */
 577
 578         assigned-clocks = <&k3_clks 152 1>,
 579                           <&k3_clks 152 4>,
 580                           <&k3_clks 152 9>,
 581                           <&k3_clks 152 13>;
 582         assigned-clock-parents = <&k3_clks 152 2>,      /* PLL16_HSDIV0 */
 583                                  <&k3_clks 152 6>,      /* PLL19_HSDIV0 */
 584                                  <&k3_clks 152 11>,     /* PLL18_HSDIV0 */
 585                                  <&k3_clks 152 18>;     /* PLL23_HSDIV0 */
 586 };
 587
 588 &mcasp0 {
 589         status = "disabled";
 590 };
 591
 592 &mcasp1 {
 593         status = "disabled";
 594 };
 595
 596 &mcasp2 {
 597         status = "disabled";
 598 };
 599
 600 &mcasp3 {
 601         status = "disabled";
 602 };
 603
 604 &mcasp4 {
 605         status = "disabled";
 606 };
 607
 608 &mcasp5 {
 609         status = "disabled";
 610 };
 611
 612 &mcasp6 {
 613         status = "disabled";
 614 };
 615
 616 &mcasp7 {
 617         status = "disabled";
 618 };
 619
 620 &mcasp8 {
 621         status = "disabled";
 622 };
 623
 624 &mcasp9 {
 625         status = "disabled";
 626 };
 627
 628 &mcasp10 {
 629         #sound-dai-cells = <0>;
 630
 631         pinctrl-names = "default";
 632         pinctrl-0 = <&mcasp10_pins_default>;
 633
 634         op-mode = <0>;          /* MCASP_IIS_MODE */
 635         tdm-slots = <2>;
 636         auxclk-fs-ratio = <256>;
 637
 638         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 639                 1 1 1 1
 640                 2 2 2 0
 641         >;
 642         tx-num-evt = <0>;
 643         rx-num-evt = <0>;
 644 };
 645
 646 &mcasp11 {
 647         status = "disabled";
 648 };
 649
 650 &cmn_refclk1 {
 651         clock-frequency = <100000000>;
 652 };
 653
 654 &wiz0_pll1_refclk {
 655         assigned-clocks = <&wiz0_pll1_refclk>;
 656         assigned-clock-parents = <&cmn_refclk1>;
 657 };
 658
 659 &wiz0_refclk_dig {
 660         assigned-clocks = <&wiz0_refclk_dig>;
 661         assigned-clock-parents = <&cmn_refclk1>;
 662 };
 663
 664 &wiz1_pll1_refclk {
 665         assigned-clocks = <&wiz1_pll1_refclk>;
 666         assigned-clock-parents = <&cmn_refclk1>;
 667 };
 668
 669 &wiz1_refclk_dig {
 670         assigned-clocks = <&wiz1_refclk_dig>;
 671         assigned-clock-parents = <&cmn_refclk1>;
 672 };
 673
 674 &wiz2_pll1_refclk {
 675         assigned-clocks = <&wiz2_pll1_refclk>;
 676         assigned-clock-parents = <&cmn_refclk1>;
 677 };
 678
 679 &wiz2_refclk_dig {
 680         assigned-clocks = <&wiz2_refclk_dig>;
 681         assigned-clock-parents = <&cmn_refclk1>;
 682 };
 683
 684 &serdes0 {
 685         assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
 686         assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
 687
 688         serdes0_pcie_link: phy@0 {
 689                 reg = <0>;
 690                 cdns,num-lanes = <1>;
 691                 #phy-cells = <0>;
 692                 cdns,phy-type = <PHY_TYPE_PCIE>;
 693                 resets = <&serdes_wiz0 1>;
 694         };
 695
 696         serdes0_qsgmii_link: phy@1 {
 697                 reg = <1>;
 698                 cdns,num-lanes = <1>;
 699                 #phy-cells = <0>;
 700                 cdns,phy-type = <PHY_TYPE_QSGMII>;
 701                 resets = <&serdes_wiz0 2>;
 702         };
 703 };
 704
 705 &serdes1 {
 706         assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
 707         assigned-clock-parents = <&wiz1_pll1_refclk>;
 708
 709         serdes1_pcie_link: phy@0 {
 710                 reg = <0>;
 711                 cdns,num-lanes = <2>;
 712                 #phy-cells = <0>;
 713                 cdns,phy-type = <PHY_TYPE_PCIE>;
 714                 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
 715         };
 716 };
 717
 718 &serdes2 {
 719         assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
 720         assigned-clock-parents = <&wiz2_pll1_refclk>;
 721
 722         serdes2_pcie_link: phy@0 {
 723                 reg = <0>;
 724                 cdns,num-lanes = <2>;
 725                 #phy-cells = <0>;
 726                 cdns,phy-type = <PHY_TYPE_PCIE>;
 727                 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
 728         };
 729 };
 730
 731 &pcie0_rc {
 732         reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
 733         phys = <&serdes0_pcie_link>;
 734         phy-names = "pcie-phy";
 735         num-lanes = <1>;
 736 };
 737
 738 &pcie1_rc {
 739         reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 740         phys = <&serdes1_pcie_link>;
 741         phy-names = "pcie-phy";
 742         num-lanes = <2>;
 743 };
 744
 745 &pcie2_rc {
 746         reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
 747         phys = <&serdes2_pcie_link>;
 748         phy-names = "pcie-phy";
 749         num-lanes = <2>;
 750 };
 751
 752 &pcie0_ep {
 753         phys = <&serdes0_pcie_link>;
 754         phy-names = "pcie-phy";
 755         num-lanes = <1>;
 756         status = "disabled";
 757 };
 758
 759 &pcie1_ep {
 760         phys = <&serdes1_pcie_link>;
 761         phy-names = "pcie-phy";
 762         num-lanes = <2>;
 763         status = "disabled";
 764 };
 765
 766 &pcie2_ep {
 767         phys = <&serdes2_pcie_link>;
 768         phy-names = "pcie-phy";
 769         num-lanes = <2>;
 770         status = "disabled";
 771 };
 772
 773 &pcie3_rc {
 774         status = "disabled";
 775 };
 776
 777 &pcie3_ep {
 778         status = "disabled";
 779 };
 780
 781 &dss {
 782         status = "disabled";
 783 };
 784
 785 &icssg0_mdio {
 786         status = "disabled";
 787 };
 788
 789 &icssg1_mdio {
 790         status = "disabled";
 791 };