arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/net/ti-dp83867.h>
   7
   8 / {
   9         chosen {
  10                 stdout-path = "serial2:115200n8";
  11                 tick-timer = &timer1;
  12         };
  13
  14         aliases {
  15                 ethernet0 = &cpsw_port1;
  16         };
  17 };
  18
  19 &cbass_main{
  20         u-boot,dm-spl;
  21 };
  22
  23 &cbass_mcu_wakeup {
  24         u-boot,dm-spl;
  25
  26         timer1: timer@40400000 {
  27                 compatible = "ti,omap5430-timer";
  28                 reg = <0x0 0x40400000 0x0 0x80>;
  29                 ti,timer-alwon;
  30                 clock-frequency = <25000000>;
  31                 u-boot,dm-spl;
  32         };
  33
  34         mcu_navss {
  35                 u-boot,dm-spl;
  36
  37                 ringacc@2b800000 {
  38                         u-boot,dm-spl;
  39                 };
  40
  41                 dma-controller@285c0000 {
  42                         u-boot,dm-spl;
  43                 };
  44         };
  45 };
  46
  47 &secure_proxy_main {
  48         u-boot,dm-spl;
  49 };
  50
  51 &dmsc {
  52         u-boot,dm-spl;
  53         k3_sysreset: sysreset-controller {
  54                 compatible = "ti,sci-sysreset";
  55                 u-boot,dm-spl;
  56         };
  57 };
  58
  59 &k3_pds {
  60         u-boot,dm-spl;
  61 };
  62
  63 &k3_clks {
  64         u-boot,dm-spl;
  65 };
  66
  67 &k3_reset {
  68         u-boot,dm-spl;
  69 };
  70
  71 &wkup_pmx0 {
  72         u-boot,dm-spl;
  73         mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  74                 pinctrl-single,pins = <
  75                         J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  76                         J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  77                         J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  78                         J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  79                         J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  80                         J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  81                         J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  82                         J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  83                         J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  84                         J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  85                         J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  86                         J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  87                 >;
  88         };
  89
  90         mcu_mdio_pins_default: mcu_mdio1_pins_default {
  91                 pinctrl-single,pins = <
  92                         J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  93                         J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  94                 >;
  95         };
  96 };
  97
  98 &main_pmx0 {
  99         u-boot,dm-spl;
 100 };
 101
 102 &main_uart0 {
 103         u-boot,dm-spl;
 104 };
 105
 106 &mcu_uart0 {
 107         u-boot,dm-spl;
 108 };
 109
 110 &main_sdhci0 {
 111         u-boot,dm-spl;
 112 };
 113
 114 &main_sdhci1 {
 115         u-boot,dm-spl;
 116 };
 117
 118 &main_usbss0_pins_default {
 119         u-boot,dm-spl;
 120 };
 121
 122 &usbss0 {
 123         u-boot,dm-spl;
 124         ti,usb2-only;
 125 };
 126
 127 &usb0 {
 128         dr_mode = "peripheral";
 129         u-boot,dm-spl;
 130 };
 131
 132 &mcu_cpsw {
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 135 };
 136
 137 &davinci_mdio {
 138         phy0: ethernet-phy@0 {
 139                 reg = <0>;
 140                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 141                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 142         };
 143 };
 144
 145 &cpsw_port1 {
 146         phy-mode = "rgmii-rxid";
 147         phy-handle = <&phy0>;
 148 };
 149
 150 &mcu_cpsw {
 151         reg = <0x0 0x46000000 0x0 0x200000>,
 152               <0x0 0x40f00200 0x0 0x2>;
 153         reg-names = "cpsw_nuss", "mac_efuse";
 154         /delete-property/ ranges;
 155
 156         cpsw-phy-sel@40f04040 {
 157                 compatible = "ti,am654-cpsw-phy-sel";
 158                 reg= <0x0 0x40f04040 0x0 0x4>;
 159                 reg-names = "gmii-sel";
 160         };
 161 };
 162
 163 &main_mmc1_pins_default {
 164         u-boot,dm-spl;
 165 };
 166
 167 &wkup_i2c0_pins_default {
 168         u-boot,dm-spl;
 169 };
 170
 171 &wkup_i2c0 {
 172         u-boot,dm-spl;
 173 };
 174
 175 &main_i2c0 {
 176         u-boot,dm-spl;
 177 };
 178
 179 &main_i2c0_pins_default {
 180         u-boot,dm-spl;
 181 };
 182
 183 &exp2 {
 184         u-boot,dm-spl;
 185 };
 186
 187 &mcu_fss0_ospi0_pins_default {
 188         u-boot,dm-spl;
 189 };
 190
 191 &fss {
 192         u-boot,dm-spl;
 193 };
 194
 195 &ospi0 {
 196         u-boot,dm-spl;
 197
 198         flash@0 {
 199                 u-boot,dm-spl;
 200         };
 201 };
 202
 203 &ospi1 {
 204         u-boot,dm-spl;
 205
 206         flash@0 {
 207                 u-boot,dm-spl;
 208         };
 209 };
 210
 211 &mcu_fss0_ospi1_pins_default {
 212         u-boot,dm-spl;
 213 };
 214
 215 &chipid {
 216         u-boot,dm-spl;
 217 };