arch/arm/dts/k3-j7200.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family
   4  *
   5  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/k3.h>
  11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
  12
  13 / {
  14         model = "Texas Instruments K3 J7200 SoC";
  15         compatible = "ti,j7200";
  16         interrupt-parent = <&gic500>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &wkup_uart0;
  22                 serial1 = &mcu_uart0;
  23                 serial2 = &main_uart0;
  24                 serial3 = &main_uart1;
  25                 serial4 = &main_uart2;
  26                 serial5 = &main_uart3;
  27                 serial6 = &main_uart4;
  28                 serial7 = &main_uart5;
  29                 serial8 = &main_uart6;
  30                 serial9 = &main_uart7;
  31                 serial10 = &main_uart8;
  32                 serial11 = &main_uart9;
  33                 i2c0 = &wkup_i2c0;
  34                 i2c1 = &mcu_i2c0;
  35                 i2c2 = &mcu_i2c1;
  36                 i2c3 = &main_i2c0;
  37                 i2c4 = &main_i2c1;
  38                 i2c5 = &main_i2c2;
  39                 i2c6 = &main_i2c3;
  40                 i2c7 = &main_i2c4;
  41                 i2c8 = &main_i2c5;
  42                 i2c9 = &main_i2c6;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 cpu-map {
  49                         cluster0: cluster0 {
  50                                 core0 {
  51                                         cpu = <&cpu0>;
  52                                 };
  53
  54                                 core1 {
  55                                         cpu = <&cpu1>;
  56                                 };
  57                         };
  58
  59                 };
  60
  61                 cpu0: cpu@0 {
  62                         compatible = "arm,cortex-a72";
  63                         reg = <0x000>;
  64                         device_type = "cpu";
  65                         enable-method = "psci";
  66                         i-cache-size = <0xC000>;
  67                         i-cache-line-size = <64>;
  68                         i-cache-sets = <256>;
  69                         d-cache-size = <0x8000>;
  70                         d-cache-line-size = <64>;
  71                         d-cache-sets = <128>;
  72                         next-level-cache = <&L2_0>;
  73                 };
  74
  75                 cpu1: cpu@1 {
  76                         compatible = "arm,cortex-a72";
  77                         reg = <0x001>;
  78                         device_type = "cpu";
  79                         enable-method = "psci";
  80                         i-cache-size = <0xC000>;
  81                         i-cache-line-size = <64>;
  82                         i-cache-sets = <256>;
  83                         d-cache-size = <0x8000>;
  84                         d-cache-line-size = <64>;
  85                         d-cache-sets = <128>;
  86                         next-level-cache = <&L2_0>;
  87                 };
  88         };
  89
  90         L2_0: l2-cache0 {
  91                 compatible = "cache";
  92                 cache-level = <2>;
  93                 cache-size = <0x100000>;
  94                 cache-line-size = <64>;
  95                 cache-sets = <2048>;
  96                 next-level-cache = <&msmc_l3>;
  97         };
  98
  99         msmc_l3: l3-cache0 {
 100                 compatible = "cache";
 101                 cache-level = <3>;
 102         };
 103
 104         firmware {
 105                 optee {
 106                         compatible = "linaro,optee-tz";
 107                         method = "smc";
 108                 };
 109
 110                 psci: psci {
 111                         compatible = "arm,psci-1.0";
 112                         method = "smc";
 113                 };
 114         };
 115
 116         a72_timer0: timer-cl0-cpu0 {
 117                 compatible = "arm,armv8-timer";
 118                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 119                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 120                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 121                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 122         };
 123
 124         pmu: pmu {
 125                 compatible = "arm,armv8-pmuv3";
 126                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 127         };
 128
 129         cbass_main: bus@100000 {
 130                 compatible = "simple-bus";
 131                 #address-cells = <2>;
 132                 #size-cells = <2>;
 133                 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
 134                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
 135                          <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
 136                          <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
 137                          <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
 138                          <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
 139                          <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
 140
 141                          /* MCUSS_WKUP Range */
 142                          <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
 143                          <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
 144                          <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
 145                          <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
 146                          <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
 147                          <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
 148                          <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
 149                          <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
 150                          <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
 151                          <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
 152                          <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
 153                          <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>;
 154
 155                 cbass_mcu_wakeup: bus@28380000 {
 156                         compatible = "simple-bus";
 157                         #address-cells = <2>;
 158                         #size-cells = <2>;
 159                         ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
 160                                  <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
 161                                  <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
 162                                  <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
 163                                  <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
 164                                  <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
 165                                  <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
 166                                  <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
 167                                  <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
 168                                  <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
 169                                  <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
 170                                  <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>; /* FSS OSPI0 data region 3 */
 171                 };
 172         };
 173 };
 174
 175 /* Now include the peripherals for each bus segments */
 176 #include "k3-j7200-main.dtsi"
 177 #include "k3-j7200-mcu-wakeup.dtsi"