arch/arm/dts/k3-j7200-r5-common-proc-board.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "k3-j7200-som-p0.dtsi"
   9 #include "k3-j7200-ddr-evm-lp4-1600.dtsi"
  10 #include "k3-j721e-ddr.dtsi"
  11
  12 / {
  13         aliases {
  14                 remoteproc0 = &sysctrler;
  15                 remoteproc1 = &a72_0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &main_uart0;
  20                 tick-timer = &timer1;
  21                 firmware-loader = &fs_loader0;
  22         };
  23
  24         fs_loader0: fs_loader@0 {
  25                 u-boot,dm-pre-reloc;
  26                 compatible = "u-boot,fs-loader";
  27         };
  28
  29         a72_0: a72@0 {
  30                 compatible = "ti,am654-rproc";
  31                 reg = <0x0 0x00a90000 0x0 0x10>;
  32                 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  33                                 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
  34                 resets = <&k3_reset 202 0>;
  35                 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
  36                 assigned-clock-rates = <2000000000>, <200000000>;
  37                 ti,sci = <&dmsc>;
  38                 ti,sci-proc-id = <32>;
  39                 ti,sci-host-id = <10>;
  40                 u-boot,dm-spl;
  41         };
  42
  43         clk_200mhz: dummy_clock_200mhz {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <200000000>;
  47                 u-boot,dm-spl;
  48         };
  49
  50         clk_19_2mhz: dummy_clock_19_2mhz {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 clock-frequency = <19200000>;
  54                 u-boot,dm-spl;
  55         };
  56 };
  57
  58 &memorycontroller {
  59         power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
  60                         <&k3_pds 90 TI_SCI_PD_SHARED>;
  61         clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
  62 };
  63
  64 &cbass_mcu_wakeup {
  65         mcu_secproxy: secproxy@2a380000 {
  66                 u-boot,dm-spl;
  67                 compatible = "ti,am654-secure-proxy";
  68                 reg = <0x0 0x2a380000 0x0 0x80000>,
  69                       <0x0 0x2a400000 0x0 0x80000>,
  70                       <0x0 0x2a480000 0x0 0x80000>;
  71                 reg-names = "rt", "scfg", "target_data";
  72                 #mbox-cells = <1>;
  73         };
  74
  75         sysctrler: sysctrler {
  76                 u-boot,dm-spl;
  77                 compatible = "ti,am654-system-controller";
  78                 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
  79                 mbox-names = "tx", "rx";
  80         };
  81 };
  82
  83 &dmsc {
  84         mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
  85         mbox-names = "tx", "rx", "notify";
  86         ti,host-id = <4>;
  87         ti,secure-host;
  88 };
  89
  90 &wkup_pmx0 {
  91         u-boot,dm-spl;
  92         wkup_uart0_pins_default: wkup_uart0_pins_default {
  93                 u-boot,dm-spl;
  94                 pinctrl-single,pins = <
  95                         J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
  96                         J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
  97                 >;
  98         };
  99
 100         mcu_uart0_pins_default: mcu_uart0_pins_default {
 101                 u-boot,dm-spl;
 102                 pinctrl-single,pins = <
 103                         J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
 104                         J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
 105                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
 106                         J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
 107                 >;
 108         };
 109
 110         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
 111                 pinctrl-single,pins = <
 112                         J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
 113                         J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
 114                 >;
 115         };
 116
 117         mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
 118                 pinctrl-single,pins = <
 119                         J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
 120                         J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
 121                         J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
 122                         J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
 123                         J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
 124                         J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
 125                         J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
 126                         J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
 127                         J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
 128                         J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
 129                         J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
 130                         J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
 131                         J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
 132                         J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
 133                 >;
 134         };
 135
 136         wkup_gpio_pins_default: wkup-gpio-pins-default {
 137                 pinctrl-single,pins = <
 138                         J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
 139                 >;
 140         };
 141 };
 142
 143 &main_pmx0 {
 144         u-boot,dm-spl;
 145
 146         main_uart0_pins_default: main_uart0_pins_default {
 147                 u-boot,dm-spl;
 148                 pinctrl-single,pins = <
 149                         J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
 150                         J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
 151                         J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
 152                         J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
 153                 >;
 154         };
 155
 156         main_i2c0_pins_default: main-i2c0-pins-default {
 157                 u-boot,dm-spl;
 158                 pinctrl-single,pins = <
 159                         J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
 160                         J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
 161                 >;
 162         };
 163
 164         main_usbss0_pins_default: main_usbss0_pins_default {
 165                 pinctrl-single,pins = <
 166                         J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
 167                 >;
 168         };
 169 };
 170
 171 &wkup_uart0 {
 172         u-boot,dm-spl;
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&wkup_uart0_pins_default>;
 175         status = "okay";
 176 };
 177
 178 &mcu_uart0 {
 179         /delete-property/ power-domains;
 180         /delete-property/ clocks;
 181         /delete-property/ clock-names;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&mcu_uart0_pins_default>;
 184         status = "okay";
 185         clock-frequency = <96000000>;
 186 };
 187
 188 &main_uart0 {
 189         status = "okay";
 190         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&main_uart0_pins_default>;
 193         status = "okay";
 194 };
 195
 196 &main_sdhci0 {
 197         /delete-property/ power-domains;
 198         /delete-property/ assigned-clocks;
 199         /delete-property/ assigned-clock-parents;
 200         clock-names = "clk_xin";
 201         clocks = <&clk_200mhz>;
 202         ti,driver-strength-ohm = <50>;
 203         non-removable;
 204         bus-width = <8>;
 205 };
 206
 207 &main_sdhci1 {
 208         /delete-property/ power-domains;
 209         /delete-property/ assigned-clocks;
 210         /delete-property/ assigned-clock-parents;
 211         clock-names = "clk_xin";
 212         clocks = <&clk_200mhz>;
 213         ti,driver-strength-ohm = <50>;
 214 };
 215
 216 &main_i2c0 {
 217         pinctrl-names = "default";
 218         pinctrl-0 = <&main_i2c0_pins_default>;
 219         clock-frequency = <400000>;
 220
 221         exp1: gpio@20 {
 222                 compatible = "ti,tca6416";
 223                 reg = <0x20>;
 224                 gpio-controller;
 225                 #gpio-cells = <2>;
 226         };
 227
 228         exp2: gpio@22 {
 229                 compatible = "ti,tca6424";
 230                 reg = <0x22>;
 231                 gpio-controller;
 232                 #gpio-cells = <2>;
 233         };
 234 };
 235
 236 &usbss0 {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&main_usbss0_pins_default>;
 239         ti,vbus-divider;
 240         ti,usb2-only;
 241 };
 242
 243 &usb0 {
 244         dr_mode = "otg";
 245         maximum-speed = "high-speed";
 246 };
 247
 248 &hbmc {
 249         status = "okay";
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
 252         reg = <0x0 0x47040000 0x0 0x100>,
 253               <0x0 0x50000000 0x0 0x8000000>;
 254         ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
 255                  <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
 256
 257         flash@0,0 {
 258                 compatible = "cypress,hyperflash", "cfi-flash";
 259                 reg = <0x0 0x0 0x4000000>;
 260         };
 261 };
 262
 263 #include "k3-j7200-common-proc-board-u-boot.dtsi"