arch/arm/dts/k3-j7200-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         msmc_ram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x0 0x70000000 0x0 0x100000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x70000000 0x100000>;
  15
  16                 atf-sram@0 {
  17                         reg = <0x0 0x20000>;
  18                 };
  19         };
  20
  21         gic500: interrupt-controller@1800000 {
  22                 compatible = "arm,gic-v3";
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26                 #interrupt-cells = <3>;
  27                 interrupt-controller;
  28                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  29                       <0x00 0x01900000 0x00 0x100000>;  /* GICR */
  30
  31                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  32                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  33
  34                 gic_its: msi-controller@1820000 {
  35                         compatible = "arm,gic-v3-its";
  36                         reg = <0x00 0x01820000 0x00 0x10000>;
  37                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  38                         msi-controller;
  39                         #msi-cells = <1>;
  40                 };
  41         };
  42
  43         main_navss: navss@30000000 {
  44                 compatible = "simple-mfd";
  45                 #address-cells = <2>;
  46                 #size-cells = <2>;
  47                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  48
  49                 secure_proxy_main: mailbox@32c00000 {
  50                         compatible = "ti,am654-secure-proxy";
  51                         #mbox-cells = <1>;
  52                         reg-names = "target_data", "rt", "scfg";
  53                         reg = <0x00 0x32c00000 0x00 0x100000>,
  54                               <0x00 0x32400000 0x00 0x100000>,
  55                               <0x00 0x32800000 0x00 0x100000>;
  56                         interrupt-names = "rx_011";
  57                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  58                 };
  59         };
  60
  61         main_pmx0: pinmux@11c000 {
  62                 compatible = "pinctrl-single";
  63                 /* Proxy 0 addressing */
  64                 reg = <0x0 0x11c000 0x0 0x2b4>;
  65                 #pinctrl-cells = <1>;
  66                 pinctrl-single,register-width = <32>;
  67                 pinctrl-single,function-mask = <0xffffffff>;
  68         };
  69
  70         main_uart0: serial@2800000 {
  71                 compatible = "ti,j721e-uart", "ti,am654-uart";
  72                 reg = <0x00 0x02800000 0x00 0x100>;
  73                 reg-shift = <2>;
  74                 reg-io-width = <4>;
  75                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  76                 clock-frequency = <48000000>;
  77                 current-speed = <115200>;
  78                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  79                 clocks = <&k3_clks 146 2>;
  80                 clock-names = "fclk";
  81         };
  82
  83         main_uart1: serial@2810000 {
  84                 compatible = "ti,j721e-uart", "ti,am654-uart";
  85                 reg = <0x00 0x02810000 0x00 0x100>;
  86                 reg-shift = <2>;
  87                 reg-io-width = <4>;
  88                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  89                 clock-frequency = <48000000>;
  90                 current-speed = <115200>;
  91                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  92                 clocks = <&k3_clks 278 2>;
  93                 clock-names = "fclk";
  94         };
  95
  96         main_uart2: serial@2820000 {
  97                 compatible = "ti,j721e-uart", "ti,am654-uart";
  98                 reg = <0x00 0x02820000 0x00 0x100>;
  99                 reg-shift = <2>;
 100                 reg-io-width = <4>;
 101                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 102                 clock-frequency = <48000000>;
 103                 current-speed = <115200>;
 104                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 105                 clocks = <&k3_clks 279 2>;
 106                 clock-names = "fclk";
 107         };
 108
 109         main_uart3: serial@2830000 {
 110                 compatible = "ti,j721e-uart", "ti,am654-uart";
 111                 reg = <0x00 0x02830000 0x00 0x100>;
 112                 reg-shift = <2>;
 113                 reg-io-width = <4>;
 114                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 115                 clock-frequency = <48000000>;
 116                 current-speed = <115200>;
 117                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 118                 clocks = <&k3_clks 280 2>;
 119                 clock-names = "fclk";
 120         };
 121
 122         main_uart4: serial@2840000 {
 123                 compatible = "ti,j721e-uart", "ti,am654-uart";
 124                 reg = <0x00 0x02840000 0x00 0x100>;
 125                 reg-shift = <2>;
 126                 reg-io-width = <4>;
 127                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 128                 clock-frequency = <48000000>;
 129                 current-speed = <115200>;
 130                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 131                 clocks = <&k3_clks 281 2>;
 132                 clock-names = "fclk";
 133         };
 134
 135         main_uart5: serial@2850000 {
 136                 compatible = "ti,j721e-uart", "ti,am654-uart";
 137                 reg = <0x00 0x02850000 0x00 0x100>;
 138                 reg-shift = <2>;
 139                 reg-io-width = <4>;
 140                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 141                 clock-frequency = <48000000>;
 142                 current-speed = <115200>;
 143                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 144                 clocks = <&k3_clks 282 2>;
 145                 clock-names = "fclk";
 146         };
 147
 148         main_uart6: serial@2860000 {
 149                 compatible = "ti,j721e-uart", "ti,am654-uart";
 150                 reg = <0x00 0x02860000 0x00 0x100>;
 151                 reg-shift = <2>;
 152                 reg-io-width = <4>;
 153                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 154                 clock-frequency = <48000000>;
 155                 current-speed = <115200>;
 156                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 157                 clocks = <&k3_clks 283 2>;
 158                 clock-names = "fclk";
 159         };
 160
 161         main_uart7: serial@2870000 {
 162                 compatible = "ti,j721e-uart", "ti,am654-uart";
 163                 reg = <0x00 0x02870000 0x00 0x100>;
 164                 reg-shift = <2>;
 165                 reg-io-width = <4>;
 166                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 167                 clock-frequency = <48000000>;
 168                 current-speed = <115200>;
 169                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 170                 clocks = <&k3_clks 284 2>;
 171                 clock-names = "fclk";
 172         };
 173
 174         main_uart8: serial@2880000 {
 175                 compatible = "ti,j721e-uart", "ti,am654-uart";
 176                 reg = <0x00 0x02880000 0x00 0x100>;
 177                 reg-shift = <2>;
 178                 reg-io-width = <4>;
 179                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 180                 clock-frequency = <48000000>;
 181                 current-speed = <115200>;
 182                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 183                 clocks = <&k3_clks 285 2>;
 184                 clock-names = "fclk";
 185         };
 186
 187         main_uart9: serial@2890000 {
 188                 compatible = "ti,j721e-uart", "ti,am654-uart";
 189                 reg = <0x00 0x02890000 0x00 0x100>;
 190                 reg-shift = <2>;
 191                 reg-io-width = <4>;
 192                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 193                 clock-frequency = <48000000>;
 194                 current-speed = <115200>;
 195                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 196                 clocks = <&k3_clks 286 2>;
 197                 clock-names = "fclk";
 198         };
 199
 200         main_sdhci0: sdhci@4f80000 {
 201                 compatible = "ti,j721e-sdhci-8bit";
 202                 reg = <0x0 0x04f80000 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
 203                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 204                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 205                 clock-names = "clk_xin", "clk_ahb";
 206                 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
 207                 ti,otap-del-sel-legacy = <0x0>;
 208                 ti,otap-del-sel-mmc-hs = <0x0>;
 209                 ti,otap-del-sel-ddr52 = <0x6>;
 210                 ti,otap-del-sel-hs200 = <0x8>;
 211                 ti,otap-del-sel-hs400 = <0x0>;
 212                 ti,strobe-sel = <0x77>;
 213                 ti,trm-icp = <0x8>;
 214                 bus-width = <8>;
 215                 mmc-hs200-1_8v;
 216                 mmc-ddr-1_8v;
 217                 dma-coherent;
 218         };
 219
 220         main_sdhci1: sdhci@4fb0000 {
 221                 compatible = "ti,j721e-sdhci-4bit";
 222                 reg = <0x0 0x04fb0000 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
 223                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 224                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 225                 clock-names = "clk_xin", "clk_ahb";
 226                 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
 227                 ti,otap-del-sel-legacy = <0x0>;
 228                 ti,otap-del-sel-sd-hs = <0x0>;
 229                 ti,otap-del-sel-sdr12 = <0xf>;
 230                 ti,otap-del-sel-sdr25 = <0xf>;
 231                 ti,otap-del-sel-sdr50 = <0xc>;
 232                 ti,otap-del-sel-sdr104 = <0x5>;
 233                 ti,otap-del-sel-ddr50 = <0xc>;
 234                 dma-coherent;
 235         };
 236
 237         main_i2c0: i2c@2000000 {
 238                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 239                 reg = <0x0 0x2000000 0x0 0x100>;
 240                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 clock-names = "fck";
 244                 clocks = <&k3_clks 187 1>;
 245                 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
 246         };
 247
 248         main_i2c1: i2c@2010000 {
 249                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 250                 reg = <0x0 0x2010000 0x0 0x100>;
 251                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 252                 #address-cells = <1>;
 253                 #size-cells = <0>;
 254                 clock-names = "fck";
 255                 clocks = <&k3_clks 188 1>;
 256                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 257         };
 258
 259         main_i2c2: i2c@2020000 {
 260                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 261                 reg = <0x0 0x2020000 0x0 0x100>;
 262                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 clock-names = "fck";
 266                 clocks = <&k3_clks 189 1>;
 267                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 268         };
 269
 270         main_i2c3: i2c@2030000 {
 271                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 272                 reg = <0x0 0x2030000 0x0 0x100>;
 273                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 clock-names = "fck";
 277                 clocks = <&k3_clks 190 1>;
 278                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 279         };
 280
 281         main_i2c4: i2c@2040000 {
 282                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 283                 reg = <0x0 0x2040000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 clock-names = "fck";
 288                 clocks = <&k3_clks 191 1>;
 289                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 290         };
 291
 292         main_i2c5: i2c@2050000 {
 293                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 294                 reg = <0x0 0x2050000 0x0 0x100>;
 295                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 296                 #address-cells = <1>;
 297                 #size-cells = <0>;
 298                 clock-names = "fck";
 299                 clocks = <&k3_clks 192 1>;
 300                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 301         };
 302
 303         main_i2c6: i2c@2060000 {
 304                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 305                 reg = <0x0 0x2060000 0x0 0x100>;
 306                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 clock-names = "fck";
 310                 clocks = <&k3_clks 193 1>;
 311                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 312         };
 313
 314         usbss0: cdns_usb@4104000 {
 315                 compatible = "ti,j721e-usb";
 316                 reg = <0x00 0x4104000 0x00 0x100>;
 317                 dma-coherent;
 318                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 319                 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
 320                 clock-names = "usb2_refclk", "lpm_clk";
 321                 assigned-clocks = <&k3_clks 288 12>;    /* USB2_REFCLK */
 322                 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
 323                 #address-cells = <2>;
 324                 #size-cells = <2>;
 325                 ranges;
 326
 327                 usb0: usb@6000000 {
 328                         compatible = "cdns,usb3";
 329                         reg = <0x00 0x6000000 0x00 0x10000>,
 330                               <0x00 0x6010000 0x00 0x10000>,
 331                               <0x00 0x6020000 0x00 0x10000>;
 332                         reg-names = "otg", "xhci", "dev";
 333                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 334                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 335                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 336                         interrupt-names = "host",
 337                                           "peripheral",
 338                                           "otg";
 339                         maximum-speed = "super-speed";
 340                         dr_mode = "otg";
 341                 };
 342         };
 343
 344         main_r5fss0: r5fss@5c00000 {
 345                 compatible = "ti,j7200-r5fss";
 346                 lockstep-mode = <0>;
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
 350                          <0x5d00000 0x00 0x5d00000 0x20000>;
 351                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
 352
 353                 main_r5fss0_core0: r5f@5c00000 {
 354                         compatible = "ti,j7200-r5f";
 355                         reg = <0x5c00000 0x00010000>,
 356                               <0x5c10000 0x00010000>;
 357                         reg-names = "atcm", "btcm";
 358                         ti,sci = <&dmsc>;
 359                         ti,sci-dev-id = <245>;
 360                         ti,sci-proc-ids = <0x06 0xFF>;
 361                         resets = <&k3_reset 245 1>;
 362                         firmware-name = "j7200-main-r5f0_0-fw";
 363                         atcm-enable = <1>;
 364                         btcm-enable = <1>;
 365                         loczrama = <1>;
 366                 };
 367
 368                 main_r5fss0_core1: r5f@5d00000 {
 369                         compatible = "ti,j7200-r5f";
 370                         reg = <0x5d00000 0x00008000>,
 371                               <0x5d10000 0x00008000>;
 372                         reg-names = "atcm", "btcm";
 373                         ti,sci = <&dmsc>;
 374                         ti,sci-dev-id = <246>;
 375                         ti,sci-proc-ids = <0x07 0xFF>;
 376                         resets = <&k3_reset 246 1>;
 377                         firmware-name = "j7200-main-r5f0_1-fw";
 378                         atcm-enable = <1>;
 379                         btcm-enable = <1>;
 380                         loczrama = <1>;
 381                 };
 382         };
 383 };