arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 #include "k3-j7200-binman.dtsi"
   7
   8 / {
   9         chosen {
  10                 stdout-path = "serial2:115200n8";
  11                 tick-timer = &timer1;
  12         };
  13
  14         aliases {
  15                 ethernet0 = &cpsw_port1;
  16                 i2c0 = &wkup_i2c0;
  17                 i2c1 = &mcu_i2c0;
  18                 i2c2 = &mcu_i2c1;
  19                 i2c3 = &main_i2c0;
  20         };
  21 };
  22
  23 &cbass_main {
  24         bootph-pre-ram;
  25 };
  26
  27 &main_navss {
  28         bootph-pre-ram;
  29 };
  30
  31 &cbass_mcu_wakeup {
  32         bootph-pre-ram;
  33
  34         timer1: timer@40400000 {
  35                 compatible = "ti,omap5430-timer";
  36                 reg = <0x0 0x40400000 0x0 0x80>;
  37                 ti,timer-alwon;
  38                 clock-frequency = <250000000>;
  39                 bootph-pre-ram;
  40         };
  41
  42         chipid@43000014 {
  43                 bootph-pre-ram;
  44         };
  45
  46         mcu_navss: bus@28380000 {
  47                 bootph-pre-ram;
  48                 #address-cells = <2>;
  49                 #size-cells = <2>;
  50
  51                 ringacc@2b800000 {
  52                         reg =   <0x0 0x2b800000 0x0 0x400000>,
  53                                 <0x0 0x2b000000 0x0 0x400000>,
  54                                 <0x0 0x28590000 0x0 0x100>,
  55                                 <0x0 0x2a500000 0x0 0x40000>,
  56                                 <0x0 0x28440000 0x0 0x40000>;
  57                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
  58                         bootph-pre-ram;
  59                 };
  60
  61                 dma-controller@285c0000 {
  62                         reg =   <0x0 0x285c0000 0x0 0x100>,
  63                                 <0x0 0x284c0000 0x0 0x4000>,
  64                                 <0x0 0x2a800000 0x0 0x40000>,
  65                                 <0x0 0x284a0000 0x0 0x4000>,
  66                                 <0x0 0x2aa00000 0x0 0x40000>,
  67                                 <0x0 0x28400000 0x0 0x2000>;
  68                         reg-names = "gcfg", "rchan", "rchanrt", "tchan",
  69                                             "tchanrt", "rflow";
  70                         bootph-pre-ram;
  71                 };
  72         };
  73 };
  74
  75 &secure_proxy_main {
  76         bootph-pre-ram;
  77 };
  78
  79 &dmsc {
  80         bootph-pre-ram;
  81         k3_sysreset: sysreset-controller {
  82                 compatible = "ti,sci-sysreset";
  83                 bootph-pre-ram;
  84         };
  85 };
  86
  87 &k3_pds {
  88         bootph-pre-ram;
  89 };
  90
  91 &k3_clks {
  92         bootph-pre-ram;
  93 };
  94
  95 &k3_reset {
  96         bootph-pre-ram;
  97 };
  98
  99 &wkup_pmx0 {
 100         bootph-pre-ram;
 101 };
 102
 103 &main_pmx0 {
 104         bootph-pre-ram;
 105 };
 106
 107 &main_uart0 {
 108         bootph-pre-ram;
 109 };
 110
 111 &mcu_uart0 {
 112         bootph-pre-ram;
 113 };
 114
 115 &main_sdhci0 {
 116         bootph-pre-ram;
 117 };
 118
 119 &main_sdhci1 {
 120         bootph-pre-ram;
 121 };
 122
 123 &wkup_i2c0 {
 124         bootph-pre-ram;
 125 };
 126
 127 &main_i2c0 {
 128         bootph-pre-ram;
 129 };
 130
 131 &main_i2c0_pins_default {
 132         bootph-pre-ram;
 133 };
 134
 135 &exp2 {
 136         bootph-pre-ram;
 137 };
 138
 139 &mcu_cpsw {
 140         reg = <0x0 0x46000000 0x0 0x200000>,
 141               <0x0 0x40f00200 0x0 0x8>;
 142         reg-names = "cpsw_nuss", "mac_efuse";
 143         /delete-property/ ranges;
 144
 145         cpsw-phy-sel@40f04040 {
 146                 compatible = "ti,am654-cpsw-phy-sel";
 147                 reg= <0x0 0x40f04040 0x0 0x4>;
 148                 reg-names = "gmii-sel";
 149         };
 150 };
 151
 152 &main_usbss0_pins_default {
 153         bootph-pre-ram;
 154 };
 155
 156 &usbss0 {
 157         bootph-pre-ram;
 158         ti,usb2-only;
 159 };
 160
 161 &usb0 {
 162         dr_mode = "peripheral";
 163         bootph-pre-ram;
 164 };
 165
 166 &mcu_fss0_hpb0_pins_default {
 167         bootph-pre-ram;
 168 };
 169
 170 &fss {
 171         bootph-pre-ram;
 172 };
 173
 174 &hbmc {
 175         bootph-pre-ram;
 176
 177         flash@0,0 {
 178                 bootph-pre-ram;
 179         };
 180 };
 181
 182 &hbmc_mux {
 183         bootph-pre-ram;
 184 };
 185
 186 &serdes_ln_ctrl {
 187         u-boot,mux-autoprobe;
 188 };
 189
 190 &usb_serdes_mux {
 191         u-boot,mux-autoprobe;
 192 };
 193
 194 &serdes0 {
 195         bootph-pre-ram;
 196 };
 197
 198 &main_r5fss0 {
 199         ti,cluster-mode = <0>;
 200 };