arch/arm/dts/k3-am654-base-board-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/pinctrl/k3.h>
   7 #include <dt-bindings/net/ti-dp83867.h>
   8
   9 / {
  10         chosen {
  11                 stdout-path = "serial2:115200n8";
  12         };
  13
  14         aliases {
  15                 serial2 = &main_uart0;
  16                 ethernet0 = &cpsw_port1;
  17         };
  18 };
  19
  20 &cbass_main{
  21         u-boot,dm-spl;
  22
  23         sdhci1: sdhci@04FA0000 {
  24                 compatible = "ti,am654-sdhci-5.1";
  25                 reg = <0x0 0x4FA0000 0x0 0x1000>,
  26                       <0x0 0x4FB0000 0x0 0x400>;
  27                 clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
  28                 clock-names = "clk_ahb", "clk_xin";
  29                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  30                 max-frequency = <25000000>;
  31                 ti,otap-del-sel-legacy = <0x0>;
  32                 ti,otap-del-sel-mmc-hs = <0x0>;
  33                 ti,otap-del-sel-sd-hs = <0x0>;
  34                 ti,otap-del-sel-sdr12 = <0x0>;
  35                 ti,otap-del-sel-sdr25 = <0x0>;
  36                 ti,otap-del-sel-sdr50 = <0x8>;
  37                 ti,otap-del-sel-sdr104 = <0x7>;
  38                 ti,otap-del-sel-ddr50 = <0x4>;
  39                 ti,otap-del-sel-ddr52 = <0x4>;
  40                 ti,otap-del-sel-hs200 = <0x7>;
  41                 ti,trm-icp = <0x8>;
  42         };
  43
  44 };
  45
  46 &cbass_mcu {
  47         u-boot,dm-spl;
  48
  49         mcu_navss {
  50                 u-boot,dm-spl;
  51
  52                 ringacc@2b800000 {
  53                         u-boot,dm-spl;
  54                 };
  55
  56                 dma-controller@285c0000 {
  57                         u-boot,dm-spl;
  58                 };
  59         };
  60 };
  61
  62 &cbass_wakeup {
  63         u-boot,dm-spl;
  64 };
  65
  66 &secure_proxy_main {
  67         u-boot,dm-spl;
  68 };
  69
  70 &dmsc {
  71         u-boot,dm-spl;
  72         k3_sysreset: sysreset-controller {
  73                 compatible = "ti,sci-sysreset";
  74                 u-boot,dm-spl;
  75         };
  76 };
  77
  78 &k3_pds {
  79         u-boot,dm-spl;
  80 };
  81
  82 &k3_clks {
  83         u-boot,dm-spl;
  84 };
  85
  86 &k3_reset {
  87         u-boot,dm-spl;
  88 };
  89
  90 &wkup_pmx0 {
  91         u-boot,dm-spl;
  92
  93         wkup_i2c0_pins_default {
  94                 u-boot,dm-spl;
  95         };
  96 };
  97
  98 &main_pmx0 {
  99         u-boot,dm-spl;
 100         main_uart0_pins_default: main_uart0_pins_default {
 101                 pinctrl-single,pins = <
 102                         AM65X_IOPAD(0x01e4, PIN_INPUT, 0)       /* (AF11) UART0_RXD */
 103                         AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)      /* (AE11) UART0_TXD */
 104                         AM65X_IOPAD(0x01ec, PIN_INPUT, 0)       /* (AG11) UART0_CTSn */
 105                         AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)      /* (AD11) UART0_RTSn */
 106                 >;
 107                 u-boot,dm-spl;
 108         };
 109
 110         main_mmc0_pins_default: main_mmc0_pins_default {
 111                 pinctrl-single,pins = <
 112                         AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)      /* (B25) MMC0_CLK */
 113                         AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)        /* (B27) MMC0_CMD */
 114                         AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)        /* (A26) MMC0_DAT0 */
 115                         AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)        /* (E25) MMC0_DAT1 */
 116                         AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)        /* (C26) MMC0_DAT2 */
 117                         AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)        /* (A25) MMC0_DAT3 */
 118                         AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)        /* (E24) MMC0_DAT4 */
 119                         AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)        /* (A24) MMC0_DAT5 */
 120                         AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)        /* (B26) MMC0_DAT6 */
 121                         AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)        /* (D25) MMC0_DAT7 */
 122                         AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0)        /* (A23) MMC0_SDCD */
 123                         AM65X_IOPAD(0x01b0, PIN_INPUT, 0)               /* (C25) MMC0_DS */
 124                 >;
 125                 u-boot,dm-spl;
 126         };
 127
 128         main_mmc1_pins_default: main_mmc1_pins_default {
 129                 pinctrl-single,pins = <
 130                         AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0)      /* (C27) MMC1_CLK */
 131                         AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0)        /* (C28) MMC1_CMD */
 132                         AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0)        /* (D28) MMC1_DAT0 */
 133                         AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0)        /* (E27) MMC1_DAT1 */
 134                         AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0)        /* (D26) MMC1_DAT2 */
 135                         AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0)        /* (D27) MMC1_DAT3 */
 136                         AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0)        /* (B24) MMC1_SDCD */
 137                         AM65X_IOPAD(0x02e0, PIN_INPUT, 0)                       /* (C24) MMC1_SDWP */
 138                 >;
 139                 u-boot,dm-spl;
 140         };
 141
 142         usb0_pins_default: usb0_pins_default {
 143                 pinctrl-single,pins = <
 144                         AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
 145                 >;
 146                 u-boot,dm-spl;
 147         };
 148 };
 149
 150 &main_pmx1 {
 151         u-boot,dm-spl;
 152 };
 153
 154 &wkup_pmx0 {
 155         mcu_cpsw_pins_default: mcu_cpsw_pins_default {
 156                 pinctrl-single,pins = <
 157                         AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
 158                         AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
 159                         AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
 160                         AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
 161                         AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
 162                         AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
 163                         AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
 164                         AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
 165                         AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
 166                         AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
 167                         AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
 168                         AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
 169                 >;
 170         };
 171
 172         mcu_mdio_pins_default: mcu_mdio1_pins_default {
 173                 pinctrl-single,pins = <
 174                         AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
 175                         AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
 176                 >;
 177         };
 178
 179         mcu-fss0-ospi0-pins-default {
 180                 u-boot,dm-spl;
 181         };
 182 };
 183
 184 &main_uart0 {
 185         u-boot,dm-spl;
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&main_uart0_pins_default>;
 188         status = "okay";
 189 };
 190
 191 &sdhci0 {
 192         u-boot,dm-spl;
 193 };
 194
 195 &sdhci1 {
 196         u-boot,dm-spl;
 197         status = "okay";
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&main_mmc1_pins_default>;
 200         sdhci-caps-mask = <0x7 0x0>;
 201         ti,driver-strength-ohm = <50>;
 202 };
 203
 204 &mcu_cpsw {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 207 };
 208
 209 &davinci_mdio {
 210         phy0: ethernet-phy@0 {
 211                 reg = <0>;
 212                 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
 213                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 214                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 215         };
 216 };
 217
 218 &cpsw_port1 {
 219         phy-mode = "rgmii-rxid";
 220         phy-handle = <&phy0>;
 221 };
 222
 223 &mcu_cpsw {
 224         reg = <0x0 0x46000000 0x0 0x200000>,
 225               <0x0 0x40f00200 0x0 0x2>;
 226         reg-names = "cpsw_nuss", "mac_efuse";
 227         /delete-property/ ranges;
 228
 229         cpsw-phy-sel@40f04040 {
 230                 compatible = "ti,am654-cpsw-phy-sel";
 231                 reg= <0x0 0x40f04040 0x0 0x4>;
 232                 reg-names = "gmii-sel";
 233         };
 234 };
 235
 236 &wkup_i2c0 {
 237         u-boot,dm-spl;
 238 };
 239
 240 &usb1 {
 241         dr_mode = "peripheral";
 242 };
 243
 244 &fss {
 245         u-boot,dm-spl;
 246 };
 247
 248 &ospi0 {
 249         u-boot,dm-spl;
 250
 251          flash@0{
 252                 u-boot,dm-spl;
 253         };
 254 };
 255
 256 &chipid {
 257         u-boot,dm-spl;
 258 };
 259
 260 &dwc3_0 {
 261         status = "okay";
 262         u-boot,dm-spl;
 263 };
 264
 265 &usb0_phy {
 266         status = "okay";
 267         u-boot,dm-spl;
 268 };
 269
 270 &usb0 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&usb0_pins_default>;
 273         dr_mode = "peripheral";
 274         u-boot,dm-spl;
 275 };
 276
 277 &scm_conf {
 278         u-boot,dm-spl;
 279 };