1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for AM6 SoC Family
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/k3.h>
12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 model = "Texas Instruments K3 AM654 SoC";
16 compatible = "ti,am654";
17 interrupt-parent = <&gic500>;
22 serial0 = &wkup_uart0;
24 serial2 = &main_uart0;
25 serial3 = &main_uart1;
26 serial4 = &main_uart2;
39 compatible = "linaro,optee-tz";
44 compatible = "arm,psci-1.0";
49 a53_timer0: timer-cl0-cpu0 {
50 compatible = "arm,armv8-timer";
51 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
52 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
53 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
54 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
58 compatible = "arm,armv8-pmuv3";
59 /* Recommendation from GIC500 TRM Table A.3 */
60 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
63 cbass_main: interconnect@100000 {
64 compatible = "simple-bus";
67 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
68 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
69 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
70 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
71 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
72 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
74 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
75 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
76 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
77 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
78 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
79 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
80 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
81 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
82 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
84 cbass_mcu: interconnect@28380000 {
85 compatible = "simple-bus";
88 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
89 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
90 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
91 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
92 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
93 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
94 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
95 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
96 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
98 cbass_wakeup: interconnect@42040000 {
99 compatible = "simple-bus";
100 #address-cells = <1>;
102 /* WKUP Basic peripherals */
103 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
109 /* Now include the peripherals for each bus segments */
110 #include "k3-am65-main.dtsi"
111 #include "k3-am65-mcu.dtsi"
112 #include "k3-am65-wakeup.dtsi"