arch/arm/dts/k3-am65-mcu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 &cbass_mcu {
   9         mcu_conf: scm_conf@40f00000 {
  10                 compatible = "syscon", "simple-mfd";
  11                 reg = <0x0 0x40f00000 0x0 0x20000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x0 0x40f00000 0x20000>;
  15
  16                 phy_gmii_sel: phy@4040 {
  17                         compatible = "ti,am654-phy-gmii-sel";
  18                         reg = <0x4040 0x4>;
  19                         #phy-cells = <1>;
  20                 };
  21         };
  22
  23         mcu_uart0: serial@40a00000 {
  24                 compatible = "ti,am654-uart";
  25                         reg = <0x00 0x40a00000 0x00 0x100>;
  26                         reg-shift = <2>;
  27                         reg-io-width = <4>;
  28                         interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
  29                         clock-frequency = <96000000>;
  30                         current-speed = <115200>;
  31         };
  32
  33         mcu_i2c0: i2c@40b00000 {
  34                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
  35                 reg = <0x0 0x40b00000 0x0 0x100>;
  36                 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 clock-names = "fck";
  40                 clocks = <&k3_clks 114 1>;
  41                 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
  42         };
  43
  44         mcu_r5fss0: r5fss@41000000 {
  45                 compatible = "ti,am654-r5fss";
  46                 lockstep-mode = <0>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 ranges = <0x41000000 0x00 0x41000000 0x20000>,
  50                          <0x41400000 0x00 0x41400000 0x20000>;
  51                 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
  52
  53                 mcu_r5fss0_core0: r5f@41000000 {
  54                         compatible = "ti,am654-r5f";
  55                         reg = <0x41000000 0x00008000>,
  56                               <0x41010000 0x00008000>;
  57                         reg-names = "atcm", "btcm";
  58                         ti,sci = <&dmsc>;
  59                         ti,sci-dev-id = <159>;
  60                         ti,sci-proc-ids = <0x01 0xFF>;
  61                         resets = <&k3_reset 159 1>;
  62                         atcm-enable = <1>;
  63                         btcm-enable = <1>;
  64                         loczrama = <1>;
  65                 };
  66
  67                 mcu_r5fss0_core1: r5f@41400000 {
  68                         compatible = "ti,am654-r5f";
  69                         reg = <0x41400000 0x00008000>,
  70                               <0x41410000 0x00008000>;
  71                         reg-names = "atcm", "btcm";
  72                         ti,sci = <&dmsc>;
  73                         ti,sci-dev-id = <245>;
  74                         ti,sci-proc-ids = <0x02 0xFF>;
  75                         resets = <&k3_reset 245 1>;
  76                         atcm-enable = <1>;
  77                         btcm-enable = <1>;
  78                         loczrama = <1>;
  79                 };
  80         };
  81
  82         fss: fss@47000000 {
  83                 compatible = "simple-bus";
  84                 #address-cells = <2>;
  85                 #size-cells = <2>;
  86                 ranges;
  87
  88                 ospi0: spi@47040000 {
  89                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
  90                         reg = <0x0 0x47040000 0x0 0x100>,
  91                                 <0x5 0x00000000 0x1 0x0000000>;
  92                         interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
  93                         cdns,fifo-depth = <256>;
  94                         cdns,fifo-width = <4>;
  95                         cdns,trigger-address = <0x0>;
  96                         clocks = <&k3_clks 248 0>;
  97                         assigned-clocks = <&k3_clks 248 0>;
  98                         assigned-clock-parents = <&k3_clks 248 2>;
  99                         assigned-clock-rates = <166666666>;
 100                         power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103                 };
 104
 105                 ospi1: spi@47050000 {
 106                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 107                         reg = <0x0 0x47050000 0x0 0x100>,
 108                                 <0x7 0x00000000 0x1 0x00000000>;
 109                         interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
 110                         cdns,fifo-depth = <256>;
 111                         cdns,fifo-width = <4>;
 112                         cdns,trigger-address = <0x0>;
 113                         clocks = <&k3_clks 249 6>;
 114                         power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                 };
 118         };
 119
 120         mcu_navss {
 121                 compatible = "simple-mfd";
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 ranges;
 125                 dma-coherent;
 126                 dma-ranges;
 127
 128                 ti,sci-dev-id = <119>;
 129
 130                 mcu_ringacc: ringacc@2b800000 {
 131                         compatible = "ti,am654-navss-ringacc";
 132                         reg =   <0x0 0x2b800000 0x0 0x400000>,
 133                                 <0x0 0x2b000000 0x0 0x400000>,
 134                                 <0x0 0x28590000 0x0 0x100>,
 135                                 <0x0 0x2a500000 0x0 0x40000>;
 136                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 137                         ti,num-rings = <286>;
 138                         ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
 139                         ti,dma-ring-reset-quirk;
 140                         ti,sci = <&dmsc>;
 141                         ti,sci-dev-id = <195>;
 142                 };
 143
 144                 mcu_udmap: dma-controller@285c0000 {
 145                         compatible = "ti,am654-navss-mcu-udmap";
 146                         reg =   <0x0 0x285c0000 0x0 0x100>,
 147                                 <0x0 0x2a800000 0x0 0x40000>,
 148                                 <0x0 0x2aa00000 0x0 0x40000>;
 149                         reg-names = "gcfg", "rchanrt", "tchanrt";
 150                         #dma-cells = <1>;
 151
 152                         ti,sci = <&dmsc>;
 153                         ti,sci-dev-id = <194>;
 154                         ti,ringacc = <&mcu_ringacc>;
 155
 156                         ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
 157                                                 <0x2>; /* TX_CHAN */
 158                         ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
 159                                                 <0x4>; /* RX_CHAN */
 160                         ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
 161                 };
 162         };
 163
 164         mcu_cpsw: ethernet@46000000 {
 165                 compatible = "ti,am654-cpsw-nuss";
 166                 #address-cells = <2>;
 167                 #size-cells = <2>;
 168                 reg = <0x0 0x46000000 0x0 0x200000>;
 169                 reg-names = "cpsw_nuss";
 170                 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 171                 dma-coherent;
 172                 clocks = <&k3_clks 5 10>;
 173                 clock-names = "fck";
 174                 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 175
 176                 dmas = <&mcu_udmap 0xf000>,
 177                        <&mcu_udmap 0xf001>,
 178                        <&mcu_udmap 0xf002>,
 179                        <&mcu_udmap 0xf003>,
 180                        <&mcu_udmap 0xf004>,
 181                        <&mcu_udmap 0xf005>,
 182                        <&mcu_udmap 0xf006>,
 183                        <&mcu_udmap 0xf007>,
 184                        <&mcu_udmap 0x7000>;
 185                 dma-names = "tx0", "tx1", "tx2", "tx3",
 186                             "tx4", "tx5", "tx6", "tx7",
 187                             "rx";
 188
 189                 ethernet-ports {
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192
 193                         cpsw_port1: port@1 {
 194                                 reg = <1>;
 195                                 ti,mac-only;
 196                                 label = "port1";
 197                                 ti,syscon-efuse = <&mcu_conf 0x200>;
 198                                 phys = <&phy_gmii_sel 1>;
 199                         };
 200                 };
 201
 202                 davinci_mdio: mdio@f00 {
 203                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 204                         reg = <0x0 0xf00 0x0 0x100>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         clocks = <&k3_clks 5 10>;
 208                         clock-names = "fck";
 209                         bus_freq = <1000000>;
 210                 };
 211
 212                 cpts@3d000 {
 213                         compatible = "ti,am65-cpts";
 214                         reg = <0x0 0x3d000 0x0 0x400>;
 215                         clocks = <&mcu_cpsw_cpts_mux>;
 216                         clock-names = "cpts";
 217                         interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
 218                         interrupt-names = "cpts";
 219                         ti,cpts-ext-ts-inputs = <4>;
 220                         ti,cpts-periodic-outputs = <2>;
 221
 222                         mcu_cpsw_cpts_mux: refclk-mux {
 223                                 #clock-cells = <0>;
 224                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 225                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 226                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 227                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 228                                 assigned-clocks = <&mcu_cpsw_cpts_mux>;
 229                                 assigned-clock-parents = <&k3_clks 118 5>;
 230                         };
 231                 };
 232         };
 233
 234         mcu_rti1: rti@40610000 {
 235                 compatible = "ti,j7-rti-wdt";
 236                 reg = <0x0 0x40610000 0x0 0x100>;
 237                 clocks = <&k3_clks 135 0>;
 238                 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
 239                 assigned-clocks = <&k3_clks 135 0>;
 240                 assigned-clock-parents = <&k3_clks 135 4>;
 241         };
 242 };