arch/arm/dts/k3-am65-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7 #include <dt-bindings/phy/phy-am654-serdes.h>
   8
   9 &cbass_main {
  10         msmc_ram: sram@70000000 {
  11                 compatible = "mmio-sram";
  12                 reg = <0x0 0x70000000 0x0 0x200000>;
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x0 0x0 0x70000000 0x200000>;
  16
  17                 atf-sram@0 {
  18                         reg = <0x0 0x20000>;
  19                 };
  20
  21                 sysfw-sram@f0000 {
  22                         reg = <0xf0000 0x10000>;
  23                 };
  24
  25                 l3cache-sram@100000 {
  26                         reg = <0x100000 0x100000>;
  27                 };
  28         };
  29
  30         gic500: interrupt-controller@1800000 {
  31                 compatible = "arm,gic-v3";
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35                 #interrupt-cells = <3>;
  36                 interrupt-controller;
  37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
  39                 /*
  40                  * vcpumntirq:
  41                  * virtual CPU interface maintenance interrupt
  42                  */
  43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  44
  45                 gic_its: msi-controller@1820000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x00 0x01820000 0x00 0x10000>;
  48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };
  52         };
  53
  54         serdes0: serdes@900000 {
  55                 compatible = "ti,phy-am654-serdes";
  56                 reg = <0x0 0x900000 0x0 0x2000>;
  57                 reg-names = "serdes";
  58                 #phy-cells = <2>;
  59                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
  60                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
  61                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
  62                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
  63                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
  64                 ti,serdes-clk = <&serdes0_clk>;
  65                 #clock-cells = <1>;
  66                 mux-controls = <&serdes_mux 0>;
  67         };
  68
  69         serdes1: serdes@910000 {
  70                 compatible = "ti,phy-am654-serdes";
  71                 reg = <0x0 0x910000 0x0 0x2000>;
  72                 reg-names = "serdes";
  73                 #phy-cells = <2>;
  74                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
  75                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
  76                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
  77                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
  78                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
  79                 ti,serdes-clk = <&serdes1_clk>;
  80                 #clock-cells = <1>;
  81                 mux-controls = <&serdes_mux 1>;
  82         };
  83
  84         main_uart0: serial@2800000 {
  85                 compatible = "ti,am654-uart";
  86                 reg = <0x00 0x02800000 0x00 0x100>;
  87                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  88                 clock-frequency = <48000000>;
  89                 current-speed = <115200>;
  90                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  91         };
  92
  93         main_uart1: serial@2810000 {
  94                 compatible = "ti,am654-uart";
  95                 reg = <0x00 0x02810000 0x00 0x100>;
  96                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  97                 clock-frequency = <48000000>;
  98                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
  99         };
 100
 101         main_uart2: serial@2820000 {
 102                 compatible = "ti,am654-uart";
 103                 reg = <0x00 0x02820000 0x00 0x100>;
 104                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 105                 clock-frequency = <48000000>;
 106                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 107         };
 108
 109         crypto: crypto@4e00000 {
 110                 compatible = "ti,am654-sa2ul";
 111                 reg = <0x0 0x4e00000 0x0 0x1200>;
 112                 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
 113                 #address-cells = <2>;
 114                 #size-cells = <2>;
 115                 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
 116
 117                 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
 118                                 <&main_udmap 0x4001>;
 119                 dma-names = "tx", "rx1", "rx2";
 120                 dma-coherent;
 121
 122                 rng: rng@4e10000 {
 123                         compatible = "inside-secure,safexcel-eip76";
 124                         reg = <0x0 0x4e10000 0x0 0x7d>;
 125                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&k3_clks 136 1>;
 127                 };
 128         };
 129
 130         main_pmx0: pinctrl@11c000 {
 131                 compatible = "pinctrl-single";
 132                 reg = <0x0 0x11c000 0x0 0x2e4>;
 133                 #pinctrl-cells = <1>;
 134                 pinctrl-single,register-width = <32>;
 135                 pinctrl-single,function-mask = <0xffffffff>;
 136         };
 137
 138         main_pmx1: pinctrl@11c2e8 {
 139                 compatible = "pinctrl-single";
 140                 reg = <0x0 0x11c2e8 0x0 0x24>;
 141                 #pinctrl-cells = <1>;
 142                 pinctrl-single,register-width = <32>;
 143                 pinctrl-single,function-mask = <0xffffffff>;
 144         };
 145
 146         main_i2c0: i2c@2000000 {
 147                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 148                 reg = <0x0 0x2000000 0x0 0x100>;
 149                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 clock-names = "fck";
 153                 clocks = <&k3_clks 110 1>;
 154                 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
 155         };
 156
 157         main_i2c1: i2c@2010000 {
 158                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 159                 reg = <0x0 0x2010000 0x0 0x100>;
 160                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 clock-names = "fck";
 164                 clocks = <&k3_clks 111 1>;
 165                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 166         };
 167
 168         main_i2c2: i2c@2020000 {
 169                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 170                 reg = <0x0 0x2020000 0x0 0x100>;
 171                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 clock-names = "fck";
 175                 clocks = <&k3_clks 112 1>;
 176                 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
 177         };
 178
 179         main_i2c3: i2c@2030000 {
 180                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
 181                 reg = <0x0 0x2030000 0x0 0x100>;
 182                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 clock-names = "fck";
 186                 clocks = <&k3_clks 113 1>;
 187                 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
 188         };
 189
 190         ecap0: pwm@3100000 {
 191                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
 192                 #pwm-cells = <3>;
 193                 reg = <0x0 0x03100000 0x0 0x60>;
 194                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 195                 clocks = <&k3_clks 39 0>;
 196                 clock-names = "fck";
 197         };
 198
 199         main_spi0: spi@2100000 {
 200                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 201                 reg = <0x0 0x2100000 0x0 0x400>;
 202                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&k3_clks 137 1>;
 204                 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
 208                 dma-names = "tx0", "rx0";
 209         };
 210
 211         main_spi1: spi@2110000 {
 212                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 213                 reg = <0x0 0x2110000 0x0 0x400>;
 214                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&k3_clks 138 1>;
 216                 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 assigned-clocks = <&k3_clks 137 1>;
 220                 assigned-clock-rates = <48000000>;
 221         };
 222
 223         main_spi2: spi@2120000 {
 224                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 225                 reg = <0x0 0x2120000 0x0 0x400>;
 226                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&k3_clks 139 1>;
 228                 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231         };
 232
 233         main_spi3: spi@2130000 {
 234                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 235                 reg = <0x0 0x2130000 0x0 0x400>;
 236                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&k3_clks 140 1>;
 238                 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241         };
 242
 243         main_spi4: spi@2140000 {
 244                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 245                 reg = <0x0 0x2140000 0x0 0x400>;
 246                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&k3_clks 141 1>;
 248                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251         };
 252
 253         sdhci0: mmc@4f80000 {
 254                 compatible = "ti,am654-sdhci-5.1";
 255                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 256                 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
 257                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 258                 clock-names = "clk_ahb", "clk_xin";
 259                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 260                 mmc-ddr-1_8v;
 261                 mmc-hs200-1_8v;
 262                 ti,otap-del-sel-legacy = <0x0>;
 263                 ti,otap-del-sel-mmc-hs = <0x0>;
 264                 ti,otap-del-sel-sd-hs = <0x0>;
 265                 ti,otap-del-sel-sdr12 = <0x0>;
 266                 ti,otap-del-sel-sdr25 = <0x0>;
 267                 ti,otap-del-sel-sdr50 = <0x8>;
 268                 ti,otap-del-sel-sdr104 = <0x7>;
 269                 ti,otap-del-sel-ddr50 = <0x5>;
 270                 ti,otap-del-sel-ddr52 = <0x5>;
 271                 ti,otap-del-sel-hs200 = <0x5>;
 272                 ti,otap-del-sel-hs400 = <0x0>;
 273                 ti,trm-icp = <0x8>;
 274                 dma-coherent;
 275         };
 276
 277         sdhci1: mmc@4fa0000 {
 278                 compatible = "ti,am654-sdhci-5.1";
 279                 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
 280                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
 281                 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
 282                 clock-names = "clk_ahb", "clk_xin";
 283                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 284                 ti,otap-del-sel-legacy = <0x0>;
 285                 ti,otap-del-sel-mmc-hs = <0x0>;
 286                 ti,otap-del-sel-sd-hs = <0x0>;
 287                 ti,otap-del-sel-sdr12 = <0x0>;
 288                 ti,otap-del-sel-sdr25 = <0x0>;
 289                 ti,otap-del-sel-sdr50 = <0x8>;
 290                 ti,otap-del-sel-sdr104 = <0x7>;
 291                 ti,otap-del-sel-ddr50 = <0x4>;
 292                 ti,otap-del-sel-ddr52 = <0x4>;
 293                 ti,otap-del-sel-hs200 = <0x7>;
 294                 ti,clkbuf-sel = <0x7>;
 295                 ti,otap-del-sel = <0x2>;
 296                 ti,trm-icp = <0x8>;
 297                 dma-coherent;
 298         };
 299
 300         scm_conf: scm-conf@100000 {
 301                 compatible = "syscon", "simple-mfd";
 302                 reg = <0 0x00100000 0 0x1c000>;
 303                 #address-cells = <1>;
 304                 #size-cells = <1>;
 305                 ranges = <0x0 0x0 0x00100000 0x1c000>;
 306
 307                 pcie0_mode: pcie-mode@4060 {
 308                         compatible = "syscon";
 309                         reg = <0x00004060 0x4>;
 310                 };
 311
 312                 pcie1_mode: pcie-mode@4070 {
 313                         compatible = "syscon";
 314                         reg = <0x00004070 0x4>;
 315                 };
 316
 317                 pcie_devid: pcie-devid@210 {
 318                         compatible = "syscon";
 319                         reg = <0x00000210 0x4>;
 320                 };
 321
 322                 serdes0_clk: clock@4080 {
 323                         compatible = "syscon";
 324                         reg = <0x00004080 0x4>;
 325                 };
 326
 327                 serdes1_clk: clock@4090 {
 328                         compatible = "syscon";
 329                         reg = <0x00004090 0x4>;
 330                 };
 331
 332                 serdes_mux: mux-controller {
 333                         compatible = "mmio-mux";
 334                         #mux-control-cells = <1>;
 335                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
 336                                         <0x4090 0x3>; /* SERDES1 lane select */
 337                 };
 338
 339                 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
 340                         compatible = "syscon";
 341                         reg = <0x0000041e0 0x14>;
 342                 };
 343
 344                 ehrpwm_tbclk: clock@4140 {
 345                         compatible = "ti,am654-ehrpwm-tbclk", "syscon";
 346                         reg = <0x4140 0x18>;
 347                         #clock-cells = <1>;
 348                 };
 349         };
 350
 351         dwc3_0: dwc3@4000000 {
 352                 compatible = "ti,am654-dwc3";
 353                 reg = <0x0 0x4000000 0x0 0x4000>;
 354                 #address-cells = <1>;
 355                 #size-cells = <1>;
 356                 ranges = <0x0 0x0 0x4000000 0x20000>;
 357                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 358                 dma-coherent;
 359                 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
 360                 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 361                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
 362                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 363                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
 364
 365                 usb0: usb@10000 {
 366                         compatible = "snps,dwc3";
 367                         reg = <0x10000 0x10000>;
 368                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 371                         interrupt-names = "peripheral",
 372                                           "host",
 373                                           "otg";
 374                         maximum-speed = "high-speed";
 375                         dr_mode = "otg";
 376                         phys = <&usb0_phy>;
 377                         phy-names = "usb2-phy";
 378                         snps,dis_u3_susphy_quirk;
 379                 };
 380         };
 381
 382         usb0_phy: phy@4100000 {
 383                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 384                 reg = <0x0 0x4100000 0x0 0x54>;
 385                 syscon-phy-power = <&scm_conf 0x4000>;
 386                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
 387                 clock-names = "wkupclk", "refclk";
 388                 #phy-cells = <0>;
 389         };
 390
 391         dwc3_1: dwc3@4020000 {
 392                 compatible = "ti,am654-dwc3";
 393                 reg = <0x0 0x4020000 0x0 0x4000>;
 394                 #address-cells = <1>;
 395                 #size-cells = <1>;
 396                 ranges = <0x0 0x0 0x4020000 0x20000>;
 397                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 398                 dma-coherent;
 399                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 400                 clocks = <&k3_clks 152 2>;
 401                 assigned-clocks = <&k3_clks 152 2>;
 402                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
 403
 404                 usb1: usb@10000 {
 405                         compatible = "snps,dwc3";
 406                         reg = <0x10000 0x10000>;
 407                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 410                         interrupt-names = "peripheral",
 411                                           "host",
 412                                           "otg";
 413                         maximum-speed = "high-speed";
 414                         dr_mode = "otg";
 415                         phys = <&usb1_phy>;
 416                         phy-names = "usb2-phy";
 417                 };
 418         };
 419
 420         usb1_phy: phy@4110000 {
 421                 compatible = "ti,am654-usb2", "ti,omap-usb2";
 422                 reg = <0x0 0x4110000 0x0 0x54>;
 423                 syscon-phy-power = <&scm_conf 0x4020>;
 424                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
 425                 clock-names = "wkupclk", "refclk";
 426                 #phy-cells = <0>;
 427         };
 428
 429         intr_main_gpio: interrupt-controller@a00000 {
 430                 compatible = "ti,sci-intr";
 431                 reg = <0x0 0x00a00000 0x0 0x400>;
 432                 ti,intr-trigger-type = <1>;
 433                 interrupt-controller;
 434                 interrupt-parent = <&gic500>;
 435                 #interrupt-cells = <1>;
 436                 ti,sci = <&dmsc>;
 437                 ti,sci-dev-id = <100>;
 438                 ti,interrupt-ranges = <0 392 32>;
 439         };
 440
 441         main_navss: bus@30800000 {
 442                 compatible = "simple-mfd";
 443                 #address-cells = <2>;
 444                 #size-cells = <2>;
 445                 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
 446                 dma-coherent;
 447                 dma-ranges;
 448
 449                 ti,sci-dev-id = <118>;
 450
 451                 intr_main_navss: interrupt-controller@310e0000 {
 452                         compatible = "ti,sci-intr";
 453                         reg = <0x0 0x310e0000 0x0 0x2000>;
 454                         ti,intr-trigger-type = <4>;
 455                         interrupt-controller;
 456                         interrupt-parent = <&gic500>;
 457                         #interrupt-cells = <1>;
 458                         ti,sci = <&dmsc>;
 459                         ti,sci-dev-id = <182>;
 460                         ti,interrupt-ranges = <0 64 64>,
 461                                               <64 448 64>;
 462                 };
 463
 464                 inta_main_udmass: interrupt-controller@33d00000 {
 465                         compatible = "ti,sci-inta";
 466                         reg = <0x0 0x33d00000 0x0 0x100000>;
 467                         interrupt-controller;
 468                         interrupt-parent = <&intr_main_navss>;
 469                         msi-controller;
 470                         #interrupt-cells = <0>;
 471                         ti,sci = <&dmsc>;
 472                         ti,sci-dev-id = <179>;
 473                         ti,interrupt-ranges = <0 0 256>;
 474                 };
 475
 476                 secure_proxy_main: mailbox@32c00000 {
 477                         compatible = "ti,am654-secure-proxy";
 478                         #mbox-cells = <1>;
 479                         reg-names = "target_data", "rt", "scfg";
 480                         reg = <0x00 0x32c00000 0x00 0x100000>,
 481                               <0x00 0x32400000 0x00 0x100000>,
 482                               <0x00 0x32800000 0x00 0x100000>;
 483                         interrupt-names = "rx_011";
 484                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 485                 };
 486
 487                 hwspinlock: spinlock@30e00000 {
 488                         compatible = "ti,am654-hwspinlock";
 489                         reg = <0x00 0x30e00000 0x00 0x1000>;
 490                         #hwlock-cells = <1>;
 491                 };
 492
 493                 mailbox0_cluster0: mailbox@31f80000 {
 494                         compatible = "ti,am654-mailbox";
 495                         reg = <0x00 0x31f80000 0x00 0x200>;
 496                         #mbox-cells = <1>;
 497                         ti,mbox-num-users = <4>;
 498                         ti,mbox-num-fifos = <16>;
 499                         interrupt-parent = <&intr_main_navss>;
 500                 };
 501
 502                 mailbox0_cluster1: mailbox@31f81000 {
 503                         compatible = "ti,am654-mailbox";
 504                         reg = <0x00 0x31f81000 0x00 0x200>;
 505                         #mbox-cells = <1>;
 506                         ti,mbox-num-users = <4>;
 507                         ti,mbox-num-fifos = <16>;
 508                         interrupt-parent = <&intr_main_navss>;
 509                 };
 510
 511                 mailbox0_cluster2: mailbox@31f82000 {
 512                         compatible = "ti,am654-mailbox";
 513                         reg = <0x00 0x31f82000 0x00 0x200>;
 514                         #mbox-cells = <1>;
 515                         ti,mbox-num-users = <4>;
 516                         ti,mbox-num-fifos = <16>;
 517                         interrupt-parent = <&intr_main_navss>;
 518                 };
 519
 520                 mailbox0_cluster3: mailbox@31f83000 {
 521                         compatible = "ti,am654-mailbox";
 522                         reg = <0x00 0x31f83000 0x00 0x200>;
 523                         #mbox-cells = <1>;
 524                         ti,mbox-num-users = <4>;
 525                         ti,mbox-num-fifos = <16>;
 526                         interrupt-parent = <&intr_main_navss>;
 527                 };
 528
 529                 mailbox0_cluster4: mailbox@31f84000 {
 530                         compatible = "ti,am654-mailbox";
 531                         reg = <0x00 0x31f84000 0x00 0x200>;
 532                         #mbox-cells = <1>;
 533                         ti,mbox-num-users = <4>;
 534                         ti,mbox-num-fifos = <16>;
 535                         interrupt-parent = <&intr_main_navss>;
 536                 };
 537
 538                 mailbox0_cluster5: mailbox@31f85000 {
 539                         compatible = "ti,am654-mailbox";
 540                         reg = <0x00 0x31f85000 0x00 0x200>;
 541                         #mbox-cells = <1>;
 542                         ti,mbox-num-users = <4>;
 543                         ti,mbox-num-fifos = <16>;
 544                         interrupt-parent = <&intr_main_navss>;
 545                 };
 546
 547                 mailbox0_cluster6: mailbox@31f86000 {
 548                         compatible = "ti,am654-mailbox";
 549                         reg = <0x00 0x31f86000 0x00 0x200>;
 550                         #mbox-cells = <1>;
 551                         ti,mbox-num-users = <4>;
 552                         ti,mbox-num-fifos = <16>;
 553                         interrupt-parent = <&intr_main_navss>;
 554                 };
 555
 556                 mailbox0_cluster7: mailbox@31f87000 {
 557                         compatible = "ti,am654-mailbox";
 558                         reg = <0x00 0x31f87000 0x00 0x200>;
 559                         #mbox-cells = <1>;
 560                         ti,mbox-num-users = <4>;
 561                         ti,mbox-num-fifos = <16>;
 562                         interrupt-parent = <&intr_main_navss>;
 563                 };
 564
 565                 mailbox0_cluster8: mailbox@31f88000 {
 566                         compatible = "ti,am654-mailbox";
 567                         reg = <0x00 0x31f88000 0x00 0x200>;
 568                         #mbox-cells = <1>;
 569                         ti,mbox-num-users = <4>;
 570                         ti,mbox-num-fifos = <16>;
 571                         interrupt-parent = <&intr_main_navss>;
 572                 };
 573
 574                 mailbox0_cluster9: mailbox@31f89000 {
 575                         compatible = "ti,am654-mailbox";
 576                         reg = <0x00 0x31f89000 0x00 0x200>;
 577                         #mbox-cells = <1>;
 578                         ti,mbox-num-users = <4>;
 579                         ti,mbox-num-fifos = <16>;
 580                         interrupt-parent = <&intr_main_navss>;
 581                 };
 582
 583                 mailbox0_cluster10: mailbox@31f8a000 {
 584                         compatible = "ti,am654-mailbox";
 585                         reg = <0x00 0x31f8a000 0x00 0x200>;
 586                         #mbox-cells = <1>;
 587                         ti,mbox-num-users = <4>;
 588                         ti,mbox-num-fifos = <16>;
 589                         interrupt-parent = <&intr_main_navss>;
 590                 };
 591
 592                 mailbox0_cluster11: mailbox@31f8b000 {
 593                         compatible = "ti,am654-mailbox";
 594                         reg = <0x00 0x31f8b000 0x00 0x200>;
 595                         #mbox-cells = <1>;
 596                         ti,mbox-num-users = <4>;
 597                         ti,mbox-num-fifos = <16>;
 598                         interrupt-parent = <&intr_main_navss>;
 599                 };
 600
 601                 ringacc: ringacc@3c000000 {
 602                         compatible = "ti,am654-navss-ringacc";
 603                         reg =   <0x0 0x3c000000 0x0 0x400000>,
 604                                 <0x0 0x38000000 0x0 0x400000>,
 605                                 <0x0 0x31120000 0x0 0x100>,
 606                                 <0x0 0x33000000 0x0 0x40000>;
 607                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
 608                         ti,num-rings = <818>;
 609                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 610                         ti,sci = <&dmsc>;
 611                         ti,sci-dev-id = <187>;
 612                         msi-parent = <&inta_main_udmass>;
 613                 };
 614
 615                 main_udmap: dma-controller@31150000 {
 616                         compatible = "ti,am654-navss-main-udmap";
 617                         reg =   <0x0 0x31150000 0x0 0x100>,
 618                                 <0x0 0x34000000 0x0 0x100000>,
 619                                 <0x0 0x35000000 0x0 0x100000>;
 620                         reg-names = "gcfg", "rchanrt", "tchanrt";
 621                         msi-parent = <&inta_main_udmass>;
 622                         #dma-cells = <1>;
 623
 624                         ti,sci = <&dmsc>;
 625                         ti,sci-dev-id = <188>;
 626                         ti,ringacc = <&ringacc>;
 627
 628                         ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
 629                                                 <0xd>; /* TX_CHAN */
 630                         ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
 631                                                 <0xa>; /* RX_CHAN */
 632                         ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
 633                 };
 634
 635                 cpts@310d0000 {
 636                         compatible = "ti,am65-cpts";
 637                         reg = <0x0 0x310d0000 0x0 0x400>;
 638                         reg-names = "cpts";
 639                         clocks = <&main_cpts_mux>;
 640                         clock-names = "cpts";
 641                         interrupts-extended = <&intr_main_navss 391>;
 642                         interrupt-names = "cpts";
 643                         ti,cpts-periodic-outputs = <6>;
 644                         ti,cpts-ext-ts-inputs = <8>;
 645
 646                         main_cpts_mux: refclk-mux {
 647                                 #clock-cells = <0>;
 648                                 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
 649                                         <&k3_clks 118 6>, <&k3_clks 118 3>,
 650                                         <&k3_clks 118 8>, <&k3_clks 118 14>,
 651                                         <&k3_clks 120 3>, <&k3_clks 121 3>;
 652                                 assigned-clocks = <&main_cpts_mux>;
 653                                 assigned-clock-parents = <&k3_clks 118 5>;
 654                         };
 655                 };
 656         };
 657
 658         main_gpio0: gpio@600000 {
 659                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 660                 reg = <0x0 0x600000 0x0 0x100>;
 661                 gpio-controller;
 662                 #gpio-cells = <2>;
 663                 interrupt-parent = <&intr_main_gpio>;
 664                 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
 665                 interrupt-controller;
 666                 #interrupt-cells = <2>;
 667                 ti,ngpio = <96>;
 668                 ti,davinci-gpio-unbanked = <0>;
 669                 clocks = <&k3_clks 57 0>;
 670                 clock-names = "gpio";
 671         };
 672
 673         main_gpio1: gpio@601000 {
 674                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
 675                 reg = <0x0 0x601000 0x0 0x100>;
 676                 gpio-controller;
 677                 #gpio-cells = <2>;
 678                 interrupt-parent = <&intr_main_gpio>;
 679                 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
 680                 interrupt-controller;
 681                 #interrupt-cells = <2>;
 682                 ti,ngpio = <90>;
 683                 ti,davinci-gpio-unbanked = <0>;
 684                 clocks = <&k3_clks 58 0>;
 685                 clock-names = "gpio";
 686         };
 687
 688         pcie0_rc: pcie@5500000 {
 689                 compatible = "ti,am654-pcie-rc";
 690                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
 691                 reg-names = "app", "dbics", "config", "atu";
 692                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 693                 #address-cells = <3>;
 694                 #size-cells = <2>;
 695                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
 696                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
 697                 ti,syscon-pcie-id = <&pcie_devid>;
 698                 ti,syscon-pcie-mode = <&pcie0_mode>;
 699                 bus-range = <0x0 0xff>;
 700                 num-viewport = <16>;
 701                 max-link-speed = <2>;
 702                 dma-coherent;
 703                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 704                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 705                 device_type = "pci";
 706         };
 707
 708         pcie0_ep: pcie-ep@5500000 {
 709                 compatible = "ti,am654-pcie-ep";
 710                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
 711                 reg-names = "app", "dbics", "addr_space", "atu";
 712                 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
 713                 ti,syscon-pcie-mode = <&pcie0_mode>;
 714                 num-ib-windows = <16>;
 715                 num-ob-windows = <16>;
 716                 max-link-speed = <2>;
 717                 dma-coherent;
 718                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
 719         };
 720
 721         pcie1_rc: pcie@5600000 {
 722                 compatible = "ti,am654-pcie-rc";
 723                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
 724                 reg-names = "app", "dbics", "config", "atu";
 725                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 726                 #address-cells = <3>;
 727                 #size-cells = <2>;
 728                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
 729                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
 730                 ti,syscon-pcie-id = <&pcie_devid>;
 731                 ti,syscon-pcie-mode = <&pcie1_mode>;
 732                 bus-range = <0x0 0xff>;
 733                 num-viewport = <16>;
 734                 max-link-speed = <2>;
 735                 dma-coherent;
 736                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 737                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
 738                 device_type = "pci";
 739         };
 740
 741         pcie1_ep: pcie-ep@5600000 {
 742                 compatible = "ti,am654-pcie-ep";
 743                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
 744                 reg-names = "app", "dbics", "addr_space", "atu";
 745                 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
 746                 ti,syscon-pcie-mode = <&pcie1_mode>;
 747                 num-ib-windows = <16>;
 748                 num-ob-windows = <16>;
 749                 max-link-speed = <2>;
 750                 dma-coherent;
 751                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
 752         };
 753
 754         mcasp0: mcasp@2b00000 {
 755                 compatible = "ti,am33xx-mcasp-audio";
 756                 reg = <0x0 0x02b00000 0x0 0x2000>,
 757                         <0x0 0x02b08000 0x0 0x1000>;
 758                 reg-names = "mpu","dat";
 759                 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 760                                 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 761                 interrupt-names = "tx", "rx";
 762
 763                 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
 764                 dma-names = "tx", "rx";
 765
 766                 clocks = <&k3_clks 104 0>;
 767                 clock-names = "fck";
 768                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 769         };
 770
 771         mcasp1: mcasp@2b10000 {
 772                 compatible = "ti,am33xx-mcasp-audio";
 773                 reg = <0x0 0x02b10000 0x0 0x2000>,
 774                         <0x0 0x02b18000 0x0 0x1000>;
 775                 reg-names = "mpu","dat";
 776                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 777                                 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 778                 interrupt-names = "tx", "rx";
 779
 780                 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
 781                 dma-names = "tx", "rx";
 782
 783                 clocks = <&k3_clks 105 0>;
 784                 clock-names = "fck";
 785                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 786         };
 787
 788         mcasp2: mcasp@2b20000 {
 789                 compatible = "ti,am33xx-mcasp-audio";
 790                 reg = <0x0 0x02b20000 0x0 0x2000>,
 791                         <0x0 0x02b28000 0x0 0x1000>;
 792                 reg-names = "mpu","dat";
 793                 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 794                                 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 795                 interrupt-names = "tx", "rx";
 796
 797                 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
 798                 dma-names = "tx", "rx";
 799
 800                 clocks = <&k3_clks 106 0>;
 801                 clock-names = "fck";
 802                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
 803         };
 804
 805         cal: cal@6f03000 {
 806                 compatible = "ti,am654-cal";
 807                 reg = <0x0 0x06f03000 0x0 0x400>,
 808                       <0x0 0x06f03800 0x0 0x40>;
 809                 reg-names = "cal_top",
 810                             "cal_rx_core0";
 811                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 812                 ti,camerrx-control = <&scm_conf 0x40c0>;
 813                 clock-names = "fck";
 814                 clocks = <&k3_clks 2 0>;
 815                 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>;
 816
 817                 ports {
 818                         #address-cells = <1>;
 819                         #size-cells = <0>;
 820
 821                         csi2_0: port@0 {
 822                                 reg = <0>;
 823                         };
 824                 };
 825         };
 826
 827         dss: dss@4a00000 {
 828                 compatible = "ti,am65x-dss";
 829                 reg =   <0x0 0x04a00000 0x0 0x1000>, /* common */
 830                         <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
 831                         <0x0 0x04a06000 0x0 0x1000>, /* vid */
 832                         <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
 833                         <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
 834                         <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
 835                         <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
 836                 reg-names = "common", "vidl1", "vid",
 837                         "ovr1", "ovr2", "vp1", "vp2";
 838
 839                 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
 840
 841                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 842
 843                 clocks =        <&k3_clks 67 1>,
 844                                 <&k3_clks 216 1>,
 845                                 <&k3_clks 67 2>;
 846                 clock-names = "fck", "vp1", "vp2";
 847
 848                 /*
 849                  * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
 850                  * DIV1. See "Figure 12-3365. DSS Integration"
 851                  * in AM65x TRM for details.
 852                  */
 853                 assigned-clocks = <&k3_clks 67 2>;
 854                 assigned-clock-parents = <&k3_clks 67 5>;
 855
 856                 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
 857
 858                 dma-coherent;
 859
 860                 dss_ports: ports {
 861                         #address-cells = <1>;
 862                         #size-cells = <0>;
 863                 };
 864         };
 865
 866         ehrpwm0: pwm@3000000 {
 867                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 868                 #pwm-cells = <3>;
 869                 reg = <0x0 0x3000000 0x0 0x100>;
 870                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 871                 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
 872                 clock-names = "tbclk", "fck";
 873         };
 874
 875         ehrpwm1: pwm@3010000 {
 876                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 877                 #pwm-cells = <3>;
 878                 reg = <0x0 0x3010000 0x0 0x100>;
 879                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 880                 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
 881                 clock-names = "tbclk", "fck";
 882         };
 883
 884         ehrpwm2: pwm@3020000 {
 885                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 886                 #pwm-cells = <3>;
 887                 reg = <0x0 0x3020000 0x0 0x100>;
 888                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 889                 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
 890                 clock-names = "tbclk", "fck";
 891         };
 892
 893         ehrpwm3: pwm@3030000 {
 894                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 895                 #pwm-cells = <3>;
 896                 reg = <0x0 0x3030000 0x0 0x100>;
 897                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 898                 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
 899                 clock-names = "tbclk", "fck";
 900         };
 901
 902         ehrpwm4: pwm@3040000 {
 903                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 904                 #pwm-cells = <3>;
 905                 reg = <0x0 0x3040000 0x0 0x100>;
 906                 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
 907                 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
 908                 clock-names = "tbclk", "fck";
 909         };
 910
 911         ehrpwm5: pwm@3050000 {
 912                 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
 913                 #pwm-cells = <3>;
 914                 reg = <0x0 0x3050000 0x0 0x100>;
 915                 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
 916                 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
 917                 clock-names = "tbclk", "fck";
 918         };
 919
 920         icssg0: icssg@b000000 {
 921                 compatible = "ti,am654-icssg";
 922                 reg = <0x00 0xb000000 0x00 0x80000>;
 923                 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
 924                 #address-cells = <1>;
 925                 #size-cells = <1>;
 926                 ranges = <0x0 0x00 0xb000000 0x80000>;
 927
 928                 icssg0_mem: memories@0 {
 929                         reg = <0x0 0x2000>,
 930                               <0x2000 0x2000>,
 931                               <0x10000 0x10000>;
 932                         reg-names = "dram0", "dram1",
 933                                     "shrdram2";
 934                 };
 935
 936                 icssg0_cfg: cfg@26000 {
 937                         compatible = "ti,pruss-cfg", "syscon";
 938                         reg = <0x26000 0x200>;
 939                         #address-cells = <1>;
 940                         #size-cells = <1>;
 941                         ranges = <0x0 0x26000 0x2000>;
 942
 943                         clocks {
 944                                 #address-cells = <1>;
 945                                 #size-cells = <0>;
 946
 947                                 icssg0_coreclk_mux: coreclk-mux@3c {
 948                                         reg = <0x3c>;
 949                                         #clock-cells = <0>;
 950                                         clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
 951                                                  <&k3_clks 62 3>;  /* icssg0_iclk */
 952                                         assigned-clocks = <&icssg0_coreclk_mux>;
 953                                         assigned-clock-parents = <&k3_clks 62 3>;
 954                                 };
 955
 956                                 icssg0_iepclk_mux: iepclk-mux@30 {
 957                                         reg = <0x30>;
 958                                         #clock-cells = <0>;
 959                                         clocks = <&k3_clks 62 10>,      /* icssg0_iep_clk */
 960                                                  <&icssg0_coreclk_mux>; /* core_clk */
 961                                         assigned-clocks = <&icssg0_iepclk_mux>;
 962                                         assigned-clock-parents = <&icssg0_coreclk_mux>;
 963                                 };
 964                         };
 965                 };
 966
 967                 icssg0_mii_rt: mii-rt@32000 {
 968                         compatible = "ti,pruss-mii", "syscon";
 969                         reg = <0x32000 0x100>;
 970                 };
 971
 972                 icssg0_mii_g_rt: mii-g-rt@33000 {
 973                         compatible = "ti,pruss-mii-g", "syscon";
 974                         reg = <0x33000 0x1000>;
 975                 };
 976
 977                 icssg0_intc: interrupt-controller@20000 {
 978                         compatible = "ti,icssg-intc";
 979                         reg = <0x20000 0x2000>;
 980                         interrupt-controller;
 981                         #interrupt-cells = <3>;
 982                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 985                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 986                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 987                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
 990                         interrupt-names = "host_intr0", "host_intr1",
 991                                           "host_intr2", "host_intr3",
 992                                           "host_intr4", "host_intr5",
 993                                           "host_intr6", "host_intr7";
 994                 };
 995
 996                 pru0_0: pru@34000 {
 997                         compatible = "ti,am654-pru";
 998                         reg = <0x34000 0x4000>,
 999                               <0x22000 0x100>,
1000                               <0x22400 0x100>;
1001                         reg-names = "iram", "control", "debug";
1002                         firmware-name = "am65x-pru0_0-fw";
1003                 };
1004
1005                 rtu0_0: rtu@4000 {
1006                         compatible = "ti,am654-rtu";
1007                         reg = <0x4000 0x2000>,
1008                               <0x23000 0x100>,
1009                               <0x23400 0x100>;
1010                         reg-names = "iram", "control", "debug";
1011                         firmware-name = "am65x-rtu0_0-fw";
1012                 };
1013
1014                 tx_pru0_0: txpru@a000 {
1015                         compatible = "ti,am654-tx-pru";
1016                         reg = <0xa000 0x1800>,
1017                               <0x25000 0x100>,
1018                               <0x25400 0x100>;
1019                         reg-names = "iram", "control", "debug";
1020                         firmware-name = "am65x-txpru0_0-fw";
1021                 };
1022
1023                 pru0_1: pru@38000 {
1024                         compatible = "ti,am654-pru";
1025                         reg = <0x38000 0x4000>,
1026                               <0x24000 0x100>,
1027                               <0x24400 0x100>;
1028                         reg-names = "iram", "control", "debug";
1029                         firmware-name = "am65x-pru0_1-fw";
1030                 };
1031
1032                 rtu0_1: rtu@6000 {
1033                         compatible = "ti,am654-rtu";
1034                         reg = <0x6000 0x2000>,
1035                               <0x23800 0x100>,
1036                               <0x23c00 0x100>;
1037                         reg-names = "iram", "control", "debug";
1038                         firmware-name = "am65x-rtu0_1-fw";
1039                 };
1040
1041                 tx_pru0_1: txpru@c000 {
1042                         compatible = "ti,am654-tx-pru";
1043                         reg = <0xc000 0x1800>,
1044                               <0x25800 0x100>,
1045                               <0x25c00 0x100>;
1046                         reg-names = "iram", "control", "debug";
1047                         firmware-name = "am65x-txpru0_1-fw";
1048                 };
1049
1050                 icssg0_mdio: mdio@32400 {
1051                         compatible = "ti,davinci_mdio";
1052                         reg = <0x32400 0x100>;
1053                         clocks = <&k3_clks 62 3>;
1054                         clock-names = "fck";
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                         bus_freq = <1000000>;
1058                 };
1059         };
1060
1061         icssg1: icssg@b100000 {
1062                 compatible = "ti,am654-icssg";
1063                 reg = <0x00 0xb100000 0x00 0x80000>;
1064                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1065                 #address-cells = <1>;
1066                 #size-cells = <1>;
1067                 ranges = <0x0 0x00 0xb100000 0x80000>;
1068
1069                 icssg1_mem: memories@0 {
1070                         reg = <0x0 0x2000>,
1071                               <0x2000 0x2000>,
1072                               <0x10000 0x10000>;
1073                         reg-names = "dram0", "dram1",
1074                                     "shrdram2";
1075                 };
1076
1077                 icssg1_cfg: cfg@26000 {
1078                         compatible = "ti,pruss-cfg", "syscon";
1079                         reg = <0x26000 0x200>;
1080                         #address-cells = <1>;
1081                         #size-cells = <1>;
1082                         ranges = <0x0 0x26000 0x2000>;
1083
1084                         clocks {
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087
1088                                 icssg1_coreclk_mux: coreclk-mux@3c {
1089                                         reg = <0x3c>;
1090                                         #clock-cells = <0>;
1091                                         clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
1092                                                  <&k3_clks 63 3>;  /* icssg1_iclk */
1093                                         assigned-clocks = <&icssg1_coreclk_mux>;
1094                                         assigned-clock-parents = <&k3_clks 63 3>;
1095                                 };
1096
1097                                 icssg1_iepclk_mux: iepclk-mux@30 {
1098                                         reg = <0x30>;
1099                                         #clock-cells = <0>;
1100                                         clocks = <&k3_clks 63 10>,      /* icssg1_iep_clk */
1101                                                  <&icssg1_coreclk_mux>; /* core_clk */
1102                                         assigned-clocks = <&icssg1_iepclk_mux>;
1103                                         assigned-clock-parents = <&icssg1_coreclk_mux>;
1104                                 };
1105                         };
1106                 };
1107
1108                 icssg1_mii_rt: mii-rt@32000 {
1109                         compatible = "ti,pruss-mii", "syscon";
1110                         reg = <0x32000 0x100>;
1111                 };
1112
1113                 icssg1_mii_g_rt: mii-g-rt@33000 {
1114                         compatible = "ti,pruss-mii-g", "syscon";
1115                         reg = <0x33000 0x1000>;
1116                 };
1117
1118                 icssg1_intc: interrupt-controller@20000 {
1119                         compatible = "ti,icssg-intc";
1120                         reg = <0x20000 0x2000>;
1121                         interrupt-controller;
1122                         #interrupt-cells = <3>;
1123                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1124                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1125                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1126                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1127                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1128                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1129                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1130                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
1131                         interrupt-names = "host_intr0", "host_intr1",
1132                                           "host_intr2", "host_intr3",
1133                                           "host_intr4", "host_intr5",
1134                                           "host_intr6", "host_intr7";
1135                 };
1136
1137                 pru1_0: pru@34000 {
1138                         compatible = "ti,am654-pru";
1139                         reg = <0x34000 0x4000>,
1140                               <0x22000 0x100>,
1141                               <0x22400 0x100>;
1142                         reg-names = "iram", "control", "debug";
1143                         firmware-name = "am65x-pru1_0-fw";
1144                 };
1145
1146                 rtu1_0: rtu@4000 {
1147                         compatible = "ti,am654-rtu";
1148                         reg = <0x4000 0x2000>,
1149                               <0x23000 0x100>,
1150                               <0x23400 0x100>;
1151                         reg-names = "iram", "control", "debug";
1152                         firmware-name = "am65x-rtu1_0-fw";
1153                 };
1154
1155                 tx_pru1_0: txpru@a000 {
1156                         compatible = "ti,am654-tx-pru";
1157                         reg = <0xa000 0x1800>,
1158                               <0x25000 0x100>,
1159                               <0x25400 0x100>;
1160                         reg-names = "iram", "control", "debug";
1161                         firmware-name = "am65x-txpru1_0-fw";
1162                 };
1163
1164                 pru1_1: pru@38000 {
1165                         compatible = "ti,am654-pru";
1166                         reg = <0x38000 0x4000>,
1167                               <0x24000 0x100>,
1168                               <0x24400 0x100>;
1169                         reg-names = "iram", "control", "debug";
1170                         firmware-name = "am65x-pru1_1-fw";
1171                 };
1172
1173                 rtu1_1: rtu@6000 {
1174                         compatible = "ti,am654-rtu";
1175                         reg = <0x6000 0x2000>,
1176                               <0x23800 0x100>,
1177                               <0x23c00 0x100>;
1178                         reg-names = "iram", "control", "debug";
1179                         firmware-name = "am65x-rtu1_1-fw";
1180                 };
1181
1182                 tx_pru1_1: txpru@c000 {
1183                         compatible = "ti,am654-tx-pru";
1184                         reg = <0xc000 0x1800>,
1185                               <0x25800 0x100>,
1186                               <0x25c00 0x100>;
1187                         reg-names = "iram", "control", "debug";
1188                         firmware-name = "am65x-txpru1_1-fw";
1189                 };
1190
1191                 icssg1_mdio: mdio@32400 {
1192                         compatible = "ti,davinci_mdio";
1193                         reg = <0x32400 0x100>;
1194                         clocks = <&k3_clks 63 3>;
1195                         clock-names = "fck";
1196                         #address-cells = <1>;
1197                         #size-cells = <0>;
1198                         bus_freq = <1000000>;
1199                 };
1200         };
1201
1202         icssg2: icssg@b200000 {
1203                 compatible = "ti,am654-icssg";
1204                 reg = <0x00 0xb200000 0x00 0x80000>;
1205                 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1206                 #address-cells = <1>;
1207                 #size-cells = <1>;
1208                 ranges = <0x0 0x00 0xb200000 0x80000>;
1209
1210                 icssg2_mem: memories@0 {
1211                         reg = <0x0 0x2000>,
1212                               <0x2000 0x2000>,
1213                               <0x10000 0x10000>;
1214                         reg-names = "dram0", "dram1",
1215                                     "shrdram2";
1216                 };
1217
1218                 icssg2_cfg: cfg@26000 {
1219                         compatible = "ti,pruss-cfg", "syscon";
1220                         reg = <0x26000 0x200>;
1221                         #address-cells = <1>;
1222                         #size-cells = <1>;
1223                         ranges = <0x0 0x26000 0x2000>;
1224
1225                         clocks {
1226                                 #address-cells = <1>;
1227                                 #size-cells = <0>;
1228
1229                                 icssg2_coreclk_mux: coreclk-mux@3c {
1230                                         reg = <0x3c>;
1231                                         #clock-cells = <0>;
1232                                         clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
1233                                                  <&k3_clks 64 3>;  /* icssg1_iclk */
1234                                         assigned-clocks = <&icssg2_coreclk_mux>;
1235                                         assigned-clock-parents = <&k3_clks 64 3>;
1236                                 };
1237
1238                                 icssg2_iepclk_mux: iepclk-mux@30 {
1239                                         reg = <0x30>;
1240                                         #clock-cells = <0>;
1241                                         clocks = <&k3_clks 64 10>,      /* icssg1_iep_clk */
1242                                                  <&icssg2_coreclk_mux>; /* core_clk */
1243                                         assigned-clocks = <&icssg2_iepclk_mux>;
1244                                         assigned-clock-parents = <&icssg2_coreclk_mux>;
1245                                 };
1246                         };
1247                 };
1248
1249                 icssg2_mii_rt: mii-rt@32000 {
1250                         compatible = "ti,pruss-mii", "syscon";
1251                         reg = <0x32000 0x100>;
1252                 };
1253
1254                 icssg2_mii_g_rt: mii-g-rt@33000 {
1255                         compatible = "ti,pruss-mii-g", "syscon";
1256                         reg = <0x33000 0x1000>;
1257                 };
1258
1259                 icssg2_intc: interrupt-controller@20000 {
1260                         compatible = "ti,icssg-intc";
1261                         reg = <0x20000 0x2000>;
1262                         interrupt-controller;
1263                         #interrupt-cells = <3>;
1264                         interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1270                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
1271                                      <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
1272                         interrupt-names = "host_intr0", "host_intr1",
1273                                           "host_intr2", "host_intr3",
1274                                           "host_intr4", "host_intr5",
1275                                           "host_intr6", "host_intr7";
1276                 };
1277
1278                 pru2_0: pru@34000 {
1279                         compatible = "ti,am654-pru";
1280                         reg = <0x34000 0x4000>,
1281                               <0x22000 0x100>,
1282                               <0x22400 0x100>;
1283                         reg-names = "iram", "control", "debug";
1284                         firmware-name = "am65x-pru2_0-fw";
1285                 };
1286
1287                 rtu2_0: rtu@4000 {
1288                         compatible = "ti,am654-rtu";
1289                         reg = <0x4000 0x2000>,
1290                               <0x23000 0x100>,
1291                               <0x23400 0x100>;
1292                         reg-names = "iram", "control", "debug";
1293                         firmware-name = "am65x-rtu2_0-fw";
1294                 };
1295
1296                 tx_pru2_0: txpru@a000 {
1297                         compatible = "ti,am654-tx-pru";
1298                         reg = <0xa000 0x1800>,
1299                               <0x25000 0x100>,
1300                               <0x25400 0x100>;
1301                         reg-names = "iram", "control", "debug";
1302                         firmware-name = "am65x-txpru2_0-fw";
1303                 };
1304
1305                 pru2_1: pru@38000 {
1306                         compatible = "ti,am654-pru";
1307                         reg = <0x38000 0x4000>,
1308                               <0x24000 0x100>,
1309                               <0x24400 0x100>;
1310                         reg-names = "iram", "control", "debug";
1311                         firmware-name = "am65x-pru2_1-fw";
1312                 };
1313
1314                 rtu2_1: rtu@6000 {
1315                         compatible = "ti,am654-rtu";
1316                         reg = <0x6000 0x2000>,
1317                               <0x23800 0x100>,
1318                               <0x23c00 0x100>;
1319                         reg-names = "iram", "control", "debug";
1320                         firmware-name = "am65x-rtu2_1-fw";
1321                 };
1322
1323                 tx_pru2_1: txpru@c000 {
1324                         compatible = "ti,am654-tx-pru";
1325                         reg = <0xc000 0x1800>,
1326                               <0x25800 0x100>,
1327                               <0x25c00 0x100>;
1328                         reg-names = "iram", "control", "debug";
1329                         firmware-name = "am65x-txpru2_1-fw";
1330                 };
1331
1332                 icssg2_mdio: mdio@32400 {
1333                         compatible = "ti,davinci_mdio";
1334                         reg = <0x32400 0x100>;
1335                         clocks = <&k3_clks 64 3>;
1336                         clock-names = "fck";
1337                         #address-cells = <1>;
1338                         #size-cells = <0>;
1339                         bus_freq = <1000000>;
1340                 };
1341         };
1342 };