1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/phy/phy-am654-serdes.h>
9 #include <dt-bindings/phy/phy.h>
12 gic500: interrupt-controller@1800000 {
13 compatible = "arm,gic-v3";
17 #interrupt-cells = <3>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0x90000>; /* GICR */
23 * virtual CPU interface maintenance interrupt
25 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
27 gic_its: gic-its@18200000 {
28 compatible = "arm,gic-v3-its";
29 reg = <0x00 0x01820000 0x00 0x10000>;
35 secure_proxy_main: mailbox@32c00000 {
36 compatible = "ti,am654-secure-proxy";
38 reg-names = "target_data", "rt", "scfg";
39 reg = <0x00 0x32c00000 0x00 0x100000>,
40 <0x00 0x32400000 0x00 0x100000>,
41 <0x00 0x32800000 0x00 0x100000>;
42 interrupt-names = "rx_011";
43 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
46 main_uart0: serial@2800000 {
47 compatible = "ti,am654-uart";
48 reg = <0x00 0x02800000 0x00 0x100>;
51 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
52 clock-frequency = <48000000>;
53 current-speed = <115200>;
56 main_uart1: serial@2810000 {
57 compatible = "ti,am654-uart";
58 reg = <0x00 0x02810000 0x00 0x100>;
61 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
62 clock-frequency = <48000000>;
63 current-speed = <115200>;
66 main_uart2: serial@2820000 {
67 compatible = "ti,am654-uart";
68 reg = <0x00 0x02820000 0x00 0x100>;
71 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
72 clock-frequency = <48000000>;
73 current-speed = <115200>;
76 main_pmx0: pinmux@11c000 {
77 compatible = "pinctrl-single";
78 reg = <0x0 0x11c000 0x0 0x2e4>;
80 pinctrl-single,register-width = <32>;
81 pinctrl-single,function-mask = <0xffffffff>;
84 main_pmx1: pinmux@11c2e8 {
85 compatible = "pinctrl-single";
86 reg = <0x0 0x11c2e8 0x0 0x24>;
88 pinctrl-single,register-width = <32>;
89 pinctrl-single,function-mask = <0xffffffff>;
92 sdhci0: sdhci@4f80000 {
93 compatible = "ti,am654-sdhci-5.1";
94 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
95 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
96 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
97 clock-names = "clk_ahb", "clk_xin";
98 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
101 ti,otap-del-sel-legacy = <0x0>;
102 ti,otap-del-sel-mmc-hs = <0x0>;
103 ti,otap-del-sel-sd-hs = <0x0>;
104 ti,otap-del-sel-sdr12 = <0x0>;
105 ti,otap-del-sel-sdr25 = <0x0>;
106 ti,otap-del-sel-sdr50 = <0x8>;
107 ti,otap-del-sel-sdr104 = <0x5>;
108 ti,otap-del-sel-ddr50 = <0x5>;
109 ti,otap-del-sel-ddr52 = <0x5>;
110 ti,otap-del-sel-hs200 = <0x5>;
111 ti,otap-del-sel-hs400 = <0x0>;
116 main_i2c0: i2c@2000000 {
117 compatible = "ti,am654-i2c", "ti,omap4-i2c";
118 reg = <0x0 0x2000000 0x0 0x100>;
119 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
120 #address-cells = <1>;
123 clocks = <&k3_clks 110 1>;
124 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
127 main_i2c1: i2c@2010000 {
128 compatible = "ti,am654-i2c", "ti,omap4-i2c";
129 reg = <0x0 0x2010000 0x0 0x100>;
130 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
131 #address-cells = <1>;
134 clocks = <&k3_clks 111 1>;
135 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
138 main_i2c2: i2c@2020000 {
139 compatible = "ti,am654-i2c", "ti,omap4-i2c";
140 reg = <0x0 0x2020000 0x0 0x100>;
141 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
145 clocks = <&k3_clks 112 1>;
146 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
149 main_i2c3: i2c@2030000 {
150 compatible = "ti,am654-i2c", "ti,omap4-i2c";
151 reg = <0x0 0x2030000 0x0 0x100>;
152 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
153 #address-cells = <1>;
156 clocks = <&k3_clks 113 1>;
157 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
160 scm_conf: scm_conf@100000 {
161 compatible = "syscon", "simple-mfd";
162 reg = <0 0x00100000 0 0x1c000>;
163 #address-cells = <1>;
165 ranges = <0x0 0x0 0x00100000 0x1c000>;
167 serdes_mux: mux-controller {
168 compatible = "mmio-mux";
169 #mux-control-cells = <1>;
170 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
171 <0x4090 0x3>; /* SERDES1 lane select */
174 pcie0_mode: pcie-mode@4060 {
175 compatible = "syscon";
176 reg = <0x00004060 0x4>;
179 pcie1_mode: pcie-mode@4070 {
180 compatible = "syscon";
181 reg = <0x00004070 0x4>;
184 serdes0_clk: serdes_clk@4080 {
185 compatible = "syscon";
186 reg = <0x00004080 0x4>;
189 serdes1_clk: serdes_clk@4090 {
190 compatible = "syscon";
191 reg = <0x00004090 0x4>;
194 pcie_devid: pcie-devid@210 {
195 compatible = "syscon";
196 reg = <0x00000210 0x4>;
200 serdes0: serdes@900000 {
201 compatible = "ti,phy-am654-serdes";
202 reg = <0x0 0x900000 0x0 0x2000>;
203 reg-names = "serdes";
205 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
206 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
207 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
208 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
209 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
210 ti,serdes-clk = <&serdes0_clk>;
211 mux-controls = <&serdes_mux 0>;
215 serdes1: serdes@910000 {
216 compatible = "ti,phy-am654-serdes";
217 reg = <0x0 0x910000 0x0 0x2000>;
218 reg-names = "serdes";
220 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
221 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
222 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
223 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
224 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
225 ti,serdes-clk = <&serdes1_clk>;
226 mux-controls = <&serdes_mux 1>;
230 pcie0_rc: pcie@5500000 {
231 compatible = "ti,am654-pcie-rc";
232 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
233 reg-names = "app", "dbics", "config", "atu";
234 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
235 #address-cells = <3>;
237 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
238 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
239 ti,syscon-pcie-id = <&pcie_devid>;
240 ti,syscon-pcie-mode = <&pcie0_mode>;
241 bus-range = <0x0 0xff>;
245 num-ob-windows = <16>;
247 max-link-speed = <3>;
248 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
249 #interrupt-cells = <1>;
250 interrupt-map-mask = <0 0 0 7>;
251 interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
252 <0 0 0 2 &pcie0_intc 0>, /* INT B */
253 <0 0 0 3 &pcie0_intc 0>, /* INT C */
254 <0 0 0 4 &pcie0_intc 0>; /* INT D */
255 msi-map = <0x0 &gic_its 0x0 0x10000>;
257 pcie0_intc: legacy-interrupt-controller@1 {
258 interrupt-controller;
259 #interrupt-cells = <1>;
260 interrupt-parent = <&gic500>;
261 interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
265 dwc3_0: dwc3@4000000 {
266 compatible = "ti,am654-dwc3";
267 reg = <0x0 0x4000000 0x0 0x4000>;
268 #address-cells = <1>;
270 ranges = <0x0 0x0 0x4000000 0x20000>;
271 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
273 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
274 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
275 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
276 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
279 compatible = "snps,dwc3";
280 reg = <0x10000 0x10000>;
281 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "peripheral",
287 maximum-speed = "high-speed";
290 phy-names = "usb2-phy";
291 snps,dis_u3_susphy_quirk;
295 usb0_phy: phy@4100000 {
296 compatible = "ti,am654-usb2", "ti,omap-usb2";
297 reg = <0x0 0x4100000 0x0 0x54>;
298 syscon-phy-power = <&scm_conf 0x4000>;
299 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
300 clock-names = "wkupclk", "refclk";
302 ti,dis-chg-det-quirk;
305 dwc3_1: dwc3@4020000 {
306 compatible = "ti,am654-dwc3";
307 reg = <0x0 0x4020000 0x0 0x4000>;
308 #address-cells = <1>;
310 ranges = <0x0 0x0 0x4020000 0x20000>;
311 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
313 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
314 assigned-clocks = <&k3_clks 152 2>;
315 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
318 compatible = "snps,dwc3";
319 reg = <0x10000 0x10000>;
320 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
323 interrupt-names = "peripheral",
326 maximum-speed = "high-speed";
329 phy-names = "usb2-phy";
333 usb1_phy: phy@4110000 {
334 compatible = "ti,am654-usb2", "ti,omap-usb2";
335 reg = <0x0 0x4110000 0x0 0x54>;
336 syscon-phy-power = <&scm_conf 0x4020>;
337 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
338 clock-names = "wkupclk", "refclk";
340 ti,dis-chg-det-quirk;