arch/arm/dts/k3-am642-sk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/net/ti-dp83867.h>
  10 #include "k3-am642.dtsi"
  11
  12 / {
  13         compatible =  "ti,am642-sk", "ti,am642";
  14         model = "Texas Instruments AM642 SK";
  15
  16         chosen {
  17                 stdout-path = "serial2:115200n8";
  18                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
  19         };
  20
  21         memory@80000000 {
  22                 device_type = "memory";
  23                 /* 2G RAM */
  24                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
  25
  26         };
  27
  28         reserved-memory {
  29                 #address-cells = <2>;
  30                 #size-cells = <2>;
  31                 ranges;
  32
  33                 secure_ddr: optee@9e800000 {
  34                         reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
  35                         alignment = <0x1000>;
  36                         no-map;
  37                 };
  38         };
  39 };
  40
  41 &main_pmx0 {
  42         main_mmc1_pins_default: main-mmc1-pins-default {
  43                 pinctrl-single,pins = <
  44                         AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
  45                         AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
  46                         AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
  47                         AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
  48                         AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
  49                         AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
  50                         AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
  51                         AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
  52                 >;
  53         };
  54
  55         main_i2c1_pins_default: main-i2c1-pins-default {
  56                 pinctrl-single,pins = <
  57                         AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
  58                         AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
  59                 >;
  60         };
  61
  62         mdio1_pins_default: mdio1-pins-default {
  63                 pinctrl-single,pins = <
  64                         AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
  65                         AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
  66                 >;
  67         };
  68
  69         rgmii1_pins_default: rgmii1-pins-default {
  70                 pinctrl-single,pins = <
  71                         AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
  72                         AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
  73                         AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
  74                         AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
  75                         AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
  76                         AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
  77                         AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
  78                         AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
  79                         AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
  80                         AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
  81                         AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
  82                         AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
  83                 >;
  84         };
  85
  86        rgmii2_pins_default: rgmii2-pins-default {
  87                 pinctrl-single,pins = <
  88                         AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
  89                         AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
  90                         AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
  91                         AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
  92                         AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
  93                         AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
  94                         AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
  95                         AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
  96                         AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
  97                         AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
  98                         AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
  99                         AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
 100                 >;
 101         };
 102 };
 103
 104 &main_uart1 {
 105         /* main_uart1 is reserved for firmware usage */
 106         status = "reserved";
 107 };
 108
 109 &main_uart2 {
 110         status = "disabled";
 111 };
 112
 113 &main_uart3 {
 114         status = "disabled";
 115 };
 116
 117 &main_uart4 {
 118         status = "disabled";
 119 };
 120
 121 &main_uart5 {
 122         status = "disabled";
 123 };
 124
 125 &main_uart6 {
 126         status = "disabled";
 127 };
 128
 129 &sdhci1 {
 130         /* SD/MMC */
 131         pinctrl-names = "default";
 132         bus-width = <4>;
 133         pinctrl-0 = <&main_mmc1_pins_default>;
 134         ti,driver-strength-ohm = <50>;
 135         disable-wp;
 136 };
 137
 138 &cpsw3g {
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&mdio1_pins_default
 141                      &rgmii1_pins_default
 142                      &rgmii2_pins_default>;
 143 };
 144
 145 &cpsw_port1 {
 146         phy-mode = "rgmii-rxid";
 147         phy-handle = <&cpsw3g_phy0>;
 148 };
 149
 150 &cpsw3g_mdio {
 151         cpsw3g_phy0: ethernet-phy@0 {
 152                 reg = <0>;
 153                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 154                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 155         };
 156 };