arch/arm/dts/k3-am642-sk-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 / {
   7         chosen {
   8                 stdout-path = "serial2:115200n8";
   9                 tick-timer = &timer1;
  10         };
  11
  12         aliases {
  13                 mmc1 = &sdhci1;
  14         };
  15 };
  16
  17 &cbass_main{
  18         u-boot,dm-spl;
  19         timer1: timer@2400000 {
  20                 compatible = "ti,omap5430-timer";
  21                 reg = <0x0 0x2400000 0x0 0x80>;
  22                 ti,timer-alwon;
  23                 clock-frequency = <250000000>;
  24                 u-boot,dm-spl;
  25         };
  26 };
  27
  28 &main_conf {
  29         u-boot,dm-spl;
  30         chipid@14 {
  31                 u-boot,dm-spl;
  32         };
  33 };
  34
  35 &main_pmx0 {
  36         u-boot,dm-spl;
  37         main_i2c0_pins_default: main-i2c0-pins-default {
  38                 u-boot,dm-spl;
  39                 pinctrl-single,pins = <
  40                         AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
  41                         AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
  42                 >;
  43         };
  44 };
  45
  46 &main_i2c0 {
  47         u-boot,dm-spl;
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&main_i2c0_pins_default>;
  50         clock-frequency = <400000>;
  51 };
  52
  53 &main_uart0 {
  54         u-boot,dm-spl;
  55 };
  56
  57 &dmss {
  58         u-boot,dm-spl;
  59 };
  60
  61 &secure_proxy_main {
  62         u-boot,dm-spl;
  63 };
  64
  65 &dmsc {
  66         u-boot,dm-spl;
  67         k3_sysreset: sysreset-controller {
  68                 compatible = "ti,sci-sysreset";
  69                 u-boot,dm-spl;
  70         };
  71 };
  72
  73 &k3_pds {
  74         u-boot,dm-spl;
  75 };
  76
  77 &k3_clks {
  78         u-boot,dm-spl;
  79 };
  80
  81 &k3_reset {
  82         u-boot,dm-spl;
  83 };
  84
  85 &sdhci0 {
  86         status = "disabled";
  87         u-boot,dm-spl;
  88 };
  89
  90 &sdhci1 {
  91         u-boot,dm-spl;
  92 };
  93
  94 &main_mmc1_pins_default {
  95         u-boot,dm-spl;
  96 };
  97
  98 &cpsw3g {
  99         reg = <0x0 0x8000000 0x0 0x200000>,
 100               <0x0 0x43000200 0x0 0x8>;
 101         reg-names = "cpsw_nuss", "mac_efuse";
 102         /delete-property/ ranges;
 103         u-boot,dm-spl;
 104
 105         cpsw-phy-sel@04044 {
 106                 compatible = "ti,am64-phy-gmii-sel";
 107                 reg = <0x0 0x43004044 0x0 0x8>;
 108                 u-boot,dm-spl;
 109         };
 110
 111         ethernet-ports {
 112                 u-boot,dm-spl;
 113         };
 114 };
 115
 116 &cpsw_port2 {
 117         u-boot,dm-spl;
 118 };
 119
 120 &cpsw_port1 {
 121         u-boot,dm-spl;
 122 };
 123
 124 &main_bcdma {
 125         u-boot,dm-spl;
 126 };
 127
 128 &main_pktdma {
 129         u-boot,dm-spl;
 130 };
 131
 132 &rgmii1_pins_default {
 133         u-boot,dm-spl;
 134 };
 135
 136 &rgmii2_pins_default {
 137         u-boot,dm-spl;
 138 };
 139
 140 &mdio1_pins_default {
 141         u-boot,dm-spl;
 142 };
 143
 144 &cpsw3g_phy0 {
 145         u-boot,dm-spl;
 146 };
 147
 148 &cpsw3g_phy1 {
 149         u-boot,dm-spl;
 150 };
 151
 152 &main_usb0_pins_default {
 153         u-boot,dm-spl;
 154 };
 155
 156 &serdes_ln_ctrl {
 157         u-boot,mux-autoprobe;
 158 };
 159
 160 &usbss0 {
 161         u-boot,dm-spl;
 162 };
 163
 164 &usb0 {
 165         dr_mode = "host";
 166         u-boot,dm-spl;
 167 };
 168
 169 &serdes_wiz0 {
 170         u-boot,dm-spl;
 171 };
 172
 173 &serdes0_usb_link {
 174         u-boot,dm-spl;
 175 };
 176
 177 &serdes0 {
 178         u-boot,dm-spl;
 179 };
 180
 181 &serdes_refclk {
 182         u-boot,dm-spl;
 183 };