arch/arm/dts/imxrt1020.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2020
   4  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
   5  */
   6
   7 #include "armv7-m.dtsi"
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/imxrt1020-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/memory/imxrt-sdram.h>
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 mmc0 = &usdhc1;
  22                 serial0 = &lpuart1;
  23         };
  24
  25         clocks {
  26                 ckil {
  27                         compatible = "fsl,imx-ckil", "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <32768>;
  30                 };
  31
  32                 ckih1 {
  33                         compatible = "fsl,imx-ckih1", "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <0>;
  36                 };
  37
  38                 osc: osc {
  39                         compatible = "fsl,imx-osc", "fixed-clock";
  40                         #clock-cells = <0>;
  41                         clock-frequency = <24000000>;
  42                 };
  43         };
  44
  45         soc {
  46                 semc: semc@402f0000 {
  47                         compatible = "fsl,imxrt-semc";
  48                         reg = <0x402f0000 0x4000>;
  49                         clocks = <&clks IMXRT1020_CLK_SEMC>;
  50                         pinctrl-0 = <&pinctrl_semc>;
  51                         pinctrl-names = "default";
  52                         status = "okay";
  53                 };
  54
  55                 lpuart1: serial@40184000 {
  56                         compatible = "fsl,imxrt-lpuart";
  57                         reg = <0x40184000 0x4000>;
  58                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  59                         clocks = <&clks IMXRT1020_CLK_LPUART1>;
  60                         clock-names = "per";
  61                         status = "disabled";
  62                 };
  63
  64                 iomuxc: iomuxc@401f8000 {
  65                         compatible = "fsl,imxrt-iomuxc";
  66                         reg = <0x401f8000 0x4000>;
  67                         fsl,mux_mask = <0x7>;
  68                 };
  69
  70                 anatop: anatop@400d8000 {
  71                         compatible = "fsl,imxrt-anatop";
  72                         reg = <0x400d8000 0x4000>;
  73                 };
  74
  75                 clks: ccm@400fc000 {
  76                         compatible = "fsl,imxrt1020-ccm";
  77                         reg = <0x400fc000 0x4000>;
  78                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  80                         #clock-cells = <1>;
  81                 };
  82
  83                 usdhc1: usdhc@402c0000 {
  84                         compatible = "fsl,imxrt-usdhc";
  85                         reg = <0x402c0000 0x10000>;
  86                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  87                         clocks = <&clks IMXRT1020_CLK_USDHC1>;
  88                         clock-names = "per";
  89                         bus-width = <4>;
  90                         fsl,tuning-start-tap = <20>;
  91                         fsl,tuning-step= <2>;
  92                         status = "disabled";
  93                 };
  94
  95                 gpio1: gpio@401b8000 {
  96                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
  97                         reg = <0x401b8000 0x4000>;
  98                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  99                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 100                         gpio-controller;
 101                         #gpio-cells = <2>;
 102                         interrupt-controller;
 103                         #interrupt-cells = <2>;
 104                 };
 105
 106                 gpio2: gpio@401bc000 {
 107                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 108                         reg = <0x401bc000 0x4000>;
 109                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 110                                 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 111                         gpio-controller;
 112                         #gpio-cells = <2>;
 113                         interrupt-controller;
 114                         #interrupt-cells = <2>;
 115                 };
 116
 117                 gpio3: gpio@401c0000 {
 118                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 119                         reg = <0x401c0000 0x4000>;
 120                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 121                                 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 122                         gpio-controller;
 123                         #gpio-cells = <2>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <2>;
 126                 };
 127
 128                 gpio5: gpio@400c0000 {
 129                         compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
 130                         reg = <0x400c0000 0x4000>;
 131                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 132                                 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 133                         gpio-controller;
 134                         #gpio-cells = <2>;
 135                         interrupt-controller;
 136                         #interrupt-cells = <2>;
 137                 };
 138
 139                 gpt1: gpt1@401ec000 {
 140                         compatible = "fsl,imxrt-gpt";
 141                         reg = <0x401ec000 0x4000>;
 142                         interrupts = <100>;
 143                         clocks = <&osc>;
 144                         status = "disabled";
 145                 };
 146         };
 147 };