1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
8 #include "imxrt1020.dtsi"
9 #include "imxrt1020-evk-u-boot.dtsi"
10 #include <dt-bindings/pinctrl/pins-imxrt1020.h>
13 model = "NXP IMXRT1020-evk board";
14 compatible = "fsl,imxrt1020-evk", "fsl,imxrt1020";
17 bootargs = "root=/dev/ram";
18 stdout-path = "serial0:115200n8";
23 device_type = "memory";
24 reg = <0x80000000 0x2000000>;
28 &lpuart1 { /* console */
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_lpuart1>;
36 * Memory configuration from sdram datasheet IS42S16160J-6TLI
38 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
44 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
48 fsl,sdram-timing = /bits/ 8 <0x2
66 fsl,base-address = <0x80000000>;
67 fsl,memory-size = <MEM_SIZE_32M>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_lpuart1>;
76 pinctrl_lpuart1: lpuart1grp {
78 MXRT1020_IOMUXC_GPIO_AD_B0_06_LPUART1_TX
80 MXRT1020_IOMUXC_GPIO_AD_B0_07_LPUART1_RX
85 pinctrl_semc: semcgrp {
87 MXRT1020_IOMUXC_GPIO_EMC_00_SEMC_DA00
89 MXRT1020_IOMUXC_GPIO_EMC_01_SEMC_DA01
91 MXRT1020_IOMUXC_GPIO_EMC_02_SEMC_DA02
93 MXRT1020_IOMUXC_GPIO_EMC_03_SEMC_DA03
95 MXRT1020_IOMUXC_GPIO_EMC_04_SEMC_DA04
97 MXRT1020_IOMUXC_GPIO_EMC_05_SEMC_DA05
99 MXRT1020_IOMUXC_GPIO_EMC_06_SEMC_DA06
101 MXRT1020_IOMUXC_GPIO_EMC_07_SEMC_DA07
103 MXRT1020_IOMUXC_GPIO_EMC_08_SEMC_DM00
105 MXRT1020_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
107 MXRT1020_IOMUXC_GPIO_EMC_10_SEMC_CAS
109 MXRT1020_IOMUXC_GPIO_EMC_11_SEMC_RAS
111 MXRT1020_IOMUXC_GPIO_EMC_12_SEMC_CS0
113 MXRT1020_IOMUXC_GPIO_EMC_13_SEMC_BA0
115 MXRT1020_IOMUXC_GPIO_EMC_14_SEMC_BA1
117 MXRT1020_IOMUXC_GPIO_EMC_15_SEMC_ADDR10
119 MXRT1020_IOMUXC_GPIO_EMC_16_SEMC_ADDR00
121 MXRT1020_IOMUXC_GPIO_EMC_17_SEMC_ADDR01
123 MXRT1020_IOMUXC_GPIO_EMC_18_SEMC_ADDR02
125 MXRT1020_IOMUXC_GPIO_EMC_19_SEMC_ADDR03
127 MXRT1020_IOMUXC_GPIO_EMC_20_SEMC_ADDR04
129 MXRT1020_IOMUXC_GPIO_EMC_21_SEMC_ADDR05
131 MXRT1020_IOMUXC_GPIO_EMC_22_SEMC_ADDR06
133 MXRT1020_IOMUXC_GPIO_EMC_23_SEMC_ADDR07
135 MXRT1020_IOMUXC_GPIO_EMC_24_SEMC_ADDR08
137 MXRT1020_IOMUXC_GPIO_EMC_25_SEMC_ADDR09
139 MXRT1020_IOMUXC_GPIO_EMC_26_SEMC_ADDR11
141 MXRT1020_IOMUXC_GPIO_EMC_27_SEMC_ADDR12
143 MXRT1020_IOMUXC_GPIO_EMC_28_SEMC_DQS
144 (IMX_PAD_SION | 0xf1) /* SEMC_DQS */
145 MXRT1020_IOMUXC_GPIO_EMC_29_SEMC_CKE
147 MXRT1020_IOMUXC_GPIO_EMC_30_SEMC_CLK
149 MXRT1020_IOMUXC_GPIO_EMC_31_SEMC_DM01
151 MXRT1020_IOMUXC_GPIO_EMC_32_SEMC_DATA08
153 MXRT1020_IOMUXC_GPIO_EMC_33_SEMC_DATA09
155 MXRT1020_IOMUXC_GPIO_EMC_34_SEMC_DATA10
157 MXRT1020_IOMUXC_GPIO_EMC_35_SEMC_DATA11
159 MXRT1020_IOMUXC_GPIO_EMC_36_SEMC_DATA12
161 MXRT1020_IOMUXC_GPIO_EMC_37_SEMC_DATA13
163 MXRT1020_IOMUXC_GPIO_EMC_38_SEMC_DATA14
165 MXRT1020_IOMUXC_GPIO_EMC_39_SEMC_DATA15
170 pinctrl_usdhc0: usdhc0grp {
172 MXRT1020_IOMUXC_GPIO_SD_B0_06_USDHC1_CD_B
174 MXRT1020_IOMUXC_GPIO_SD_B0_02_USDHC1_CMD
176 MXRT1020_IOMUXC_GPIO_SD_B0_03_USDHC1_CLK
178 MXRT1020_IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3
180 MXRT1020_IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2
182 MXRT1020_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1
184 MXRT1020_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0
196 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
197 pinctrl-0 = <&pinctrl_usdhc0>;
198 pinctrl-1 = <&pinctrl_usdhc0>;
199 pinctrl-2 = <&pinctrl_usdhc0>;
200 pinctrl-3 = <&pinctrl_usdhc0>;
203 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;