arch/arm/dts/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &fec1;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 i2c3 = &i2c4;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42                 usb0 = &usb_dwc3_0;
  43                 usb1 = &usb_dwc3_1;
  44         };
  45
  46         ckil: clock-ckil {
  47                 compatible = "fixed-clock";
  48                 #clock-cells = <0>;
  49                 clock-frequency = <32768>;
  50                 clock-output-names = "ckil";
  51         };
  52
  53         osc_25m: clock-osc-25m {
  54                 compatible = "fixed-clock";
  55                 #clock-cells = <0>;
  56                 clock-frequency = <25000000>;
  57                 clock-output-names = "osc_25m";
  58         };
  59
  60         osc_27m: clock-osc-27m {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <27000000>;
  64                 clock-output-names = "osc_27m";
  65         };
  66
  67         clk_ext1: clock-ext1 {
  68                 compatible = "fixed-clock";
  69                 #clock-cells = <0>;
  70                 clock-frequency = <133000000>;
  71                 clock-output-names = "clk_ext1";
  72         };
  73
  74         clk_ext2: clock-ext2 {
  75                 compatible = "fixed-clock";
  76                 #clock-cells = <0>;
  77                 clock-frequency = <133000000>;
  78                 clock-output-names = "clk_ext2";
  79         };
  80
  81         clk_ext3: clock-ext3 {
  82                 compatible = "fixed-clock";
  83                 #clock-cells = <0>;
  84                 clock-frequency = <133000000>;
  85                 clock-output-names = "clk_ext3";
  86         };
  87
  88         clk_ext4: clock-ext4 {
  89                 compatible = "fixed-clock";
  90                 #clock-cells = <0>;
  91                 clock-frequency= <133000000>;
  92                 clock-output-names = "clk_ext4";
  93         };
  94
  95         cpus {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 A53_0: cpu@0 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53";
 102                         reg = <0x0>;
 103                         clock-latency = <61036>; /* two CLK32 periods */
 104                         clocks = <&clk IMX8MQ_CLK_ARM>;
 105                         enable-method = "psci";
 106                         next-level-cache = <&A53_L2>;
 107                         operating-points-v2 = <&a53_opp_table>;
 108                         #cooling-cells = <2>;
 109                         nvmem-cells = <&cpu_speed_grade>;
 110                         nvmem-cell-names = "speed_grade";
 111                 };
 112
 113                 A53_1: cpu@1 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53";
 116                         reg = <0x1>;
 117                         clock-latency = <61036>; /* two CLK32 periods */
 118                         clocks = <&clk IMX8MQ_CLK_ARM>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&A53_L2>;
 121                         operating-points-v2 = <&a53_opp_table>;
 122                         #cooling-cells = <2>;
 123                 };
 124
 125                 A53_2: cpu@2 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53";
 128                         reg = <0x2>;
 129                         clock-latency = <61036>; /* two CLK32 periods */
 130                         clocks = <&clk IMX8MQ_CLK_ARM>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&A53_L2>;
 133                         operating-points-v2 = <&a53_opp_table>;
 134                         #cooling-cells = <2>;
 135                 };
 136
 137                 A53_3: cpu@3 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53";
 140                         reg = <0x3>;
 141                         clock-latency = <61036>; /* two CLK32 periods */
 142                         clocks = <&clk IMX8MQ_CLK_ARM>;
 143                         enable-method = "psci";
 144                         next-level-cache = <&A53_L2>;
 145                         operating-points-v2 = <&a53_opp_table>;
 146                         #cooling-cells = <2>;
 147                 };
 148
 149                 A53_L2: l2-cache0 {
 150                         compatible = "cache";
 151                 };
 152         };
 153
 154         a53_opp_table: opp-table {
 155                 compatible = "operating-points-v2";
 156                 opp-shared;
 157
 158                 opp-800000000 {
 159                         opp-hz = /bits/ 64 <800000000>;
 160                         opp-microvolt = <900000>;
 161                         /* Industrial only */
 162                         opp-supported-hw = <0xf>, <0x4>;
 163                         clock-latency-ns = <150000>;
 164                         opp-suspend;
 165                 };
 166
 167                 opp-1000000000 {
 168                         opp-hz = /bits/ 64 <1000000000>;
 169                         opp-microvolt = <900000>;
 170                         /* Consumer only */
 171                         opp-supported-hw = <0xe>, <0x3>;
 172                         clock-latency-ns = <150000>;
 173                         opp-suspend;
 174                 };
 175
 176                 opp-1300000000 {
 177                         opp-hz = /bits/ 64 <1300000000>;
 178                         opp-microvolt = <1000000>;
 179                         opp-supported-hw = <0xc>, <0x4>;
 180                         clock-latency-ns = <150000>;
 181                         opp-suspend;
 182                 };
 183
 184                 opp-1500000000 {
 185                         opp-hz = /bits/ 64 <1500000000>;
 186                         opp-microvolt = <1000000>;
 187                         opp-supported-hw = <0x8>, <0x3>;
 188                         clock-latency-ns = <150000>;
 189                         opp-suspend;
 190                 };
 191         };
 192
 193         pmu {
 194                 compatible = "arm,cortex-a53-pmu";
 195                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 196                 interrupt-parent = <&gic>;
 197                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-1.0";
 202                 method = "smc";
 203         };
 204
 205         thermal-zones {
 206                 cpu_thermal: cpu-thermal {
 207                         polling-delay-passive = <250>;
 208                         polling-delay = <2000>;
 209                         thermal-sensors = <&tmu 0>;
 210
 211                         trips {
 212                                 cpu_alert: cpu-alert {
 213                                         temperature = <80000>;
 214                                         hysteresis = <2000>;
 215                                         type = "passive";
 216                                 };
 217
 218                                 cpu-crit {
 219                                         temperature = <90000>;
 220                                         hysteresis = <2000>;
 221                                         type = "critical";
 222                                 };
 223                         };
 224
 225                         cooling-maps {
 226                                 map0 {
 227                                         trip = <&cpu_alert>;
 228                                         cooling-device =
 229                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 230                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 231                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 232                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 233                                 };
 234                         };
 235                 };
 236
 237                 gpu-thermal {
 238                         polling-delay-passive = <250>;
 239                         polling-delay = <2000>;
 240                         thermal-sensors = <&tmu 1>;
 241
 242                         trips {
 243                                 gpu_alert: gpu-alert {
 244                                         temperature = <80000>;
 245                                         hysteresis = <2000>;
 246                                         type = "passive";
 247                                 };
 248
 249                                 gpu-crit {
 250                                         temperature = <90000>;
 251                                         hysteresis = <2000>;
 252                                         type = "critical";
 253                                 };
 254                         };
 255
 256                         cooling-maps {
 257                                 map0 {
 258                                         trip = <&gpu_alert>;
 259                                         cooling-device =
 260                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 261                                 };
 262                         };
 263                 };
 264
 265                 vpu-thermal {
 266                         polling-delay-passive = <250>;
 267                         polling-delay = <2000>;
 268                         thermal-sensors = <&tmu 2>;
 269
 270                         trips {
 271                                 vpu-crit {
 272                                         temperature = <90000>;
 273                                         hysteresis = <2000>;
 274                                         type = "critical";
 275                                 };
 276                         };
 277                 };
 278         };
 279
 280         timer {
 281                 compatible = "arm,armv8-timer";
 282                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 283                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 284                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 285                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 286                 interrupt-parent = <&gic>;
 287                 arm,no-tick-in-suspend;
 288         };
 289
 290         soc@0 {
 291                 compatible = "simple-bus";
 292                 #address-cells = <1>;
 293                 #size-cells = <1>;
 294                 ranges = <0x0 0x0 0x0 0x3e000000>;
 295                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 296
 297                 bus@30000000 { /* AIPS1 */
 298                         compatible = "fsl,aips-bus", "simple-bus";
 299                         reg = <0x30000000 0x400000>;
 300                         #address-cells = <1>;
 301                         #size-cells = <1>;
 302                         ranges = <0x30000000 0x30000000 0x400000>;
 303
 304                         sai1: sai@30010000 {
 305                                 #sound-dai-cells = <0>;
 306                                 compatible = "fsl,imx8mq-sai";
 307                                 reg = <0x30010000 0x10000>;
 308                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 309                                 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
 310                                          <&clk IMX8MQ_CLK_SAI1_ROOT>,
 311                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 312                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 313                                 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
 314                                 dma-names = "rx", "tx";
 315                                 status = "disabled";
 316                         };
 317
 318                         sai6: sai@30030000 {
 319                                 #sound-dai-cells = <0>;
 320                                 compatible = "fsl,imx8mq-sai";
 321                                 reg = <0x30030000 0x10000>;
 322                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 323                                 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
 324                                          <&clk IMX8MQ_CLK_SAI6_ROOT>,
 325                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 326                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 327                                 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
 328                                 dma-names = "rx", "tx";
 329                                 status = "disabled";
 330                         };
 331
 332                         sai5: sai@30040000 {
 333                                 #sound-dai-cells = <0>;
 334                                 compatible = "fsl,imx8mq-sai";
 335                                 reg = <0x30040000 0x10000>;
 336                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 337                                 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
 338                                          <&clk IMX8MQ_CLK_SAI5_ROOT>,
 339                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 340                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 341                                 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
 342                                 dma-names = "rx", "tx";
 343                                 status = "disabled";
 344                         };
 345
 346                         sai4: sai@30050000 {
 347                                 #sound-dai-cells = <0>;
 348                                 compatible = "fsl,imx8mq-sai";
 349                                 reg = <0x30050000 0x10000>;
 350                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
 352                                          <&clk IMX8MQ_CLK_SAI4_ROOT>,
 353                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 354                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 355                                 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
 356                                 dma-names = "rx", "tx";
 357                                 status = "disabled";
 358                         };
 359
 360                         gpio1: gpio@30200000 {
 361                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 362                                 reg = <0x30200000 0x10000>;
 363                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 364                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 365                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 366                                 gpio-controller;
 367                                 #gpio-cells = <2>;
 368                                 interrupt-controller;
 369                                 #interrupt-cells = <2>;
 370                                 gpio-ranges = <&iomuxc 0 10 30>;
 371                         };
 372
 373                         gpio2: gpio@30210000 {
 374                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 375                                 reg = <0x30210000 0x10000>;
 376                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 377                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 379                                 gpio-controller;
 380                                 #gpio-cells = <2>;
 381                                 interrupt-controller;
 382                                 #interrupt-cells = <2>;
 383                                 gpio-ranges = <&iomuxc 0 40 21>;
 384                         };
 385
 386                         gpio3: gpio@30220000 {
 387                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 388                                 reg = <0x30220000 0x10000>;
 389                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 390                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 392                                 gpio-controller;
 393                                 #gpio-cells = <2>;
 394                                 interrupt-controller;
 395                                 #interrupt-cells = <2>;
 396                                 gpio-ranges = <&iomuxc 0 61 26>;
 397                         };
 398
 399                         gpio4: gpio@30230000 {
 400                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 401                                 reg = <0x30230000 0x10000>;
 402                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 403                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 404                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 405                                 gpio-controller;
 406                                 #gpio-cells = <2>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <2>;
 409                                 gpio-ranges = <&iomuxc 0 87 32>;
 410                         };
 411
 412                         gpio5: gpio@30240000 {
 413                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 414                                 reg = <0x30240000 0x10000>;
 415                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 416                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 417                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 418                                 gpio-controller;
 419                                 #gpio-cells = <2>;
 420                                 interrupt-controller;
 421                                 #interrupt-cells = <2>;
 422                                 gpio-ranges = <&iomuxc 0 119 30>;
 423                         };
 424
 425                         tmu: tmu@30260000 {
 426                                 compatible = "fsl,imx8mq-tmu";
 427                                 reg = <0x30260000 0x10000>;
 428                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 429                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 430                                 little-endian;
 431                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 432                                 fsl,tmu-calibration = <0x00000000 0x00000023
 433                                                        0x00000001 0x00000029
 434                                                        0x00000002 0x0000002f
 435                                                        0x00000003 0x00000035
 436                                                        0x00000004 0x0000003d
 437                                                        0x00000005 0x00000043
 438                                                        0x00000006 0x0000004b
 439                                                        0x00000007 0x00000051
 440                                                        0x00000008 0x00000057
 441                                                        0x00000009 0x0000005f
 442                                                        0x0000000a 0x00000067
 443                                                        0x0000000b 0x0000006f
 444
 445                                                        0x00010000 0x0000001b
 446                                                        0x00010001 0x00000023
 447                                                        0x00010002 0x0000002b
 448                                                        0x00010003 0x00000033
 449                                                        0x00010004 0x0000003b
 450                                                        0x00010005 0x00000043
 451                                                        0x00010006 0x0000004b
 452                                                        0x00010007 0x00000055
 453                                                        0x00010008 0x0000005d
 454                                                        0x00010009 0x00000067
 455                                                        0x0001000a 0x00000070
 456
 457                                                        0x00020000 0x00000017
 458                                                        0x00020001 0x00000023
 459                                                        0x00020002 0x0000002d
 460                                                        0x00020003 0x00000037
 461                                                        0x00020004 0x00000041
 462                                                        0x00020005 0x0000004b
 463                                                        0x00020006 0x00000057
 464                                                        0x00020007 0x00000063
 465                                                        0x00020008 0x0000006f
 466
 467                                                        0x00030000 0x00000015
 468                                                        0x00030001 0x00000021
 469                                                        0x00030002 0x0000002d
 470                                                        0x00030003 0x00000039
 471                                                        0x00030004 0x00000045
 472                                                        0x00030005 0x00000053
 473                                                        0x00030006 0x0000005f
 474                                                        0x00030007 0x00000071>;
 475                                 #thermal-sensor-cells =  <1>;
 476                         };
 477
 478                         wdog1: watchdog@30280000 {
 479                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 480                                 reg = <0x30280000 0x10000>;
 481                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 483                                 status = "disabled";
 484                         };
 485
 486                         wdog2: watchdog@30290000 {
 487                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 488                                 reg = <0x30290000 0x10000>;
 489                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 490                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 491                                 status = "disabled";
 492                         };
 493
 494                         wdog3: watchdog@302a0000 {
 495                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 496                                 reg = <0x302a0000 0x10000>;
 497                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 498                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 499                                 status = "disabled";
 500                         };
 501
 502                         sdma2: sdma@302c0000 {
 503                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 504                                 reg = <0x302c0000 0x10000>;
 505                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 506                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 507                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 508                                 clock-names = "ipg", "ahb";
 509                                 #dma-cells = <3>;
 510                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 511                         };
 512
 513                         lcdif: lcd-controller@30320000 {
 514                                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 515                                 reg = <0x30320000 0x10000>;
 516                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 518                                 clock-names = "pix";
 519                                 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
 520                                                   <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
 521                                                   <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
 522                                                   <&clk IMX8MQ_VIDEO_PLL1>;
 523                                 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
 524                                                   <&clk IMX8MQ_VIDEO_PLL1>,
 525                                                   <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 526                                 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
 527                                 status = "disabled";
 528
 529                                 port@0 {
 530                                         lcdif_mipi_dsi: endpoint {
 531                                                 remote-endpoint = <&mipi_dsi_lcdif_in>;
 532                                         };
 533                                 };
 534                         };
 535
 536                         iomuxc: pinctrl@30330000 {
 537                                 compatible = "fsl,imx8mq-iomuxc";
 538                                 reg = <0x30330000 0x10000>;
 539                         };
 540
 541                         iomuxc_gpr: syscon@30340000 {
 542                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 543                                              "syscon", "simple-mfd";
 544                                 reg = <0x30340000 0x10000>;
 545
 546                                 mux: mux-controller {
 547                                         compatible = "mmio-mux";
 548                                         #mux-control-cells = <1>;
 549                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 550                                 };
 551                         };
 552
 553                         ocotp: efuse@30350000 {
 554                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 555                                 reg = <0x30350000 0x10000>;
 556                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 557                                 #address-cells = <1>;
 558                                 #size-cells = <1>;
 559
 560                                 cpu_speed_grade: speed-grade@10 {
 561                                         reg = <0x10 4>;
 562                                 };
 563                         };
 564
 565                         anatop: syscon@30360000 {
 566                                 compatible = "fsl,imx8mq-anatop", "syscon";
 567                                 reg = <0x30360000 0x10000>;
 568                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 569                         };
 570
 571                         snvs: snvs@30370000 {
 572                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 573                                 reg = <0x30370000 0x10000>;
 574
 575                                 snvs_rtc: snvs-rtc-lp{
 576                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 577                                         regmap =<&snvs>;
 578                                         offset = <0x34>;
 579                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 580                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 581                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 582                                         clock-names = "snvs-rtc";
 583                                 };
 584
 585                                 snvs_pwrkey: snvs-powerkey {
 586                                         compatible = "fsl,sec-v4.0-pwrkey";
 587                                         regmap = <&snvs>;
 588                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 589                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 590                                         clock-names = "snvs-pwrkey";
 591                                         linux,keycode = <KEY_POWER>;
 592                                         wakeup-source;
 593                                         status = "disabled";
 594                                 };
 595                         };
 596
 597                         clk: clock-controller@30380000 {
 598                                 compatible = "fsl,imx8mq-ccm";
 599                                 reg = <0x30380000 0x10000>;
 600                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 601                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 602                                 #clock-cells = <1>;
 603                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 604                                          <&clk_ext1>, <&clk_ext2>,
 605                                          <&clk_ext3>, <&clk_ext4>;
 606                                 clock-names = "ckil", "osc_25m", "osc_27m",
 607                                               "clk_ext1", "clk_ext2",
 608                                               "clk_ext3", "clk_ext4";
 609                                 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
 610                                                   <&clk IMX8MQ_CLK_A53_CORE>,
 611                                                   <&clk IMX8MQ_CLK_NOC>,
 612                                                   <&clk IMX8MQ_CLK_AUDIO_AHB>,
 613                                                   <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
 614                                                   <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
 615                                                   <&clk IMX8MQ_AUDIO_PLL1>,
 616                                                   <&clk IMX8MQ_AUDIO_PLL2>;
 617                                 assigned-clock-rates = <0>, <0>,
 618                                                        <800000000>,
 619                                                        <0>,
 620                                                        <0>,
 621                                                        <0>,
 622                                                        <786432000>,
 623                                                        <722534400>;
 624                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
 625                                                          <&clk IMX8MQ_ARM_PLL_OUT>,
 626                                                          <0>,
 627                                                          <&clk IMX8MQ_SYS2_PLL_500M>,
 628                                                          <&clk IMX8MQ_AUDIO_PLL1>,
 629                                                          <&clk IMX8MQ_AUDIO_PLL2>;
 630                         };
 631
 632                         src: reset-controller@30390000 {
 633                                 compatible = "fsl,imx8mq-src", "syscon";
 634                                 reg = <0x30390000 0x10000>;
 635                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 636                                 #reset-cells = <1>;
 637                         };
 638
 639                         gpc: gpc@303a0000 {
 640                                 compatible = "fsl,imx8mq-gpc";
 641                                 reg = <0x303a0000 0x10000>;
 642                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 643                                 interrupt-parent = <&gic>;
 644                                 interrupt-controller;
 645                                 #interrupt-cells = <3>;
 646
 647                                 pgc {
 648                                         #address-cells = <1>;
 649                                         #size-cells = <0>;
 650
 651                                         pgc_mipi: power-domain@0 {
 652                                                 #power-domain-cells = <0>;
 653                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 654                                         };
 655
 656                                         /*
 657                                          * As per comment in ATF source code:
 658                                          *
 659                                          * PCIE1 and PCIE2 share the
 660                                          * same reset signal, if we
 661                                          * power down PCIE2, PCIE1
 662                                          * will be held in reset too.
 663                                          *
 664                                          * So instead of creating two
 665                                          * separate power domains for
 666                                          * PCIE1 and PCIE2 we create a
 667                                          * link between both and use
 668                                          * it as a shared PCIE power
 669                                          * domain.
 670                                          */
 671                                         pgc_pcie: power-domain@1 {
 672                                                 #power-domain-cells = <0>;
 673                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 674                                                 power-domains = <&pgc_pcie2>;
 675                                         };
 676
 677                                         pgc_otg1: power-domain@2 {
 678                                                 #power-domain-cells = <0>;
 679                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 680                                         };
 681
 682                                         pgc_otg2: power-domain@3 {
 683                                                 #power-domain-cells = <0>;
 684                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 685                                         };
 686
 687                                         pgc_ddr1: power-domain@4 {
 688                                                 #power-domain-cells = <0>;
 689                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 690                                         };
 691
 692                                         pgc_gpu: power-domain@5 {
 693                                                 #power-domain-cells = <0>;
 694                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 695                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 696                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 697                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 698                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 699                                         };
 700
 701                                         pgc_vpu: power-domain@6 {
 702                                                 #power-domain-cells = <0>;
 703                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 704                                                 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
 705                                         };
 706
 707                                         pgc_disp: power-domain@7 {
 708                                                 #power-domain-cells = <0>;
 709                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 710                                         };
 711
 712                                         pgc_mipi_csi1: power-domain@8 {
 713                                                 #power-domain-cells = <0>;
 714                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 715                                         };
 716
 717                                         pgc_mipi_csi2: power-domain@9 {
 718                                                 #power-domain-cells = <0>;
 719                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 720                                         };
 721
 722                                         pgc_pcie2: power-domain@a {
 723                                                 #power-domain-cells = <0>;
 724                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 725                                         };
 726                                 };
 727                         };
 728                 };
 729
 730                 bus@30400000 { /* AIPS2 */
 731                         compatible = "fsl,aips-bus", "simple-bus";
 732                         reg = <0x30400000 0x400000>;
 733                         #address-cells = <1>;
 734                         #size-cells = <1>;
 735                         ranges = <0x30400000 0x30400000 0x400000>;
 736
 737                         pwm1: pwm@30660000 {
 738                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 739                                 reg = <0x30660000 0x10000>;
 740                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 741                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 742                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 743                                 clock-names = "ipg", "per";
 744                                 #pwm-cells = <2>;
 745                                 status = "disabled";
 746                         };
 747
 748                         pwm2: pwm@30670000 {
 749                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 750                                 reg = <0x30670000 0x10000>;
 751                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 753                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 754                                 clock-names = "ipg", "per";
 755                                 #pwm-cells = <2>;
 756                                 status = "disabled";
 757                         };
 758
 759                         pwm3: pwm@30680000 {
 760                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 761                                 reg = <0x30680000 0x10000>;
 762                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 764                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 765                                 clock-names = "ipg", "per";
 766                                 #pwm-cells = <2>;
 767                                 status = "disabled";
 768                         };
 769
 770                         pwm4: pwm@30690000 {
 771                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 772                                 reg = <0x30690000 0x10000>;
 773                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 774                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 775                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 776                                 clock-names = "ipg", "per";
 777                                 #pwm-cells = <2>;
 778                                 status = "disabled";
 779                         };
 780
 781                         system_counter: timer@306a0000 {
 782                                 compatible = "nxp,sysctr-timer";
 783                                 reg = <0x306a0000 0x20000>;
 784                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 785                                 clocks = <&osc_25m>;
 786                                 clock-names = "per";
 787                         };
 788                 };
 789
 790                 bus@30800000 { /* AIPS3 */
 791                         compatible = "fsl,aips-bus", "simple-bus";
 792                         reg = <0x30800000 0x400000>;
 793                         #address-cells = <1>;
 794                         #size-cells = <1>;
 795                         ranges = <0x30800000 0x30800000 0x400000>,
 796                                  <0x08000000 0x08000000 0x10000000>;
 797
 798                         spdif1: spdif@30810000 {
 799                                 compatible = "fsl,imx35-spdif";
 800                                 reg = <0x30810000 0x10000>;
 801                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
 803                                         <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
 804                                         <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
 805                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
 806                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
 807                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
 808                                         <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
 809                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
 810                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
 811                                         <&clk IMX8MQ_CLK_DUMMY>; /* spba */
 812                                 clock-names = "core", "rxtx0",
 813                                               "rxtx1", "rxtx2",
 814                                               "rxtx3", "rxtx4",
 815                                               "rxtx5", "rxtx6",
 816                                               "rxtx7", "spba";
 817                                 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
 818                                 dma-names = "rx", "tx";
 819                                 status = "disabled";
 820                         };
 821
 822                         ecspi1: spi@30820000 {
 823                                 #address-cells = <1>;
 824                                 #size-cells = <0>;
 825                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 826                                 reg = <0x30820000 0x10000>;
 827                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 829                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 830                                 clock-names = "ipg", "per";
 831                                 status = "disabled";
 832                         };
 833
 834                         ecspi2: spi@30830000 {
 835                                 #address-cells = <1>;
 836                                 #size-cells = <0>;
 837                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 838                                 reg = <0x30830000 0x10000>;
 839                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 841                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 842                                 clock-names = "ipg", "per";
 843                                 status = "disabled";
 844                         };
 845
 846                         ecspi3: spi@30840000 {
 847                                 #address-cells = <1>;
 848                                 #size-cells = <0>;
 849                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 850                                 reg = <0x30840000 0x10000>;
 851                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 853                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 854                                 clock-names = "ipg", "per";
 855                                 status = "disabled";
 856                         };
 857
 858                         uart1: serial@30860000 {
 859                                 compatible = "fsl,imx8mq-uart",
 860                                              "fsl,imx6q-uart";
 861                                 reg = <0x30860000 0x10000>;
 862                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 863                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 864                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 865                                 clock-names = "ipg", "per";
 866                                 status = "disabled";
 867                         };
 868
 869                         uart3: serial@30880000 {
 870                                 compatible = "fsl,imx8mq-uart",
 871                                              "fsl,imx6q-uart";
 872                                 reg = <0x30880000 0x10000>;
 873                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 874                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 875                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 876                                 clock-names = "ipg", "per";
 877                                 status = "disabled";
 878                         };
 879
 880                         uart2: serial@30890000 {
 881                                 compatible = "fsl,imx8mq-uart",
 882                                              "fsl,imx6q-uart";
 883                                 reg = <0x30890000 0x10000>;
 884                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 885                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 886                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 887                                 clock-names = "ipg", "per";
 888                                 status = "disabled";
 889                         };
 890
 891                         spdif2: spdif@308a0000 {
 892                                 compatible = "fsl,imx35-spdif";
 893                                 reg = <0x308a0000 0x10000>;
 894                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 895                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
 896                                         <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
 897                                         <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
 898                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
 899                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
 900                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
 901                                         <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
 902                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
 903                                         <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
 904                                         <&clk IMX8MQ_CLK_DUMMY>; /* spba */
 905                                 clock-names = "core", "rxtx0",
 906                                               "rxtx1", "rxtx2",
 907                                               "rxtx3", "rxtx4",
 908                                               "rxtx5", "rxtx6",
 909                                               "rxtx7", "spba";
 910                                 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
 911                                 dma-names = "rx", "tx";
 912                                 status = "disabled";
 913                         };
 914
 915                         sai2: sai@308b0000 {
 916                                 #sound-dai-cells = <0>;
 917                                 compatible = "fsl,imx8mq-sai";
 918                                 reg = <0x308b0000 0x10000>;
 919                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 920                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 921                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 922                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 923                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 924                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 925                                 dma-names = "rx", "tx";
 926                                 status = "disabled";
 927                         };
 928
 929                         sai3: sai@308c0000 {
 930                                 #sound-dai-cells = <0>;
 931                                 compatible = "fsl,imx8mq-sai";
 932                                 reg = <0x308c0000 0x10000>;
 933                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 934                                 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
 935                                          <&clk IMX8MQ_CLK_SAI3_ROOT>,
 936                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 937                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 938                                 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
 939                                 dma-names = "rx", "tx";
 940                                 status = "disabled";
 941                         };
 942
 943                         crypto: crypto@30900000 {
 944                                 compatible = "fsl,sec-v4.0";
 945                                 #address-cells = <1>;
 946                                 #size-cells = <1>;
 947                                 reg = <0x30900000 0x40000>;
 948                                 ranges = <0 0x30900000 0x40000>;
 949                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clk IMX8MQ_CLK_AHB>,
 951                                          <&clk IMX8MQ_CLK_IPG_ROOT>;
 952                                 clock-names = "aclk", "ipg";
 953
 954                                 sec_jr0: jr@1000 {
 955                                         compatible = "fsl,sec-v4.0-job-ring";
 956                                         reg = <0x1000 0x1000>;
 957                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 958                                 };
 959
 960                                 sec_jr1: jr@2000 {
 961                                         compatible = "fsl,sec-v4.0-job-ring";
 962                                         reg = <0x2000 0x1000>;
 963                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 964                                 };
 965
 966                                 sec_jr2: jr@3000 {
 967                                         compatible = "fsl,sec-v4.0-job-ring";
 968                                         reg = <0x3000 0x1000>;
 969                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 970                                 };
 971                         };
 972
 973                         mipi_dsi: mipi-dsi@30a00000 {
 974                                 compatible = "fsl,imx8mq-nwl-dsi";
 975                                 reg = <0x30a00000 0x300>;
 976                                 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
 977                                          <&clk IMX8MQ_CLK_DSI_AHB>,
 978                                          <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
 979                                          <&clk IMX8MQ_CLK_DSI_PHY_REF>,
 980                                          <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 981                                 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
 982                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
 983                                                   <&clk IMX8MQ_CLK_DSI_CORE>,
 984                                                   <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
 985                                 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
 986                                                          <&clk IMX8MQ_SYS1_PLL_266M>;
 987                                 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
 988                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 989                                 mux-controls = <&mux 0>;
 990                                 power-domains = <&pgc_mipi>;
 991                                 phys = <&dphy>;
 992                                 phy-names = "dphy";
 993                                 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
 994                                          <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
 995                                          <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
 996                                          <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
 997                                 reset-names = "byte", "dpi", "esc", "pclk";
 998                                 status = "disabled";
 999
1000                                 ports {
1001                                         #address-cells = <1>;
1002                                         #size-cells = <0>;
1003
1004                                         port@0 {
1005                                                 reg = <0>;
1006                                                 #address-cells = <1>;
1007                                                 #size-cells = <0>;
1008                                                 mipi_dsi_lcdif_in: endpoint@0 {
1009                                                         reg = <0>;
1010                                                         remote-endpoint = <&lcdif_mipi_dsi>;
1011                                                 };
1012                                         };
1013                                 };
1014                         };
1015
1016                         dphy: dphy@30a00300 {
1017                                 compatible = "fsl,imx8mq-mipi-dphy";
1018                                 reg = <0x30a00300 0x100>;
1019                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1020                                 clock-names = "phy_ref";
1021                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1022                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1023                                 assigned-clock-rates = <24000000>;
1024                                 #phy-cells = <0>;
1025                                 power-domains = <&pgc_mipi>;
1026                                 status = "disabled";
1027                         };
1028
1029                         i2c1: i2c@30a20000 {
1030                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1031                                 reg = <0x30a20000 0x10000>;
1032                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1033                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036                                 status = "disabled";
1037                         };
1038
1039                         i2c2: i2c@30a30000 {
1040                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1041                                 reg = <0x30a30000 0x10000>;
1042                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1043                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 status = "disabled";
1047                         };
1048
1049                         i2c3: i2c@30a40000 {
1050                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1051                                 reg = <0x30a40000 0x10000>;
1052                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1053                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1054                                 #address-cells = <1>;
1055                                 #size-cells = <0>;
1056                                 status = "disabled";
1057                         };
1058
1059                         i2c4: i2c@30a50000 {
1060                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1061                                 reg = <0x30a50000 0x10000>;
1062                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1063                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1064                                 #address-cells = <1>;
1065                                 #size-cells = <0>;
1066                                 status = "disabled";
1067                         };
1068
1069                         uart4: serial@30a60000 {
1070                                 compatible = "fsl,imx8mq-uart",
1071                                              "fsl,imx6q-uart";
1072                                 reg = <0x30a60000 0x10000>;
1073                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1074                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1075                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
1076                                 clock-names = "ipg", "per";
1077                                 status = "disabled";
1078                         };
1079
1080                         mu: mailbox@30aa0000 {
1081                                 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1082                                 reg = <0x30aa0000 0x10000>;
1083                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1084                                 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1085                                 #mbox-cells = <2>;
1086                         };
1087
1088                         usdhc1: mmc@30b40000 {
1089                                 compatible = "fsl,imx8mq-usdhc",
1090                                              "fsl,imx7d-usdhc";
1091                                 reg = <0x30b40000 0x10000>;
1092                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1093                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1094                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1095                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1096                                 clock-names = "ipg", "ahb", "per";
1097                                 fsl,tuning-start-tap = <20>;
1098                                 fsl,tuning-step = <2>;
1099                                 bus-width = <4>;
1100                                 status = "disabled";
1101                         };
1102
1103                         usdhc2: mmc@30b50000 {
1104                                 compatible = "fsl,imx8mq-usdhc",
1105                                              "fsl,imx7d-usdhc";
1106                                 reg = <0x30b50000 0x10000>;
1107                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1108                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1109                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1110                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1111                                 clock-names = "ipg", "ahb", "per";
1112                                 fsl,tuning-start-tap = <20>;
1113                                 fsl,tuning-step = <2>;
1114                                 bus-width = <4>;
1115                                 status = "disabled";
1116                         };
1117
1118                         qspi0: spi@30bb0000 {
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1122                                 reg = <0x30bb0000 0x10000>,
1123                                       <0x08000000 0x10000000>;
1124                                 reg-names = "QuadSPI", "QuadSPI-memory";
1125                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1126                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1127                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
1128                                 clock-names = "qspi_en", "qspi";
1129                                 status = "disabled";
1130                         };
1131
1132                         sdma1: sdma@30bd0000 {
1133                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1134                                 reg = <0x30bd0000 0x10000>;
1135                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1136                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1137                                          <&clk IMX8MQ_CLK_AHB>;
1138                                 clock-names = "ipg", "ahb";
1139                                 #dma-cells = <3>;
1140                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1141                         };
1142
1143                         fec1: ethernet@30be0000 {
1144                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1145                                 reg = <0x30be0000 0x10000>;
1146                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1147                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1148                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1149                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1150                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1151                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
1152                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
1153                                          <&clk IMX8MQ_CLK_ENET_REF>,
1154                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1155                                 clock-names = "ipg", "ahb", "ptp",
1156                                               "enet_clk_ref", "enet_out";
1157                                 fsl,num-tx-queues = <3>;
1158                                 fsl,num-rx-queues = <3>;
1159                                 status = "disabled";
1160                         };
1161                 };
1162
1163                 bus@32c00000 { /* AIPS4 */
1164                         compatible = "fsl,aips-bus", "simple-bus";
1165                         reg = <0x32c00000 0x400000>;
1166                         #address-cells = <1>;
1167                         #size-cells = <1>;
1168                         ranges = <0x32c00000 0x32c00000 0x400000>;
1169
1170                         irqsteer: interrupt-controller@32e2d000 {
1171                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1172                                 reg = <0x32e2d000 0x1000>;
1173                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1174                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1175                                 clock-names = "ipg";
1176                                 fsl,channel = <0>;
1177                                 fsl,num-irqs = <64>;
1178                                 interrupt-controller;
1179                                 #interrupt-cells = <1>;
1180                         };
1181                 };
1182
1183                 gpu: gpu@38000000 {
1184                         compatible = "vivante,gc";
1185                         reg = <0x38000000 0x40000>;
1186                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1187                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1188                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1189                                  <&clk IMX8MQ_CLK_GPU_AXI>,
1190                                  <&clk IMX8MQ_CLK_GPU_AHB>;
1191                         clock-names = "core", "shader", "bus", "reg";
1192                         #cooling-cells = <2>;
1193                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1194                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1195                                           <&clk IMX8MQ_CLK_GPU_AXI>,
1196                                           <&clk IMX8MQ_CLK_GPU_AHB>,
1197                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
1198                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1199                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1200                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1201                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1202                                                  <&clk IMX8MQ_GPU_PLL>;
1203                         assigned-clock-rates = <800000000>, <800000000>,
1204                                                <800000000>, <800000000>, <0>;
1205                         power-domains = <&pgc_gpu>;
1206                 };
1207
1208                 usb_dwc3_0: usb@38100000 {
1209                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1210                         reg = <0x38100000 0x10000>;
1211                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1212                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1213                                  <&clk IMX8MQ_CLK_32K>;
1214                         clock-names = "bus_early", "ref", "suspend";
1215                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1216                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1217                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1218                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1219                         assigned-clock-rates = <500000000>, <100000000>;
1220                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1221                         phys = <&usb3_phy0>, <&usb3_phy0>;
1222                         phy-names = "usb2-phy", "usb3-phy";
1223                         power-domains = <&pgc_otg1>;
1224                         usb3-resume-missing-cas;
1225                         status = "disabled";
1226                 };
1227
1228                 usb3_phy0: usb-phy@381f0040 {
1229                         compatible = "fsl,imx8mq-usb-phy";
1230                         reg = <0x381f0040 0x40>;
1231                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1232                         clock-names = "phy";
1233                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1234                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1235                         assigned-clock-rates = <100000000>;
1236                         #phy-cells = <0>;
1237                         status = "disabled";
1238                 };
1239
1240                 usb_dwc3_1: usb@38200000 {
1241                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1242                         reg = <0x38200000 0x10000>;
1243                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1244                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1245                                  <&clk IMX8MQ_CLK_32K>;
1246                         clock-names = "bus_early", "ref", "suspend";
1247                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1248                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1249                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1250                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1251                         assigned-clock-rates = <500000000>, <100000000>;
1252                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1253                         phys = <&usb3_phy1>, <&usb3_phy1>;
1254                         phy-names = "usb2-phy", "usb3-phy";
1255                         power-domains = <&pgc_otg2>;
1256                         usb3-resume-missing-cas;
1257                         status = "disabled";
1258                 };
1259
1260                 usb3_phy1: usb-phy@382f0040 {
1261                         compatible = "fsl,imx8mq-usb-phy";
1262                         reg = <0x382f0040 0x40>;
1263                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1264                         clock-names = "phy";
1265                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1266                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1267                         assigned-clock-rates = <100000000>;
1268                         #phy-cells = <0>;
1269                         status = "disabled";
1270                 };
1271
1272                 vpu: video-codec@38300000 {
1273                         compatible = "nxp,imx8mq-vpu";
1274                         reg = <0x38300000 0x10000>,
1275                               <0x38310000 0x10000>,
1276                               <0x38320000 0x10000>;
1277                         reg-names = "g1", "g2", "ctrl";
1278                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1279                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1280                         interrupt-names = "g1", "g2";
1281                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1282                                  <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1283                                  <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1284                         clock-names = "g1", "g2", "bus";
1285                         assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1286                                           <&clk IMX8MQ_CLK_VPU_G2>,
1287                                           <&clk IMX8MQ_CLK_VPU_BUS>,
1288                                           <&clk IMX8MQ_VPU_PLL_BYPASS>;
1289                         assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1290                                                  <&clk IMX8MQ_VPU_PLL_OUT>,
1291                                                  <&clk IMX8MQ_SYS1_PLL_800M>,
1292                                                  <&clk IMX8MQ_VPU_PLL>;
1293                         assigned-clock-rates = <600000000>, <600000000>,
1294                                                <800000000>, <0>;
1295                         power-domains = <&pgc_vpu>;
1296                 };
1297
1298                 pcie0: pcie@33800000 {
1299                         compatible = "fsl,imx8mq-pcie";
1300                         reg = <0x33800000 0x400000>,
1301                               <0x1ff00000 0x80000>;
1302                         reg-names = "dbi", "config";
1303                         #address-cells = <3>;
1304                         #size-cells = <2>;
1305                         device_type = "pci";
1306                         bus-range = <0x00 0xff>;
1307                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1308                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1309                         num-lanes = <1>;
1310                         num-viewport = <4>;
1311                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1312                         interrupt-names = "msi";
1313                         #interrupt-cells = <1>;
1314                         interrupt-map-mask = <0 0 0 0x7>;
1315                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1316                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1317                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1318                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1319                         fsl,max-link-speed = <2>;
1320                         power-domains = <&pgc_pcie>;
1321                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1322                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1323                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1324                         reset-names = "pciephy", "apps", "turnoff";
1325                         status = "disabled";
1326                 };
1327
1328                 pcie1: pcie@33c00000 {
1329                         compatible = "fsl,imx8mq-pcie";
1330                         reg = <0x33c00000 0x400000>,
1331                               <0x27f00000 0x80000>;
1332                         reg-names = "dbi", "config";
1333                         #address-cells = <3>;
1334                         #size-cells = <2>;
1335                         device_type = "pci";
1336                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1337                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1338                         num-lanes = <1>;
1339                         num-viewport = <4>;
1340                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1341                         interrupt-names = "msi";
1342                         #interrupt-cells = <1>;
1343                         interrupt-map-mask = <0 0 0 0x7>;
1344                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1345                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1346                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1347                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1348                         fsl,max-link-speed = <2>;
1349                         power-domains = <&pgc_pcie>;
1350                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1351                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1352                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1353                         reset-names = "pciephy", "apps", "turnoff";
1354                         status = "disabled";
1355                 };
1356
1357                 gic: interrupt-controller@38800000 {
1358                         compatible = "arm,gic-v3";
1359                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1360                               <0x38880000 0xc0000>,     /* GICR */
1361                               <0x31000000 0x2000>,      /* GICC */
1362                               <0x31010000 0x2000>,      /* GICV */
1363                               <0x31020000 0x2000>;      /* GICH */
1364                         #interrupt-cells = <3>;
1365                         interrupt-controller;
1366                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1367                         interrupt-parent = <&gic>;
1368                 };
1369
1370                 ddrc: memory-controller@3d400000 {
1371                         compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1372                         reg = <0x3d400000 0x400000>;
1373                         clock-names = "core", "pll", "alt", "apb";
1374                         clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1375                                  <&clk IMX8MQ_DRAM_PLL_OUT>,
1376                                  <&clk IMX8MQ_CLK_DRAM_ALT>,
1377                                  <&clk IMX8MQ_CLK_DRAM_APB>;
1378                 };
1379
1380                 ddr-pmu@3d800000 {
1381                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1382                         reg = <0x3d800000 0x400000>;
1383                         interrupt-parent = <&gic>;
1384                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1385                 };
1386         };
1387 };