1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 model = "Google i.MX8MQ Phanbell";
12 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
19 device_type = "memory";
20 reg = <0x00000000 0x40000000 0 0x40000000>;
23 pmic_osc: clock-pmic {
24 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 clock-output-names = "pmic_osc";
30 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
31 compatible = "regulator-fixed";
32 regulator-name = "VSD_3V3";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 cpu-supply = <&buck2>;
45 cpu-supply = <&buck2>;
49 cpu-supply = <&buck2>;
53 cpu-supply = <&buck2>;
57 clock-frequency = <400000>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_i2c1>;
63 compatible = "rohm,bd71837";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_pmic>;
69 clock-output-names = "pmic_clk";
70 interrupt-parent = <&gpio1>;
71 interrupts = <3 GPIO_ACTIVE_LOW>;
75 regulator-name = "buck1";
76 regulator-min-microvolt = <700000>;
77 regulator-max-microvolt = <1300000>;
80 regulator-ramp-delay = <1250>;
81 rohm,dvs-run-voltage = <900000>;
82 rohm,dvs-idle-voltage = <900000>;
83 rohm,dvs-suspend-voltage = <800000>;
87 regulator-name = "buck2";
88 regulator-min-microvolt = <850000>;
89 regulator-max-microvolt = <1000000>;
92 rohm,dvs-run-voltage = <1000000>;
93 rohm,dvs-idle-voltage = <900000>;
97 regulator-name = "buck3";
98 regulator-min-microvolt = <700000>;
99 regulator-max-microvolt = <1300000>;
101 rohm,dvs-run-voltage = <900000>;
105 regulator-name = "buck4";
106 regulator-min-microvolt = <700000>;
107 regulator-max-microvolt = <1300000>;
110 rohm,dvs-run-voltage = <900000>;
114 regulator-name = "buck5";
115 regulator-min-microvolt = <700000>;
116 regulator-max-microvolt = <1350000>;
122 regulator-name = "buck6";
123 regulator-min-microvolt = <3000000>;
124 regulator-max-microvolt = <3300000>;
130 regulator-name = "buck7";
131 regulator-min-microvolt = <1605000>;
132 regulator-max-microvolt = <1995000>;
138 regulator-name = "buck8";
139 regulator-min-microvolt = <800000>;
140 regulator-max-microvolt = <1400000>;
146 regulator-name = "ldo1";
147 regulator-min-microvolt = <3000000>;
148 regulator-max-microvolt = <3300000>;
154 regulator-name = "ldo2";
155 regulator-min-microvolt = <900000>;
156 regulator-max-microvolt = <900000>;
162 regulator-name = "ldo3";
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
170 regulator-name = "ldo4";
171 regulator-min-microvolt = <900000>;
172 regulator-max-microvolt = <1800000>;
178 regulator-name = "ldo5";
179 regulator-min-microvolt = <1800000>;
180 regulator-max-microvolt = <3300000>;
186 regulator-name = "ldo6";
187 regulator-min-microvolt = <900000>;
188 regulator-max-microvolt = <1800000>;
194 regulator-name = "ldo7";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3300000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_fec1>;
207 phy-mode = "rgmii-id";
208 phy-handle = <ðphy0>;
209 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
210 phy-reset-duration = <10>;
211 phy-reset-post-delay = <50>;
216 #address-cells = <1>;
218 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet-phy-ieee802.3-c22";
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>;
232 pinctrl-names = "default", "state_100mhz", "state_200mhz";
233 pinctrl-0 = <&pinctrl_usdhc1>;
234 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
235 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
242 pinctrl-names = "default", "state_100mhz", "state_200mhz";
243 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
244 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
245 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
247 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
248 vmmc-supply = <®_usdhc2_vmmc>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_wdog>;
273 fsl,ext-reset-output;
278 pinctrl_fec1: fec1grp {
280 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
281 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
282 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
283 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
284 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
285 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
286 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
287 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
288 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
289 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
290 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
291 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
292 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
293 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
294 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
298 pinctrl_i2c1: i2c1grp {
300 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
301 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
305 pinctrl_pmic: pmicirq {
307 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
311 pinctrl_uart1: uart1grp {
313 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
314 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
318 pinctrl_usdhc1: usdhc1grp {
320 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
321 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
322 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
323 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
324 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
325 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
326 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
327 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
328 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
329 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
330 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
331 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
335 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
337 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
338 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
339 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
340 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
341 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
342 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
343 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
344 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
345 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
346 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
347 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
348 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
352 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
354 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
355 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
356 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
357 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
358 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
359 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
360 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
361 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
362 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
363 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
364 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
365 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
369 pinctrl_usdhc2_gpio: usdhc2grpgpio {
371 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
372 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
376 pinctrl_usdhc2: usdhc2grp {
378 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
379 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
380 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
381 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
382 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
383 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
384 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
388 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
390 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
391 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
392 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
393 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
394 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
395 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
396 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
400 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
402 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
403 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
404 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
405 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
406 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
407 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
408 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
412 pinctrl_wdog: wdoggrp {
414 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6