arch/arm/dts/imx8mn.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mn-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 #include "imx8mn-pinfunc.h"
  12
  13 / {
  14         compatible = "fsl,imx8mn";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec1;
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 mmc0 = &usdhc1;
  31                 mmc1 = &usdhc2;
  32                 mmc2 = &usdhc3;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 spi0 = &ecspi1;
  38                 spi1 = &ecspi2;
  39                 spi2 = &ecspi3;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 A53_0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x0>;
  50                         clock-latency = <61036>;
  51                         clocks = <&clk IMX8MN_CLK_ARM>;
  52                         enable-method = "psci";
  53                         next-level-cache = <&A53_L2>;
  54                 };
  55
  56                 A53_1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53";
  59                         reg = <0x1>;
  60                         clock-latency = <61036>;
  61                         clocks = <&clk IMX8MN_CLK_ARM>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&A53_L2>;
  64                 };
  65
  66                 A53_2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a53";
  69                         reg = <0x2>;
  70                         clock-latency = <61036>;
  71                         clocks = <&clk IMX8MN_CLK_ARM>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&A53_L2>;
  74                 };
  75
  76                 A53_3: cpu@3 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53";
  79                         reg = <0x3>;
  80                         clock-latency = <61036>;
  81                         clocks = <&clk IMX8MN_CLK_ARM>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&A53_L2>;
  84                 };
  85
  86                 A53_L2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         memory@40000000 {
  92                 device_type = "memory";
  93                 reg = <0x0 0x40000000 0 0x80000000>;
  94         };
  95
  96         osc_32k: clock-osc-32k {
  97                 compatible = "fixed-clock";
  98                 #clock-cells = <0>;
  99                 clock-frequency = <32768>;
 100                 clock-output-names = "osc_32k";
 101         };
 102
 103         osc_24m: clock-osc-24m {
 104                 compatible = "fixed-clock";
 105                 #clock-cells = <0>;
 106                 clock-frequency = <24000000>;
 107                 clock-output-names = "osc_24m";
 108         };
 109
 110         clk_ext1: clock-ext1 {
 111                 compatible = "fixed-clock";
 112                 #clock-cells = <0>;
 113                 clock-frequency = <133000000>;
 114                 clock-output-names = "clk_ext1";
 115         };
 116
 117         clk_ext2: clock-ext2 {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <133000000>;
 121                 clock-output-names = "clk_ext2";
 122         };
 123
 124         clk_ext3: clock-ext3 {
 125                 compatible = "fixed-clock";
 126                 #clock-cells = <0>;
 127                 clock-frequency = <133000000>;
 128                 clock-output-names = "clk_ext3";
 129         };
 130
 131         clk_ext4: clock-ext4 {
 132                 compatible = "fixed-clock";
 133                 #clock-cells = <0>;
 134                 clock-frequency= <133000000>;
 135                 clock-output-names = "clk_ext4";
 136         };
 137
 138         psci {
 139                 compatible = "arm,psci-1.0";
 140                 method = "smc";
 141         };
 142
 143         timer {
 144                 compatible = "arm,armv8-timer";
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 149                 clock-frequency = <8000000>;
 150                 arm,no-tick-in-suspend;
 151         };
 152
 153         soc@0 {
 154                 compatible = "simple-bus";
 155                 #address-cells = <1>;
 156                 #size-cells = <1>;
 157                 ranges = <0x0 0x0 0x0 0x3e000000>;
 158
 159                 aips1: bus@30000000 {
 160                         compatible = "fsl,aips-bus", "simple-bus";
 161                         reg = <0x30000000 0x400000>;
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         ranges;
 165
 166                         gpio1: gpio@30200000 {
 167                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 168                                 reg = <0x30200000 0x10000>;
 169                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 170                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 171                                 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 interrupt-controller;
 175                                 #interrupt-cells = <2>;
 176                         };
 177
 178                         gpio2: gpio@30210000 {
 179                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 180                                 reg = <0x30210000 0x10000>;
 181                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 182                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 183                                 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
 184                                 gpio-controller;
 185                                 #gpio-cells = <2>;
 186                                 interrupt-controller;
 187                                 #interrupt-cells = <2>;
 188                         };
 189
 190                         gpio3: gpio@30220000 {
 191                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 192                                 reg = <0x30220000 0x10000>;
 193                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 194                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 195                                 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
 196                                 gpio-controller;
 197                                 #gpio-cells = <2>;
 198                                 interrupt-controller;
 199                                 #interrupt-cells = <2>;
 200                         };
 201
 202                         gpio4: gpio@30230000 {
 203                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 204                                 reg = <0x30230000 0x10000>;
 205                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 206                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 207                                 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
 208                                 gpio-controller;
 209                                 #gpio-cells = <2>;
 210                                 interrupt-controller;
 211                                 #interrupt-cells = <2>;
 212                         };
 213
 214                         gpio5: gpio@30240000 {
 215                                 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
 216                                 reg = <0x30240000 0x10000>;
 217                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 219                                 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
 220                                 gpio-controller;
 221                                 #gpio-cells = <2>;
 222                                 interrupt-controller;
 223                                 #interrupt-cells = <2>;
 224                         };
 225
 226                         wdog1: watchdog@30280000 {
 227                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 228                                 reg = <0x30280000 0x10000>;
 229                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 230                                 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
 231                                 status = "disabled";
 232                         };
 233
 234                         wdog2: watchdog@30290000 {
 235                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 236                                 reg = <0x30290000 0x10000>;
 237                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 238                                 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
 239                                 status = "disabled";
 240                         };
 241
 242                         wdog3: watchdog@302a0000 {
 243                                 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
 244                                 reg = <0x302a0000 0x10000>;
 245                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 246                                 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
 247                                 status = "disabled";
 248                         };
 249
 250                         sdma3: dma-controller@302b0000 {
 251                                 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
 252                                 reg = <0x302b0000 0x10000>;
 253                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 254                                 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
 255                                  <&clk IMX8MN_CLK_SDMA3_ROOT>;
 256                                 clock-names = "ipg", "ahb";
 257                                 #dma-cells = <3>;
 258                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 259                         };
 260
 261                         sdma2: dma-controller@302c0000 {
 262                                 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
 263                                 reg = <0x302c0000 0x10000>;
 264                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 265                                 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
 266                                          <&clk IMX8MN_CLK_SDMA2_ROOT>;
 267                                 clock-names = "ipg", "ahb";
 268                                 #dma-cells = <3>;
 269                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 270                         };
 271
 272                         iomuxc: pinctrl@30330000 {
 273                                 compatible = "fsl,imx8mn-iomuxc";
 274                                 reg = <0x30330000 0x10000>;
 275                         };
 276
 277                         gpr: iomuxc-gpr@30340000 {
 278                                 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
 279                                 reg = <0x30340000 0x10000>;
 280                         };
 281
 282                         ocotp: ocotp-ctrl@30350000 {
 283                                 compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
 284                                 reg = <0x30350000 0x10000>;
 285                                 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
 286                         };
 287
 288                         anatop: anatop@30360000 {
 289                                 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
 290                                              "syscon", "simple-bus";
 291                                 reg = <0x30360000 0x10000>;
 292                         };
 293
 294                         snvs: snvs@30370000 {
 295                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 296                                 reg = <0x30370000 0x10000>;
 297
 298                                 snvs_rtc: snvs-rtc-lp {
 299                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 300                                         regmap = <&snvs>;
 301                                         offset = <0x34>;
 302                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 303                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 304                                         clock-names = "snvs-rtc";
 305                                 };
 306
 307                                 snvs_pwrkey: snvs-powerkey {
 308                                         compatible = "fsl,sec-v4.0-pwrkey";
 309                                         regmap = <&snvs>;
 310                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 311                                         linux,keycode = <KEY_POWER>;
 312                                         wakeup-source;
 313                                         status = "disabled";
 314                                 };
 315                         };
 316
 317                         clk: clock-controller@30380000 {
 318                                 compatible = "fsl,imx8mn-ccm";
 319                                 reg = <0x30380000 0x10000>;
 320                                 #clock-cells = <1>;
 321                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 322                                          <&clk_ext3>, <&clk_ext4>;
 323                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 324                                               "clk_ext3", "clk_ext4";
 325                         };
 326
 327                         src: reset-controller@30390000 {
 328                                 compatible = "fsl,imx8mn-src", "syscon";
 329                                 reg = <0x30390000 0x10000>;
 330                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 331                                 #reset-cells = <1>;
 332                         };
 333                 };
 334
 335                 aips2: bus@30400000 {
 336                         compatible = "fsl,aips-bus", "simple-bus";
 337                         reg = <0x30400000 0x400000>;
 338                         #address-cells = <1>;
 339                         #size-cells = <1>;
 340                         ranges;
 341
 342                         pwm1: pwm@30660000 {
 343                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 344                                 reg = <0x30660000 0x10000>;
 345                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 346                                 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
 347                                         <&clk IMX8MN_CLK_PWM1_ROOT>;
 348                                 clock-names = "ipg", "per";
 349                                 #pwm-cells = <2>;
 350                                 status = "disabled";
 351                         };
 352
 353                         pwm2: pwm@30670000 {
 354                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 355                                 reg = <0x30670000 0x10000>;
 356                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 357                                 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
 358                                          <&clk IMX8MN_CLK_PWM2_ROOT>;
 359                                 clock-names = "ipg", "per";
 360                                 #pwm-cells = <2>;
 361                                 status = "disabled";
 362                         };
 363
 364                         pwm3: pwm@30680000 {
 365                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 366                                 reg = <0x30680000 0x10000>;
 367                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
 369                                          <&clk IMX8MN_CLK_PWM3_ROOT>;
 370                                 clock-names = "ipg", "per";
 371                                 #pwm-cells = <2>;
 372                                 status = "disabled";
 373                         };
 374
 375                         pwm4: pwm@30690000 {
 376                                 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
 377                                 reg = <0x30690000 0x10000>;
 378                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 379                                 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
 380                                          <&clk IMX8MN_CLK_PWM4_ROOT>;
 381                                 clock-names = "ipg", "per";
 382                                 #pwm-cells = <2>;
 383                                 status = "disabled";
 384                         };
 385                 };
 386
 387                 aips3: bus@30800000 {
 388                         compatible = "fsl,aips-bus", "simple-bus";
 389                         reg = <0x30800000 0x400000>;
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges;
 393
 394                         ecspi1: spi@30820000 {
 395                                 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 396                                 #address-cells = <1>;
 397                                 #size-cells = <0>;
 398                                 reg = <0x30820000 0x10000>;
 399                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 400                                 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
 401                                          <&clk IMX8MN_CLK_ECSPI1_ROOT>;
 402                                 clock-names = "ipg", "per";
 403                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 404                                 dma-names = "rx", "tx";
 405                                 status = "disabled";
 406                         };
 407
 408                         ecspi2: spi@30830000 {
 409                                 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 410                                 #address-cells = <1>;
 411                                 #size-cells = <0>;
 412                                 reg = <0x30830000 0x10000>;
 413                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 414                                 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
 415                                          <&clk IMX8MN_CLK_ECSPI2_ROOT>;
 416                                 clock-names = "ipg", "per";
 417                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 418                                 dma-names = "rx", "tx";
 419                                 status = "disabled";
 420                         };
 421
 422                         ecspi3: spi@30840000 {
 423                                 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
 424                                 #address-cells = <1>;
 425                                 #size-cells = <0>;
 426                                 reg = <0x30840000 0x10000>;
 427                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
 429                                          <&clk IMX8MN_CLK_ECSPI3_ROOT>;
 430                                 clock-names = "ipg", "per";
 431                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 432                                 dma-names = "rx", "tx";
 433                                 status = "disabled";
 434                         };
 435
 436                         uart1: serial@30860000 {
 437                                 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 438                                 reg = <0x30860000 0x10000>;
 439                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 440                                 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
 441                                          <&clk IMX8MN_CLK_UART1_ROOT>;
 442                                 clock-names = "ipg", "per";
 443                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 444                                 dma-names = "rx", "tx";
 445                                 status = "disabled";
 446                         };
 447
 448                         uart3: serial@30880000 {
 449                                 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 450                                 reg = <0x30880000 0x10000>;
 451                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
 453                                          <&clk IMX8MN_CLK_UART3_ROOT>;
 454                                 clock-names = "ipg", "per";
 455                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 456                                 dma-names = "rx", "tx";
 457                                 status = "disabled";
 458                         };
 459
 460                         uart2: serial@30890000 {
 461                                 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 462                                 reg = <0x30890000 0x10000>;
 463                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
 465                                          <&clk IMX8MN_CLK_UART2_ROOT>;
 466                                 clock-names = "ipg", "per";
 467                                 status = "disabled";
 468                         };
 469
 470                         i2c1: i2c@30a20000 {
 471                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 472                                 #address-cells = <1>;
 473                                 #size-cells = <0>;
 474                                 reg = <0x30a20000 0x10000>;
 475                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 476                                 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
 477                                 status = "disabled";
 478                         };
 479
 480                         i2c2: i2c@30a30000 {
 481                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 482                                 #address-cells = <1>;
 483                                 #size-cells = <0>;
 484                                 reg = <0x30a30000 0x10000>;
 485                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 486                                 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
 487                                 status = "disabled";
 488                         };
 489
 490                         i2c3: i2c@30a40000 {
 491                                 #address-cells = <1>;
 492                                 #size-cells = <0>;
 493                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 494                                 reg = <0x30a40000 0x10000>;
 495                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 496                                 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
 497                                 status = "disabled";
 498                         };
 499
 500                         i2c4: i2c@30a50000 {
 501                                 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
 502                                 #address-cells = <1>;
 503                                 #size-cells = <0>;
 504                                 reg = <0x30a50000 0x10000>;
 505                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 506                                 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
 507                                 status = "disabled";
 508                         };
 509
 510                         uart4: serial@30a60000 {
 511                                 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
 512                                 reg = <0x30a60000 0x10000>;
 513                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
 515                                          <&clk IMX8MN_CLK_UART4_ROOT>;
 516                                 clock-names = "ipg", "per";
 517                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 518                                 dma-names = "rx", "tx";
 519                                 status = "disabled";
 520                         };
 521
 522                         usdhc1: mmc@30b40000 {
 523                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
 524                                 reg = <0x30b40000 0x10000>;
 525                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 526                                 clocks = <&clk IMX8MN_CLK_DUMMY>,
 527                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 528                                          <&clk IMX8MN_CLK_USDHC1_ROOT>;
 529                                 clock-names = "ipg", "ahb", "per";
 530                                 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
 531                                 assigned-clock-rates = <400000000>;
 532                                 fsl,tuning-start-tap = <20>;
 533                                 fsl,tuning-step= <2>;
 534                                 bus-width = <4>;
 535                                 status = "disabled";
 536                         };
 537
 538                         usdhc2: mmc@30b50000 {
 539                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
 540                                 reg = <0x30b50000 0x10000>;
 541                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 542                                 clocks = <&clk IMX8MN_CLK_DUMMY>,
 543                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 544                                          <&clk IMX8MN_CLK_USDHC2_ROOT>;
 545                                 clock-names = "ipg", "ahb", "per";
 546                                 fsl,tuning-start-tap = <20>;
 547                                 fsl,tuning-step= <2>;
 548                                 bus-width = <4>;
 549                                 status = "disabled";
 550                         };
 551
 552                         usdhc3: mmc@30b60000 {
 553                                 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
 554                                 reg = <0x30b60000 0x10000>;
 555                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 556                                 clocks = <&clk IMX8MN_CLK_DUMMY>,
 557                                          <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
 558                                          <&clk IMX8MN_CLK_USDHC3_ROOT>;
 559                                 clock-names = "ipg", "ahb", "per";
 560                                 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 561                                 assigned-clock-rates = <400000000>;
 562                                 fsl,tuning-start-tap = <20>;
 563                                 fsl,tuning-step= <2>;
 564                                 bus-width = <4>;
 565                                 status = "disabled";
 566                         };
 567
 568                         sdma1: dma-controller@30bd0000 {
 569                                 compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
 570                                 reg = <0x30bd0000 0x10000>;
 571                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 572                                 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
 573                                          <&clk IMX8MN_CLK_SDMA1_ROOT>;
 574                                 clock-names = "ipg", "ahb";
 575                                 #dma-cells = <3>;
 576                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 577                         };
 578
 579                         fec1: ethernet@30be0000 {
 580                                 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
 581                                 reg = <0x30be0000 0x10000>;
 582                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 583                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 584                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
 586                                          <&clk IMX8MN_CLK_ENET1_ROOT>,
 587                                          <&clk IMX8MN_CLK_ENET_TIMER>,
 588                                          <&clk IMX8MN_CLK_ENET_REF>,
 589                                          <&clk IMX8MN_CLK_ENET_PHY_REF>;
 590                                 clock-names = "ipg", "ahb", "ptp",
 591                                               "enet_clk_ref", "enet_out";
 592                                 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
 593                                                   <&clk IMX8MN_CLK_ENET_TIMER>,
 594                                                   <&clk IMX8MN_CLK_ENET_REF>,
 595                                                   <&clk IMX8MN_CLK_ENET_TIMER>;
 596                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
 597                                                          <&clk IMX8MN_SYS_PLL2_100M>,
 598                                                          <&clk IMX8MN_SYS_PLL2_125M>;
 599                                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 600                                 fsl,num-tx-queues = <3>;
 601                                 fsl,num-rx-queues = <3>;
 602                                 status = "disabled";
 603                         };
 604
 605                 };
 606
 607                 aips4: bus@32c00000 {
 608                         compatible = "fsl,aips-bus", "simple-bus";
 609                         reg = <0x32c00000 0x400000>;
 610                         #address-cells = <1>;
 611                         #size-cells = <1>;
 612                         ranges;
 613
 614                         usbotg1: usb@32e40000 {
 615                                 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
 616                                 reg = <0x32e40000 0x200>;
 617                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 618                                 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
 619                                 clock-names = "usb1_ctrl_root_clk";
 620                                 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
 621                                                   <&clk IMX8MN_CLK_USB_CORE_REF>;
 622                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
 623                                                          <&clk IMX8MN_SYS_PLL1_100M>;
 624                                 fsl,usbphy = <&usbphynop1>;
 625                                 fsl,usbmisc = <&usbmisc1 0>;
 626                                 status = "disabled";
 627                         };
 628
 629                         usbmisc1: usbmisc@32e40200 {
 630                                 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
 631                                 #index-cells = <1>;
 632                                 reg = <0x32e40200 0x200>;
 633                         };
 634
 635                         usbotg2: usb@32e50000 {
 636                                 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
 637                                 reg = <0x32e50000 0x200>;
 638                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 639                                 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
 640                                 clock-names = "usb1_ctrl_root_clk";
 641                                 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
 642                                                   <&clk IMX8MN_CLK_USB_CORE_REF>;
 643                                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
 644                                                          <&clk IMX8MN_SYS_PLL1_100M>;
 645                                 fsl,usbphy = <&usbphynop2>;
 646                                 fsl,usbmisc = <&usbmisc2 0>;
 647                                 status = "disabled";
 648                         };
 649
 650                         usbmisc2: usbmisc@32e50200 {
 651                                 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
 652                                 #index-cells = <1>;
 653                                 reg = <0x32e50200 0x200>;
 654                         };
 655
 656                 };
 657
 658                 dma_apbh: dma-controller@33000000 {
 659                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
 660                         reg = <0x33000000 0x2000>;
 661                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 665                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 666                         #dma-cells = <1>;
 667                         dma-channels = <4>;
 668                         clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 669                 };
 670
 671                 gpmi: nand-controller@33002000 {
 672                         compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
 673                         #address-cells = <1>;
 674                         #size-cells = <1>;
 675                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
 676                         reg-names = "gpmi-nand", "bch";
 677                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 678                         interrupt-names = "bch";
 679                         clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
 680                                  <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 681                         clock-names = "gpmi_io", "gpmi_bch_apb";
 682                         dmas = <&dma_apbh 0>;
 683                         dma-names = "rx-tx";
 684                         status = "disabled";
 685                 };
 686
 687                 gic: interrupt-controller@38800000 {
 688                         compatible = "arm,gic-v3";
 689                         reg = <0x38800000 0x10000>,
 690                               <0x38880000 0xc0000>;
 691                         #interrupt-cells = <3>;
 692                         interrupt-controller;
 693                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 694                 };
 695         };
 696
 697         usbphynop1: usbphynop1 {
 698                 compatible = "usb-nop-xceiv";
 699                 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
 700                 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
 701                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
 702                 clock-names = "main_clk";
 703         };
 704
 705         usbphynop2: usbphynop2 {
 706                 compatible = "usb-nop-xceiv";
 707                 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
 708                 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
 709                 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
 710                 clock-names = "main_clk";
 711         };
 712 };