arch/arm/dts/imx8mm-verdin.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/usb/pd.h>
   9 #include "imx8mm.dtsi"
  10
  11 / {
  12         model = "Toradex Verdin iMX8M Mini Quad/DualLite";
  13         compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         aliases {
  20                 eeprom0 = &eeprom_module;
  21                 eeprom1 = &eeprom_carrier_board;
  22                 eeprom2 = &eeprom_display_adapter;
  23         };
  24
  25         /* fixed clock dedicated to SPI CAN controller */
  26         clk20m: oscillator {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <20000000>;
  30         };
  31
  32         reg_ethphy: regulator-ethphy {
  33                 compatible = "regulator-fixed";
  34                 enable-active-high;
  35                 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  36                 off-on-delay = <500000>;
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_reg_eth>;
  39                 regulator-boot-on;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-name = "V3.3_ETH";
  43                 startup-delay-us = <200000>;
  44         };
  45
  46         reg_usb_otg1_vbus: regulator-usb-otg1 {
  47                 compatible = "regulator-fixed";
  48                 enable-active-high;
  49                 /* Verdin USB1_EN */
  50                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  51                 pinctrl-names = "default";
  52                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  53                 regulator-name = "usb_otg1_vbus";
  54                 regulator-min-microvolt = <5000000>;
  55                 regulator-max-microvolt = <5000000>;
  56         };
  57
  58         reg_usb_otg2_vbus: regulator-usb-otg2 {
  59                 compatible = "regulator-fixed";
  60                 enable-active-high;
  61                 /* Verdin USB2_EN */
  62                 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  65                 regulator-name = "usb_otg2_vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68         };
  69
  70         reg_usdhc2_vmmc: regulator-usdhc2 {
  71                 compatible = "regulator-fixed";
  72                 enable-active-high;
  73                 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
  76                 regulator-name = "V3.3_SD";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 startup-delay-us = <2000>;
  80         };
  81
  82         reg_wifi_en: regulator-wifi-en {
  83                 compatible = "regulator-fixed";
  84                 enable-active-high;
  85                 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
  88                 regulator-name = "V3.3_WI-FI";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 startup-delay-us = <2000>;
  92         };
  93 };
  94
  95 &A53_0 {
  96         arm-supply = <&buck2_reg>;
  97 };
  98
  99 &clk {
 100         assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
 101         assigned-clock-rates = <786432000>, <722534400>;
 102 };
 103
 104 /* Verdin SPI_1 */
 105 &ecspi2 {
 106         #address-cells = <1>;
 107         #size-cells = <0>;
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_ecspi2>;
 110         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 111         status = "okay";
 112
 113         spidev20: spidev@0 {
 114                 compatible = "toradex,evalspi";
 115                 reg = <0>;
 116                 spi-max-frequency = <10000000>;
 117                 status = "okay";
 118         };
 119 };
 120
 121 /* On-module CAN controller 1 & 2 */
 122 &ecspi3 {
 123         #address-cells = <1>;
 124         #size-cells = <0>;
 125         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
 126                    <&gpio1 5 GPIO_ACTIVE_LOW>;
 127         /* This property is required, even if marked as obsolete in the doku */
 128         fsl,spi-num-chipselects = <2>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_ecspi3>;
 131         status = "okay";
 132
 133         can1: can@0 {
 134                 compatible = "microchip,mcp2517fd";
 135                 clocks = <&clk20m>;
 136                 gpio-controller;
 137                 interrupt-parent = <&gpio1>;
 138                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 139                 microchip,clock-allways-on;
 140                 microchip,clock-out-div = <1>;
 141                 pinctrl-names = "default";
 142                 pinctrl-0 = <&pinctrl_can1_int>;
 143                 reg = <0>;
 144                 spi-max-frequency = <2000000>;
 145         };
 146
 147         can2: can@1 {
 148                 compatible = "microchip,mcp2517fd";
 149                 clocks = <&clk20m>;
 150                 gpio-controller;
 151                 interrupt-parent = <&gpio1>;
 152                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&pinctrl_can2_int>;
 155                 reg = <1>;
 156                 spi-max-frequency = <2000000>;
 157         };
 158 };
 159
 160 &fec1 {
 161         fsl,magic-packet;
 162         phy-handle = <&ethphy0>;
 163         phy-mode = "rgmii";
 164         phy-supply = <&reg_ethphy>;
 165         pinctrl-names = "default", "sleep";
 166         pinctrl-0 = <&pinctrl_fec1>;
 167         pinctrl-1 = <&pinctrl_fec1_sleep>;
 168         status = "okay";
 169
 170         mdio {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173
 174                 ethphy0: ethernet-phy@7 {
 175                         compatible = "ethernet-phy-ieee802.3-c22";
 176                         interrupt-parent = <&gpio1>;
 177                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 178                         micrel,led-mode = <0>;
 179                         reg = <7>;
 180                 };
 181         };
 182 };
 183
 184 &gpio4 {
 185         /*
 186          * The SE050 security element may be driven via I2C from user space.
 187          * The element itself is enabled here as it has no kernel driver.
 188          */
 189         se050_ena {
 190                 gpio-hog;
 191                 gpios = <19 GPIO_ACTIVE_HIGH>;
 192                 line-name = "SE050_ENABLE";
 193                 output-high;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&pinctrl_se050_ena>;
 196         };
 197 };
 198
 199 /* On-module I2C */
 200 &i2c1 {
 201         clock-frequency = <400000>;
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_i2c1>;
 204         status = "okay";
 205
 206         /* Assembled on V1.1 HW and later */
 207         pmic {
 208                 reg = <0x25>;
 209                 u-boot,dm-spl;
 210                 compatible = "nxp,pca9450a";
 211                 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
 212                 pinctrl-0 = <&pinctrl_pmic>;
 213                 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
 214
 215                 regulators {
 216                         u-boot,dm-spl;
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219
 220                         pca9450,pmic-buck2-uses-i2c-dvs;
 221                         /* Run/Standby voltage */
 222                         pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
 223
 224                         buck1_reg: regulator@0 {
 225                                 reg = <0>;
 226                                 regulator-compatible = "buck1";
 227                                 regulator-min-microvolt = <600000>;
 228                                 regulator-max-microvolt = <2187500>;
 229                                 regulator-boot-on;
 230                                 regulator-always-on;
 231                                 regulator-ramp-delay = <3125>;
 232                         };
 233
 234                         buck2_reg: regulator@1 {
 235                                 reg = <1>;
 236                                 regulator-compatible = "buck2";
 237                                 regulator-min-microvolt = <600000>;
 238                                 regulator-max-microvolt = <2187500>;
 239                                 regulator-boot-on;
 240                                 regulator-always-on;
 241                                 regulator-ramp-delay = <3125>;
 242                         };
 243
 244                         buck3_reg: regulator@2 {
 245                                 reg = <2>;
 246                                 regulator-compatible = "buck3";
 247                                 regulator-min-microvolt = <600000>;
 248                                 regulator-max-microvolt = <2187500>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                         };
 252
 253                         buck4_reg: regulator@3 {
 254                                 reg = <3>;
 255                                 regulator-compatible = "buck4";
 256                                 regulator-min-microvolt = <600000>;
 257                                 regulator-max-microvolt = <3400000>;
 258                                 regulator-boot-on;
 259                                 regulator-always-on;
 260                         };
 261
 262                         buck5_reg: regulator@4 {
 263                                 reg = <4>;
 264                                 regulator-compatible = "buck5";
 265                                 regulator-min-microvolt = <600000>;
 266                                 regulator-max-microvolt = <3400000>;
 267                                 regulator-boot-on;
 268                                 regulator-always-on;
 269                         };
 270
 271                         buck6_reg: regulator@5 {
 272                                 reg = <5>;
 273                                 regulator-compatible = "buck6";
 274                                 regulator-min-microvolt = <600000>;
 275                                 regulator-max-microvolt = <3400000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                         };
 279
 280                         ldo1_reg: regulator@6 {
 281                                 reg = <6>;
 282                                 regulator-compatible = "ldo1";
 283                                 regulator-min-microvolt = <1600000>;
 284                                 regulator-max-microvolt = <3300000>;
 285                                 regulator-boot-on;
 286                                 regulator-always-on;
 287                         };
 288
 289                         ldo2_reg: regulator@7 {
 290                                 reg = <7>;
 291                                 regulator-compatible = "ldo2";
 292                                 regulator-min-microvolt = <800000>;
 293                                 regulator-max-microvolt = <1150000>;
 294                                 regulator-boot-on;
 295                                 regulator-always-on;
 296                         };
 297
 298                         ldo3_reg: regulator@8 {
 299                                 reg = <8>;
 300                                 regulator-compatible = "ldo3";
 301                                 regulator-min-microvolt = <800000>;
 302                                 regulator-max-microvolt = <3300000>;
 303                                 regulator-boot-on;
 304                                 regulator-always-on;
 305                         };
 306
 307                         ldo4_reg: regulator@9 {
 308                                 reg = <9>;
 309                                 regulator-compatible = "ldo4";
 310                                 regulator-min-microvolt = <800000>;
 311                                 regulator-max-microvolt = <3300000>;
 312                                 regulator-boot-on;
 313                                 regulator-always-on;
 314                         };
 315
 316                         ldo5_reg: regulator@10 {
 317                                 reg = <10>;
 318                                 regulator-compatible = "ldo5";
 319                                 regulator-min-microvolt = <800000>;
 320                                 regulator-max-microvolt = <3300000>;
 321                         };
 322
 323                 };
 324         };
 325
 326         /* Epson RX8130 real time clock on carrier board */
 327         rtc@32 {
 328                 compatible = "epson,rx8130";
 329                 reg = <0x32>;
 330         };
 331
 332         eeprom_module: eeprom@50 {
 333                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 334                 pagesize = <16>;
 335                 reg = <0x50>;
 336         };
 337 };
 338
 339 /* Verdin I2C_2_DSI */
 340 &i2c2 {
 341         clock-frequency = <10000>;
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_i2c2>;
 344         status = "okay";
 345 };
 346
 347 /* Verdin I2C_3_HDMI N/A */
 348
 349 /* Verdin I2C_4_CSI */
 350 &i2c3 {
 351         clock-frequency = <400000>;
 352         pinctrl-names = "default";
 353         pinctrl-0 = <&pinctrl_i2c3>;
 354         status = "okay";
 355 };
 356
 357 /* Verdin I2C_1 */
 358 &i2c4 {
 359         clock-frequency = <400000>;
 360         pinctrl-names = "default";
 361         pinctrl-0 = <&pinctrl_i2c4>;
 362         status = "okay";
 363
 364         /* Audio Codec */
 365         wm8904_1a: codec@1a {
 366                 compatible = "wlf,wm8904";
 367                 #sound-dai-cells = <0>;
 368                 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
 369                 clock-names = "mclk";
 370                 reg = <0x1a>;
 371         };
 372
 373         gpio_expander_21: gpio-expander@21 {
 374                 compatible = "nxp,pcal6416";
 375                 #gpio-cells = <2>;
 376                 gpio-controller;
 377                 reg = <0x21>;
 378         };
 379
 380         /* Current measurement into module VCC */
 381         hwmon@40 {
 382                 compatible = "ti,ina219";
 383                 reg = <0x40>;
 384                 shunt-resistor = <10000>;
 385                 status = "okay";
 386         };
 387
 388         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
 389         eeprom_display_adapter: eeprom@50 {
 390                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 391                 pagesize = <16>;
 392                 reg = <0x50>;
 393         };
 394
 395         /* EEPROM on carrier board */
 396         eeprom_carrier_board: eeprom@57 {
 397                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 398                 pagesize = <16>;
 399                 reg = <0x57>;
 400         };
 401 };
 402
 403 /* Verdin PWM_3_DSI */
 404 &pwm1 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_pwm_1>;
 407         #pwm-cells = <3>;
 408         status = "okay";
 409 };
 410
 411 /* Verdin PWM_1 */
 412 &pwm2 {
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&pinctrl_pwm_2>;
 415         #pwm-cells = <3>;
 416         status = "okay";
 417 };
 418
 419 /* Verdin PWM_2 */
 420 &pwm3 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&pinctrl_pwm_3>;
 423         #pwm-cells = <3>;
 424         status = "okay";
 425 };
 426
 427 /* Verdin UART_3, Console/Debug UART */
 428 &uart1 {
 429         fsl,uart-has-rtscts;
 430         pinctrl-names = "default";
 431         pinctrl-0 = <&pinctrl_uart1>;
 432         status = "okay";
 433 };
 434
 435 /* Verdin UART_1 */
 436 &uart2 {
 437         pinctrl-names = "default";
 438         pinctrl-0 = <&pinctrl_uart2>;
 439         fsl,uart-has-rtscts;
 440         status = "okay";
 441 };
 442
 443 /* Verdin UART_2 */
 444 &uart3 {
 445         pinctrl-names = "default";
 446         pinctrl-0 = <&pinctrl_uart3>;
 447         fsl,uart-has-rtscts;
 448         status = "okay";
 449 };
 450
 451 /* Verdin UART_4 */
 452 /*
 453  * resource allocated to M4 by default, must not be accessed from A-35 or you
 454  * get an OOPS
 455  */
 456 &uart4 {
 457         pinctrl-names = "default";
 458         pinctrl-0 = <&pinctrl_uart4>;
 459         status = "disabled";
 460 };
 461
 462 /* Verdin USB_1 */
 463 &usbotg1 {
 464         dr_mode = "otg";
 465         picophy,dc-vol-level-adjust = <7>;
 466         picophy,pre-emp-curr-control = <3>;
 467         vbus-supply = <&reg_usb_otg1_vbus>;
 468         status = "okay";
 469 };
 470
 471 /* Verdin USB_2 */
 472 &usbotg2 {
 473         dr_mode = "host";
 474         picophy,dc-vol-level-adjust = <7>;
 475         picophy,pre-emp-curr-control = <3>;
 476         vbus-supply = <&reg_usb_otg2_vbus>;
 477         status = "okay";
 478 };
 479
 480 /* On-module eMMC */
 481 &usdhc1 {
 482         bus-width = <8>;
 483         keep-power-in-suspend;
 484         non-removable;
 485         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 486         pinctrl-0 = <&pinctrl_usdhc1>;
 487         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 488         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 489         pm-ignore-notify;
 490         status = "okay";
 491         /* TODO Strobe */
 492 };
 493
 494 /* Verdin SD_1 */
 495 &usdhc2 {
 496         bus-width = <4>;
 497         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 498         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 499         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 500         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 501         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 502         vmmc-supply = <&reg_usdhc2_vmmc>;
 503         status = "okay";
 504 };
 505
 506 /* On-module Wi-Fi */
 507 &usdhc3 {
 508         bus-width = <4>;
 509         non-removable;
 510         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 511         pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
 512         pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
 513         pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
 514         vmmc-supply = <&reg_wifi_en>;
 515         status = "okay";
 516 };
 517
 518 &wdog1 {
 519         fsl,ext-reset-output;
 520         pinctrl-names = "default";
 521         pinctrl-0 = <&pinctrl_wdog>;
 522         status = "okay";
 523 };
 524
 525 &iomuxc {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,
 528                     <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,
 529                     <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,
 530                     <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,
 531                     <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;
 532
 533         pinctrl_can1_int: can1intgrp {
 534                 fsl,pins = <
 535                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x1c4
 536                 >;
 537         };
 538
 539         pinctrl_can2_int: can2intgrp {
 540                 fsl,pins = <
 541                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x1c4
 542                 >;
 543         };
 544
 545         pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {
 546                 fsl,pins = <
 547                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x1c4           /* SODIMM 250 */
 548                 >;
 549         };
 550
 551         pinctrl_dsi_bkl_en: dsi_bkl_en {
 552                 fsl,pins = <
 553                         MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3       0x1c4           /* SODIMM 21 */
 554                 >;
 555         };
 556
 557         pinctrl_ecspi2: ecspi2grp {
 558                 fsl,pins = <
 559                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x1c4           /* SODIMM 198 */
 560                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x4             /* SODIMM 200 */
 561                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x4             /* SODIMM 196 */
 562                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x1c4           /* SODIMM 202 */
 563                 >;
 564         };
 565
 566         pinctrl_ecspi3: ecspi3grp {
 567                 fsl,pins = <
 568                         MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x1c4
 569                         MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK      0x4
 570                         MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI      0x4
 571                         MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO      0x1c4
 572                         MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25       0x1c4
 573                 >;
 574         };
 575
 576         pinctrl_fec1: fec1grp {
 577                 fsl,pins = <
 578                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 579                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 580                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 581                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 582                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 583                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 584                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 585                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 586                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 587                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 588                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 589                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 590                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 591                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 592                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x1c4
 593                 >;
 594         };
 595
 596         pinctrl_fec1_sleep: fec1-sleepgrp {
 597                 fsl,pins = <
 598                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 599                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 600                         MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                0x1f
 601                         MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                0x1f
 602                         MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                0x1f
 603                         MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                0x1f
 604                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 605                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 606                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 607                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 608                         MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                0x1f
 609                         MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x1f
 610                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 611                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 612                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x184
 613                 >;
 614         };
 615
 616         pinctrl_flexspi0: flexspi0grp {
 617                 fsl,pins = <
 618                         MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x1c2           /* SODIMM 52 */
 619                         MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82            /* SODIMM 54 */
 620                         MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B    0x82            /* SODIMM 64 */
 621                         MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82            /* SODIMM 56 */
 622                         MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82            /* SODIMM 58 */
 623                         MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82            /* SODIMM 60 */
 624                         MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82            /* SODIMM 62 */
 625                         MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS        0x82            /* SODIMM 66 */
 626                 >;
 627         };
 628
 629         /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
 630         pinctrl_gpio1: gpio1grp {
 631                 fsl,pins = <
 632                         MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4       0x184           /* SODIMM 206 */
 633                 >;
 634         };
 635
 636         pinctrl_gpio2: gpio2grp {
 637                 fsl,pins = <
 638                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x184           /* SODIMM 208 */
 639                 >;
 640         };
 641
 642         pinctrl_gpio3: gpio3grp {
 643                 fsl,pins = <
 644                         MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26       0x184           /* SODIMM 210 */
 645                 >;
 646         };
 647
 648         pinctrl_gpio4: gpio4grp {
 649                 fsl,pins = <
 650                         MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27       0x184           /* SODIMM 212 */
 651                 >;
 652         };
 653
 654         pinctrl_gpio5: gpio5grp {
 655                 fsl,pins = <
 656                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x184           /* SODIMM 216 */
 657                 >;
 658         };
 659
 660         pinctrl_gpio6: gpio6grp {
 661                 fsl,pins = <
 662                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x184           /* SODIMM 218 */
 663                 >;
 664         };
 665
 666         pinctrl_gpio7: gpio7grp {
 667                 fsl,pins = <
 668                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x184           /* SODIMM 220 */
 669                 >;
 670         };
 671
 672         pinctrl_gpio8: gpio8grp {
 673                 fsl,pins = <
 674                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x184           /* SODIMM 222 */
 675                 >;
 676         };
 677
 678         pinctrl_gpio_hog1: gpiohog1grp {
 679                 fsl,pins = <
 680                         MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20       0x1c4           /* SODIMM 88 */
 681                         MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1         0x1c4           /* SODIMM 90 */
 682                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x1c4           /* SODIMM 92 */
 683                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x1c4           /* SODIMM 94 */
 684                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x1c4           /* SODIMM 96 */
 685                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x1c4           /* SODIMM 100 */
 686                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x1c4           /* SODIMM 102 */
 687                         MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11        0x1c4           /* SODIMM 104 */
 688                         MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12       0x1c4           /* SODIMM 106 */
 689                         MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13       0x1c4           /* SODIMM 108 */
 690                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14       0x1c4           /* SODIMM 112 */
 691                         MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15       0x1c4           /* SODIMM 114 */
 692                         MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x1c4           /* SODIMM 116 */
 693                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x1c4           /* SODIMM 118 */
 694                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0x1c4           /* SODIMM 120 */
 695                 >;
 696         };
 697
 698         pinctrl_gpio_hog2: gpiohog2grp {
 699                 fsl,pins = <
 700                         MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2        0x1c4           /* SODIMM 91 */
 701                 >;
 702         };
 703
 704         pinctrl_gpio_hog3: gpiohog3grp {
 705                 fsl,pins = <
 706                         MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13      0x1c4           /* SODIMM 157 */
 707                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4           /* SODIMM 187 */
 708                 >;
 709         };
 710
 711         /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
 712         pinctrl_gpio_hpd: gpiohpdgrp {
 713                 fsl,pins = <
 714                         MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15       0x184           /* SODIMM 17 */
 715                 >;
 716         };
 717
 718         /* On-module I2C */
 719         pinctrl_i2c1: i2c1grp {
 720                 fsl,pins = <
 721                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c6
 722                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c6
 723                 >;
 724         };
 725
 726         /* Verdin I2C_4_CSI */
 727         pinctrl_i2c2: i2c2grp {
 728                 fsl,pins = <
 729                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c6      /* SODIMM 55 */
 730                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c6      /* SODIMM 53 */
 731                 >;
 732         };
 733
 734         /* Verdin I2C_2_DSI */
 735         pinctrl_i2c3: i2c3grp {
 736                 fsl,pins = <
 737                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c6      /* SODIMM 95 */
 738                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c6      /* SODIMM 93 */
 739                 >;
 740         };
 741
 742         /* Verdin I2C_1 */
 743         pinctrl_i2c4: i2c4grp {
 744                 fsl,pins = <
 745                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c6      /* SODIMM 14 */
 746                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c6      /* SODIMM 12 */
 747                 >;
 748         };
 749
 750         pinctrl_pcie0: pcie0grp {
 751                 fsl,pins = <
 752                         MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19       0x6             /* SODIMM 244 */
 753                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x6             /* PMIC_EN_PCIe_CLK */
 754                 >;
 755         };
 756
 757         pinctrl_pmic: pmicirqgrp {
 758                 fsl,pins = <
 759                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 760                 >;
 761         };
 762
 763         pinctrl_pwm_1: pwm1grp {
 764                 fsl,pins = <
 765                         MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT        0x6             /* SODIMM 19 */
 766                 >;
 767         };
 768
 769         pinctrl_pwm_2: pwm2grp {
 770                 fsl,pins = <
 771                         MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT          0x6             /* SODIMM 15 */
 772                 >;
 773         };
 774
 775         pinctrl_pwm_3: pwm3grp {
 776                 fsl,pins = <
 777                         MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT          0x6             /* SODIMM 16 */
 778                 >;
 779         };
 780
 781         pinctrl_reg_eth: regethgrp {
 782                 fsl,pins = <
 783                         MX8MM_IOMUXC_SD2_WP_GPIO2_IO20          0x184
 784                 >;
 785         };
 786
 787         pinctrl_reg_usb1_en: regusb1engrp {
 788                 fsl,pins = <
 789                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x184           /* SODIMM 155 */
 790                 >;
 791         };
 792
 793         pinctrl_reg_usb2_en: regusb2engrp {
 794                 fsl,pins = <
 795                         MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14      0x184           /* SODIMM 185 */
 796                 >;
 797         };
 798
 799         pinctrl_sai2: sai2grp {
 800                 fsl,pins = <
 801                         MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6            /* SODIMM 38 */
 802                         MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6            /* SODIMM 36 */
 803                         MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6            /* SODIMM 30 */
 804                         MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6            /* SODIMM 34 */
 805                         MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6            /* SODIMM 32 */
 806                 >;
 807         };
 808
 809         pinctrl_sai5: sai5grp {
 810                 fsl,pins = <
 811                         MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0    0xd6            /* SODIMM 48 */
 812                         MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC     0xd6            /* SODIMM 44 */
 813                         MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK     0xd6            /* SODIMM 42 */
 814                         MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0    0xd6            /* SODIMM 46 */
 815                 >;
 816         };
 817
 818         pinctrl_se050_ena: se050enagrp {
 819                 fsl,pins = <
 820                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19       0x184
 821                 >;
 822         };
 823
 824         pinctrl_uart1: uart1grp {
 825                 fsl,pins = <
 826                         MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX      0x1c4           /* SODIMM 147 */
 827                         MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX     0x1c4           /* SODIMM 149 */
 828                 >;
 829         };
 830
 831         pinctrl_uart2: uart2grp {
 832                 fsl,pins = <
 833                         MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B   0x1c4           /* SODIMM 133 */
 834                         MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B   0x1c4           /* SODIMM 135 */
 835                         MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX      0x1c4           /* SODIMM 131 */
 836                         MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX     0x1c4           /* SODIMM 129 */
 837                 >;
 838         };
 839
 840         pinctrl_uart3: uart3grp {
 841                 fsl,pins = <
 842                         MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x1c4   /* SODIMM 141 */
 843                         MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x1c4   /* SODIMM 139 */
 844                         MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x1c4   /* SODIMM 137 */
 845                         MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B         0x1c4   /* SODIMM 143 */
 846                 >;
 847         };
 848
 849         pinctrl_uart4: uart4grp {
 850                 fsl,pins = <
 851                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x1c4           /* SODIMM 151 */
 852                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x1c4           /* SODIMM 153 */
 853                 >;
 854         };
 855
 856         pinctrl_usdhc1: usdhc1grp {
 857                 fsl,pins = <
 858                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 859                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 860                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 861                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 862                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 863                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 864                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d0
 865                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d0
 866                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d0
 867                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d0
 868                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x190
 869                 >;
 870         };
 871
 872         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 873                 fsl,pins = <
 874                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 875                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 876                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 877                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 878                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 879                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 880                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d4
 881                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d4
 882                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d4
 883                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d4
 884                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x194
 885                 >;
 886         };
 887
 888         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 889                 fsl,pins = <
 890                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 891                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 892                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 893                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 894                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 895                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 896                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d6
 897                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d6
 898                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d6
 899                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d6
 900                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x196
 901                 >;
 902         };
 903
 904         pinctrl_usdhc2_cd: usdhc2cdgrp {
 905                 fsl,pins = <
 906                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4           /* SODIMM 84 */
 907                 >;
 908         };
 909
 910         pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
 911                 fsl,pins = <
 912                         MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5         0x184           /* SODIMM 76 */
 913                 >;
 914         };
 915
 916         pinctrl_usdhc2: usdhc2grp {
 917                 fsl,pins = <
 918                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 919                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190           /* SODIMM 78 */
 920                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0           /* SODIMM 74 */
 921                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0           /* SODIMM 80 */
 922                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0           /* SODIMM 82 */
 923                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0           /* SODIMM 70 */
 924                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0           /* SODIMM 72 */
 925                 >;
 926         };
 927
 928         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 929                 fsl,pins = <
 930                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 931                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 932                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 933                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 934                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 935                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 936                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 937                 >;
 938         };
 939
 940         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 941                 fsl,pins = <
 942                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 943                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 944                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 945                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 946                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 947                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 948                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 949                 >;
 950         };
 951
 952         pinctrl_usdhc3: usdhc3grp {
 953                 fsl,pins = <
 954                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 955                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 956                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 957                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 958                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 959                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 960                 >;
 961         };
 962
 963         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 964                 fsl,pins = <
 965                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 966                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 967                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 968                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 969                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 970                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 971                 >;
 972         };
 973
 974         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 975                 fsl,pins = <
 976                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 977                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 978                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 979                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 980                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 981                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 982                 >;
 983         };
 984
 985         pinctrl_wdog: wdoggrp {
 986                 fsl,pins = <
 987                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 988                 >;
 989         };
 990
 991         pinctrl_wifi_ctrl: wifictrlgrp {
 992                 fsl,pins = <
 993                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x1c4           /* WIFI_WKUP_BT */
 994                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9        0x1c4           /* WIFI_W_WKUP_HOST */
 995                         MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x1c4           /* WIFI_WKUP_WLAN */
 996                 >;
 997         };
 998
 999         pinctrl_wifi_i2s: wifii2sgrp {
1000                 fsl,pins = <
1001                         MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK     0xd6
1002                         MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0    0xd6
1003                         MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC     0xd6
1004                         MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0    0xd6
1005                 >;
1006         };
1007
1008         pinctrl_wifi_pwr_en: wifipwrengrp {
1009                 fsl,pins = <
1010                         MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x184           /* PMIC_EN_WIFI */
1011                 >;
1012         };
1013 };