arch/arm/dts/imx8mm-verdin.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright 2020 Toradex
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/usb/pd.h>
   9 #include "imx8mm.dtsi"
  10
  11 / {
  12         model = "Toradex Verdin iMX8M Mini Quad/DualLite";
  13         compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         aliases {
  20                 eeprom0 = &eeprom_module;
  21                 eeprom1 = &eeprom_carrier_board;
  22                 eeprom2 = &eeprom_display_adapter;
  23         };
  24
  25         /* fixed clock dedicated to SPI CAN controller */
  26         clk20m: oscillator {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <20000000>;
  30         };
  31
  32         reg_ethphy: regulator-ethphy {
  33                 compatible = "regulator-fixed";
  34                 enable-active-high;
  35                 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
  36                 off-on-delay = <500000>;
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_reg_eth>;
  39                 regulator-boot-on;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-name = "V3.3_ETH";
  43                 startup-delay-us = <200000>;
  44         };
  45
  46         reg_usb_otg1_vbus: regulator-usb-otg1 {
  47                 compatible = "regulator-fixed";
  48                 enable-active-high;
  49                 /* Verdin USB1_EN */
  50                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  51                 pinctrl-names = "default";
  52                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  53                 regulator-name = "usb_otg1_vbus";
  54                 regulator-min-microvolt = <5000000>;
  55                 regulator-max-microvolt = <5000000>;
  56         };
  57
  58         reg_usb_otg2_vbus: regulator-usb-otg2 {
  59                 compatible = "regulator-fixed";
  60                 enable-active-high;
  61                 /* Verdin USB2_EN */
  62                 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  63                 pinctrl-names = "default";
  64                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  65                 regulator-name = "usb_otg2_vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68         };
  69
  70         reg_usdhc2_vmmc: regulator-usdhc2 {
  71                 compatible = "regulator-fixed";
  72                 enable-active-high;
  73                 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
  76                 regulator-name = "V3.3_SD";
  77                 regulator-min-microvolt = <3300000>;
  78                 regulator-max-microvolt = <3300000>;
  79                 startup-delay-us = <2000>;
  80         };
  81
  82         reg_wifi_en: regulator-wifi-en {
  83                 compatible = "regulator-fixed";
  84                 enable-active-high;
  85                 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
  86                 pinctrl-names = "default";
  87                 pinctrl-0 = <&pinctrl_wifi_pwr_en>;
  88                 regulator-name = "V3.3_WI-FI";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 startup-delay-us = <2000>;
  92         };
  93 };
  94
  95 &A53_0 {
  96         arm-supply = <&buck2_reg>;
  97 };
  98
  99 &clk {
 100         assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
 101         assigned-clock-rates = <786432000>, <722534400>;
 102 };
 103
 104 /* Verdin SPI_1 */
 105 &ecspi2 {
 106         #address-cells = <1>;
 107         #size-cells = <0>;
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_ecspi2>;
 110         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 111         status = "okay";
 112
 113         spidev20: spidev@0 {
 114                 compatible = "toradex,evalspi";
 115                 reg = <0>;
 116                 spi-max-frequency = <10000000>;
 117                 status = "okay";
 118         };
 119 };
 120
 121 /* On-module CAN controller 1 & 2 */
 122 &ecspi3 {
 123         #address-cells = <1>;
 124         #size-cells = <0>;
 125         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
 126                    <&gpio1 5 GPIO_ACTIVE_LOW>;
 127         /* This property is required, even if marked as obsolete in the doku */
 128         fsl,spi-num-chipselects = <2>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_ecspi3>;
 131         status = "okay";
 132
 133         can1: can@0 {
 134                 compatible = "microchip,mcp2517fd";
 135                 clocks = <&clk20m>;
 136                 gpio-controller;
 137                 interrupt-parent = <&gpio1>;
 138                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 139                 microchip,clock-allways-on;
 140                 microchip,clock-out-div = <1>;
 141                 pinctrl-names = "default";
 142                 pinctrl-0 = <&pinctrl_can1_int>;
 143                 reg = <0>;
 144                 spi-max-frequency = <2000000>;
 145         };
 146
 147         can2: can@1 {
 148                 compatible = "microchip,mcp2517fd";
 149                 clocks = <&clk20m>;
 150                 gpio-controller;
 151                 interrupt-parent = <&gpio1>;
 152                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&pinctrl_can2_int>;
 155                 reg = <1>;
 156                 spi-max-frequency = <2000000>;
 157         };
 158 };
 159
 160 &fec1 {
 161         fsl,magic-packet;
 162         phy-handle = <&ethphy0>;
 163         phy-mode = "rgmii";
 164         phy-supply = <&reg_ethphy>;
 165         pinctrl-names = "default", "sleep";
 166         pinctrl-0 = <&pinctrl_fec1>;
 167         pinctrl-1 = <&pinctrl_fec1_sleep>;
 168         status = "okay";
 169
 170         mdio {
 171                 #address-cells = <1>;
 172                 #size-cells = <0>;
 173
 174                 ethphy0: ethernet-phy@7 {
 175                         compatible = "ethernet-phy-ieee802.3-c22";
 176                         interrupt-parent = <&gpio1>;
 177                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 178                         micrel,led-mode = <0>;
 179                         reg = <7>;
 180                 };
 181         };
 182 };
 183
 184 &gpio4 {
 185         /*
 186          * The SE050 security element may be driven via I2C from user space.
 187          * The element itself is enabled here as it has no kernel driver.
 188          */
 189         se050_ena {
 190                 gpio-hog;
 191                 gpios = <19 GPIO_ACTIVE_HIGH>;
 192                 line-name = "SE050_ENABLE";
 193                 output-high;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&pinctrl_se050_ena>;
 196         };
 197 };
 198
 199 /* On-module I2C */
 200 &i2c1 {
 201         clock-frequency = <400000>;
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_i2c1>;
 204         status = "okay";
 205
 206         pmic@4b {
 207                 compatible = "rohm,bd71840", "rohm,bd71837";
 208                 bd71837,pmic-buck2-uses-i2c-dvs;
 209                 bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
 210                 gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
 211                 /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
 212                 pinctrl-0 = <&pinctrl_pmic>;
 213                 reg = <0x4b>;
 214
 215                 gpo {
 216                         rohm,drv = <0x0C>;      /* 0b0000_1100 all gpos with cmos output mode */
 217                 };
 218
 219                 regulators {
 220                         buck1_reg: BUCK1 {
 221                                 regulator-always-on;
 222                                 regulator-boot-on;
 223                                 regulator-compatible = "buck1";
 224                                 regulator-max-microvolt = <1300000>;
 225                                 regulator-min-microvolt = <700000>;
 226                                 regulator-ramp-delay = <1250>;
 227                         };
 228
 229                         buck2_reg: BUCK2 {
 230                                 regulator-always-on;
 231                                 regulator-boot-on;
 232                                 regulator-compatible = "buck2";
 233                                 regulator-max-microvolt = <1300000>;
 234                                 regulator-min-microvolt = <700000>;
 235                                 regulator-ramp-delay = <1250>;
 236                         };
 237
 238                         buck5_reg: BUCK5 {
 239                                 regulator-always-on;
 240                                 regulator-boot-on;
 241                                 regulator-compatible = "buck5";
 242                                 regulator-max-microvolt = <1350000>;
 243                                 regulator-min-microvolt = <700000>;
 244                         };
 245
 246                         buck6_reg: BUCK6 {
 247                                 regulator-always-on;
 248                                 regulator-boot-on;
 249                                 regulator-compatible = "buck6";
 250                                 regulator-max-microvolt = <3300000>;
 251                                 regulator-min-microvolt = <3000000>;
 252                         };
 253
 254                         buck7_reg: BUCK7 {
 255                                 regulator-always-on;
 256                                 regulator-boot-on;
 257                                 regulator-compatible = "buck7";
 258                                 regulator-max-microvolt = <1995000>;
 259                                 regulator-min-microvolt = <1605000>;
 260                         };
 261
 262                         buck8_reg: BUCK8 {
 263                                 regulator-always-on;
 264                                 regulator-boot-on;
 265                                 regulator-compatible = "buck8";
 266                                 regulator-max-microvolt = <1400000>;
 267                                 regulator-min-microvolt = <800000>;
 268                         };
 269
 270                         ldo1_reg: LDO1 {
 271                                 regulator-always-on;
 272                                 regulator-boot-on;
 273                                 regulator-compatible = "ldo1";
 274                                 regulator-max-microvolt = <3300000>;
 275                                 regulator-min-microvolt = <3000000>;
 276                         };
 277
 278                         ldo2_reg: LDO2 {
 279                                 regulator-always-on;
 280                                 regulator-boot-on;
 281                                 regulator-compatible = "ldo2";
 282                                 regulator-max-microvolt = <900000>;
 283                                 regulator-min-microvolt = <900000>;
 284                         };
 285
 286                         ldo3_reg: LDO3 {
 287                                 regulator-always-on;
 288                                 regulator-boot-on;
 289                                 regulator-compatible = "ldo3";
 290                                 regulator-max-microvolt = <3300000>;
 291                                 regulator-min-microvolt = <1800000>;
 292                         };
 293
 294                         ldo4_reg: LDO4 {
 295                                 regulator-always-on;
 296                                 regulator-boot-on;
 297                                 regulator-compatible = "ldo4";
 298                                 regulator-max-microvolt = <1800000>;
 299                                 regulator-min-microvolt = <900000>;
 300                         };
 301
 302                         ldo5_reg: LDO5 {
 303                                 regulator-compatible = "ldo5";
 304                                 regulator-max-microvolt = <3300000>;
 305                                 regulator-min-microvolt = <3300000>;
 306                         };
 307
 308                         ldo6_reg: LDO6 {
 309                                 regulator-always-on;
 310                                 regulator-boot-on;
 311                                 regulator-compatible = "ldo6";
 312                                 regulator-max-microvolt = <1800000>;
 313                                 regulator-min-microvolt = <900000>;
 314                         };
 315                 };
 316         };
 317
 318         /* Epson RX8130 real time clock on carrier board */
 319         rtc@32 {
 320                 compatible = "epson,rx8130";
 321                 reg = <0x32>;
 322         };
 323
 324         adc@34 {
 325                 compatible = "maxim,max11607";
 326                 reg = <0x34>;
 327                 vcc-supply = <&ldo5_reg>;
 328         };
 329
 330         eeprom_module: eeprom@50 {
 331                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 332                 pagesize = <16>;
 333                 reg = <0x50>;
 334         };
 335 };
 336
 337 /* Verdin I2C_2_DSI */
 338 &i2c2 {
 339         clock-frequency = <10000>;
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_i2c2>;
 342         status = "okay";
 343 };
 344
 345 /* Verdin I2C_3_HDMI N/A */
 346
 347 /* Verdin I2C_4_CSI */
 348 &i2c3 {
 349         clock-frequency = <400000>;
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_i2c3>;
 352         status = "okay";
 353 };
 354
 355 /* Verdin I2C_1 */
 356 &i2c4 {
 357         clock-frequency = <400000>;
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_i2c4>;
 360         status = "okay";
 361
 362         /* Audio Codec */
 363         wm8904_1a: codec@1a {
 364                 compatible = "wlf,wm8904";
 365                 #sound-dai-cells = <0>;
 366                 clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
 367                 clock-names = "mclk";
 368                 reg = <0x1a>;
 369         };
 370
 371         gpio_expander_21: gpio-expander@21 {
 372                 compatible = "nxp,pcal6416";
 373                 #gpio-cells = <2>;
 374                 gpio-controller;
 375                 reg = <0x21>;
 376         };
 377
 378         /* Current measurement into module VCC */
 379         hwmon@40 {
 380                 compatible = "ti,ina219";
 381                 reg = <0x40>;
 382                 shunt-resistor = <10000>;
 383                 status = "okay";
 384         };
 385
 386         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
 387         eeprom_display_adapter: eeprom@50 {
 388                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 389                 pagesize = <16>;
 390                 reg = <0x50>;
 391         };
 392
 393         /* EEPROM on carrier board */
 394         eeprom_carrier_board: eeprom@57 {
 395                 compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 396                 pagesize = <16>;
 397                 reg = <0x57>;
 398         };
 399 };
 400
 401 /* Verdin PWM_3_DSI */
 402 &pwm1 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_pwm_1>;
 405         #pwm-cells = <3>;
 406         status = "okay";
 407 };
 408
 409 /* Verdin PWM_1 */
 410 &pwm2 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_pwm_2>;
 413         #pwm-cells = <3>;
 414         status = "okay";
 415 };
 416
 417 /* Verdin PWM_2 */
 418 &pwm3 {
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&pinctrl_pwm_3>;
 421         #pwm-cells = <3>;
 422         status = "okay";
 423 };
 424
 425 /* Verdin UART_3, Console/Debug UART */
 426 &uart1 {
 427         fsl,uart-has-rtscts;
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_uart1>;
 430         status = "okay";
 431 };
 432
 433 /* Verdin UART_1 */
 434 &uart2 {
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_uart2>;
 437         fsl,uart-has-rtscts;
 438         status = "okay";
 439 };
 440
 441 /* Verdin UART_2 */
 442 &uart3 {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&pinctrl_uart3>;
 445         fsl,uart-has-rtscts;
 446         status = "okay";
 447 };
 448
 449 /* Verdin UART_4 */
 450 /*
 451  * resource allocated to M4 by default, must not be accessed from A-35 or you
 452  * get an OOPS
 453  */
 454 &uart4 {
 455         pinctrl-names = "default";
 456         pinctrl-0 = <&pinctrl_uart4>;
 457         status = "disabled";
 458 };
 459
 460 /* Verdin USB_1 */
 461 &usbotg1 {
 462         dr_mode = "otg";
 463         picophy,dc-vol-level-adjust = <7>;
 464         picophy,pre-emp-curr-control = <3>;
 465         vbus-supply = <&reg_usb_otg1_vbus>;
 466         status = "okay";
 467 };
 468
 469 /* Verdin USB_2 */
 470 &usbotg2 {
 471         dr_mode = "host";
 472         picophy,dc-vol-level-adjust = <7>;
 473         picophy,pre-emp-curr-control = <3>;
 474         vbus-supply = <&reg_usb_otg2_vbus>;
 475         status = "okay";
 476 };
 477
 478 /* On-module eMMC */
 479 &usdhc1 {
 480         bus-width = <8>;
 481         keep-power-in-suspend;
 482         non-removable;
 483         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 484         pinctrl-0 = <&pinctrl_usdhc1>;
 485         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 486         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 487         pm-ignore-notify;
 488         status = "okay";
 489         /* TODO Strobe */
 490 };
 491
 492 /* Verdin SD_1 */
 493 &usdhc2 {
 494         bus-width = <4>;
 495         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 496         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 497         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 498         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 499         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 500         vmmc-supply = <&reg_usdhc2_vmmc>;
 501         status = "okay";
 502 };
 503
 504 /* On-module Wi-Fi */
 505 &usdhc3 {
 506         bus-width = <4>;
 507         non-removable;
 508         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 509         pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
 510         pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
 511         pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
 512         vmmc-supply = <&reg_wifi_en>;
 513         status = "okay";
 514 };
 515
 516 &wdog1 {
 517         fsl,ext-reset-output;
 518         pinctrl-names = "default";
 519         pinctrl-0 = <&pinctrl_wdog>;
 520         status = "okay";
 521 };
 522
 523 &iomuxc {
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,
 526                     <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,
 527                     <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,
 528                     <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,
 529                     <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;
 530
 531         pinctrl_can1_int: can1intgrp {
 532                 fsl,pins = <
 533                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x1c4
 534                 >;
 535         };
 536
 537         pinctrl_can2_int: can2intgrp {
 538                 fsl,pins = <
 539                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x1c4
 540                 >;
 541         };
 542
 543         pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {
 544                 fsl,pins = <
 545                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20        0x1c4           /* SODIMM 250 */
 546                 >;
 547         };
 548
 549         pinctrl_dsi_bkl_en: dsi_bkl_en {
 550                 fsl,pins = <
 551                         MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3       0x1c4           /* SODIMM 21 */
 552                 >;
 553         };
 554
 555         pinctrl_ecspi2: ecspi2grp {
 556                 fsl,pins = <
 557                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x1c4           /* SODIMM 198 */
 558                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x4             /* SODIMM 200 */
 559                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x4             /* SODIMM 196 */
 560                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x1c4           /* SODIMM 202 */
 561                 >;
 562         };
 563
 564         pinctrl_ecspi3: ecspi3grp {
 565                 fsl,pins = <
 566                         MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x1c4
 567                         MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK      0x4
 568                         MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI      0x4
 569                         MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO      0x1c4
 570                         MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25       0x1c4
 571                 >;
 572         };
 573
 574         pinctrl_fec1: fec1grp {
 575                 fsl,pins = <
 576                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 577                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 578                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 579                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 580                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 581                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 582                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 583                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 584                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 585                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 586                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 587                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 588                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 589                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 590                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x1c4
 591                 >;
 592         };
 593
 594         pinctrl_fec1_sleep: fec1-sleepgrp {
 595                 fsl,pins = <
 596                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 597                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 598                         MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                0x1f
 599                         MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                0x1f
 600                         MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                0x1f
 601                         MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                0x1f
 602                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 603                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 604                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 605                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 606                         MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                0x1f
 607                         MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x1f
 608                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 609                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 610                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x184
 611                 >;
 612         };
 613
 614         pinctrl_flexspi0: flexspi0grp {
 615                 fsl,pins = <
 616                         MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x1c2           /* SODIMM 52 */
 617                         MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82            /* SODIMM 54 */
 618                         MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B    0x82            /* SODIMM 64 */
 619                         MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82            /* SODIMM 56 */
 620                         MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82            /* SODIMM 58 */
 621                         MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82            /* SODIMM 60 */
 622                         MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82            /* SODIMM 62 */
 623                         MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS        0x82            /* SODIMM 66 */
 624                 >;
 625         };
 626
 627         /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
 628         pinctrl_gpio1: gpio1grp {
 629                 fsl,pins = <
 630                         MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4       0x184           /* SODIMM 206 */
 631                 >;
 632         };
 633
 634         pinctrl_gpio2: gpio2grp {
 635                 fsl,pins = <
 636                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x184           /* SODIMM 208 */
 637                 >;
 638         };
 639
 640         pinctrl_gpio3: gpio3grp {
 641                 fsl,pins = <
 642                         MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26       0x184           /* SODIMM 210 */
 643                 >;
 644         };
 645
 646         pinctrl_gpio4: gpio4grp {
 647                 fsl,pins = <
 648                         MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27       0x184           /* SODIMM 212 */
 649                 >;
 650         };
 651
 652         pinctrl_gpio5: gpio5grp {
 653                 fsl,pins = <
 654                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x184           /* SODIMM 216 */
 655                 >;
 656         };
 657
 658         pinctrl_gpio6: gpio6grp {
 659                 fsl,pins = <
 660                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x184           /* SODIMM 218 */
 661                 >;
 662         };
 663
 664         pinctrl_gpio7: gpio7grp {
 665                 fsl,pins = <
 666                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x184           /* SODIMM 220 */
 667                 >;
 668         };
 669
 670         pinctrl_gpio8: gpio8grp {
 671                 fsl,pins = <
 672                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x184           /* SODIMM 222 */
 673                 >;
 674         };
 675
 676         pinctrl_gpio_hog1: gpiohog1grp {
 677                 fsl,pins = <
 678                         MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20       0x1c4           /* SODIMM 88 */
 679                         MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1         0x1c4           /* SODIMM 90 */
 680                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x1c4           /* SODIMM 92 */
 681                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x1c4           /* SODIMM 94 */
 682                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x1c4           /* SODIMM 96 */
 683                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x1c4           /* SODIMM 100 */
 684                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x1c4           /* SODIMM 102 */
 685                         MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11        0x1c4           /* SODIMM 104 */
 686                         MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12       0x1c4           /* SODIMM 106 */
 687                         MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13       0x1c4           /* SODIMM 108 */
 688                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14       0x1c4           /* SODIMM 112 */
 689                         MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15       0x1c4           /* SODIMM 114 */
 690                         MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x1c4           /* SODIMM 116 */
 691                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x1c4           /* SODIMM 118 */
 692                         MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10       0x1c4           /* SODIMM 120 */
 693                 >;
 694         };
 695
 696         pinctrl_gpio_hog2: gpiohog2grp {
 697                 fsl,pins = <
 698                         MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2        0x1c4           /* SODIMM 91 */
 699                 >;
 700         };
 701
 702         pinctrl_gpio_hog3: gpiohog3grp {
 703                 fsl,pins = <
 704                         MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13      0x1c4           /* SODIMM 157 */
 705                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4           /* SODIMM 187 */
 706                 >;
 707         };
 708
 709         /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
 710         pinctrl_gpio_hpd: gpiohpdgrp {
 711                 fsl,pins = <
 712                         MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15       0x184           /* SODIMM 17 */
 713                 >;
 714         };
 715
 716         /* On-module I2C */
 717         pinctrl_i2c1: i2c1grp {
 718                 fsl,pins = <
 719                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c6
 720                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c6
 721                 >;
 722         };
 723
 724         /* Verdin I2C_4_CSI */
 725         pinctrl_i2c2: i2c2grp {
 726                 fsl,pins = <
 727                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c6      /* SODIMM 55 */
 728                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c6      /* SODIMM 53 */
 729                 >;
 730         };
 731
 732         /* Verdin I2C_2_DSI */
 733         pinctrl_i2c3: i2c3grp {
 734                 fsl,pins = <
 735                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c6      /* SODIMM 95 */
 736                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c6      /* SODIMM 93 */
 737                 >;
 738         };
 739
 740         /* Verdin I2C_1 */
 741         pinctrl_i2c4: i2c4grp {
 742                 fsl,pins = <
 743                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL          0x400001c6      /* SODIMM 14 */
 744                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA          0x400001c6      /* SODIMM 12 */
 745                 >;
 746         };
 747
 748         pinctrl_pcie0: pcie0grp {
 749                 fsl,pins = <
 750                         MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19       0x6             /* SODIMM 244 */
 751                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x6             /* PMIC_EN_PCIe_CLK */
 752                 >;
 753         };
 754
 755         pinctrl_pmic: pmicirqgrp {
 756                 fsl,pins = <
 757                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 758                 >;
 759         };
 760
 761         pinctrl_pwm_1: pwm1grp {
 762                 fsl,pins = <
 763                         MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT        0x6             /* SODIMM 19 */
 764                 >;
 765         };
 766
 767         pinctrl_pwm_2: pwm2grp {
 768                 fsl,pins = <
 769                         MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT          0x6             /* SODIMM 15 */
 770                 >;
 771         };
 772
 773         pinctrl_pwm_3: pwm3grp {
 774                 fsl,pins = <
 775                         MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT          0x6             /* SODIMM 16 */
 776                 >;
 777         };
 778
 779         pinctrl_reg_eth: regethgrp {
 780                 fsl,pins = <
 781                         MX8MM_IOMUXC_SD2_WP_GPIO2_IO20          0x184
 782                 >;
 783         };
 784
 785         pinctrl_reg_usb1_en: regusb1engrp {
 786                 fsl,pins = <
 787                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x184           /* SODIMM 155 */
 788                 >;
 789         };
 790
 791         pinctrl_reg_usb2_en: regusb2engrp {
 792                 fsl,pins = <
 793                         MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14      0x184           /* SODIMM 185 */
 794                 >;
 795         };
 796
 797         pinctrl_sai2: sai2grp {
 798                 fsl,pins = <
 799                         MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6            /* SODIMM 38 */
 800                         MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6            /* SODIMM 36 */
 801                         MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6            /* SODIMM 30 */
 802                         MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6            /* SODIMM 34 */
 803                         MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6            /* SODIMM 32 */
 804                 >;
 805         };
 806
 807         pinctrl_sai5: sai5grp {
 808                 fsl,pins = <
 809                         MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0    0xd6            /* SODIMM 48 */
 810                         MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC     0xd6            /* SODIMM 44 */
 811                         MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK     0xd6            /* SODIMM 42 */
 812                         MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0    0xd6            /* SODIMM 46 */
 813                 >;
 814         };
 815
 816         pinctrl_se050_ena: se050enagrp {
 817                 fsl,pins = <
 818                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19       0x184
 819                 >;
 820         };
 821
 822         pinctrl_uart1: uart1grp {
 823                 fsl,pins = <
 824                         MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX      0x1c4           /* SODIMM 147 */
 825                         MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX     0x1c4           /* SODIMM 149 */
 826                 >;
 827         };
 828
 829         pinctrl_uart2: uart2grp {
 830                 fsl,pins = <
 831                         MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B   0x1c4           /* SODIMM 133 */
 832                         MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B   0x1c4           /* SODIMM 135 */
 833                         MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX      0x1c4           /* SODIMM 131 */
 834                         MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX     0x1c4           /* SODIMM 129 */
 835                 >;
 836         };
 837
 838         pinctrl_uart3: uart3grp {
 839                 fsl,pins = <
 840                         MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B        0x1c4   /* SODIMM 141 */
 841                         MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX           0x1c4   /* SODIMM 139 */
 842                         MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX           0x1c4   /* SODIMM 137 */
 843                         MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B         0x1c4   /* SODIMM 143 */
 844                 >;
 845         };
 846
 847         pinctrl_uart4: uart4grp {
 848                 fsl,pins = <
 849                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x1c4           /* SODIMM 151 */
 850                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x1c4           /* SODIMM 153 */
 851                 >;
 852         };
 853
 854         pinctrl_usdhc1: usdhc1grp {
 855                 fsl,pins = <
 856                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 857                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 858                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 859                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 860                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 861                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 862                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d0
 863                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d0
 864                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d0
 865                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d0
 866                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x190
 867                 >;
 868         };
 869
 870         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 871                 fsl,pins = <
 872                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 873                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 874                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 875                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 876                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 877                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 878                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d4
 879                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d4
 880                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d4
 881                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d4
 882                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x194
 883                 >;
 884         };
 885
 886         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 887                 fsl,pins = <
 888                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 889                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 890                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 891                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 892                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 893                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 894                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d6
 895                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d6
 896                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d6
 897                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d6
 898                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE   0x196
 899                 >;
 900         };
 901
 902         pinctrl_usdhc2_cd: usdhc2cdgrp {
 903                 fsl,pins = <
 904                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4           /* SODIMM 84 */
 905                 >;
 906         };
 907
 908         pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
 909                 fsl,pins = <
 910                         MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5         0x184           /* SODIMM 76 */
 911                 >;
 912         };
 913
 914         pinctrl_usdhc2: usdhc2grp {
 915                 fsl,pins = <
 916                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 917                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190           /* SODIMM 78 */
 918                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0           /* SODIMM 74 */
 919                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0           /* SODIMM 80 */
 920                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0           /* SODIMM 82 */
 921                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0           /* SODIMM 70 */
 922                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0           /* SODIMM 72 */
 923                 >;
 924         };
 925
 926         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 927                 fsl,pins = <
 928                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 929                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 930                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 931                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 932                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 933                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 934                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 935                 >;
 936         };
 937
 938         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 939                 fsl,pins = <
 940                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 941                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 942                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 943                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 944                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 945                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 946                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 947                 >;
 948         };
 949
 950         pinctrl_usdhc3: usdhc3grp {
 951                 fsl,pins = <
 952                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 953                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 954                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 955                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 956                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 957                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 958                 >;
 959         };
 960
 961         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 962                 fsl,pins = <
 963                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 964                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 965                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 966                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 967                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 968                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 969                 >;
 970         };
 971
 972         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 973                 fsl,pins = <
 974                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 975                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 976                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 977                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 978                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 979                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 980                 >;
 981         };
 982
 983         pinctrl_wdog: wdoggrp {
 984                 fsl,pins = <
 985                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 986                 >;
 987         };
 988
 989         pinctrl_wifi_ctrl: wifictrlgrp {
 990                 fsl,pins = <
 991                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x1c4           /* WIFI_WKUP_BT */
 992                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9        0x1c4           /* WIFI_W_WKUP_HOST */
 993                         MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x1c4           /* WIFI_WKUP_WLAN */
 994                 >;
 995         };
 996
 997         pinctrl_wifi_i2s: wifii2sgrp {
 998                 fsl,pins = <
 999                         MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK     0xd6
1000                         MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0    0xd6
1001                         MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC     0xd6
1002                         MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0    0xd6
1003                 >;
1004         };
1005
1006         pinctrl_wifi_pwr_en: wifipwrengrp {
1007                 fsl,pins = <
1008                         MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25       0x184           /* PMIC_EN_WIFI */
1009                 >;
1010         };
1011 };