arch/arm/dts/imx8mm-venice-gw72xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         aliases {
  11                 usb0 = &usbotg1;
  12                 usb1 = &usbotg2;
  13         };
  14
  15         led-controller {
  16                 compatible = "gpio-leds";
  17                 pinctrl-names = "default";
  18                 pinctrl-0 = <&pinctrl_gpio_leds>;
  19
  20                 led-0 {
  21                         function = LED_FUNCTION_STATUS;
  22                         color = <LED_COLOR_ID_GREEN>;
  23                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  24                         default-state = "on";
  25                         linux,default-trigger = "heartbeat";
  26                 };
  27
  28                 led-1 {
  29                         function = LED_FUNCTION_STATUS;
  30                         color = <LED_COLOR_ID_RED>;
  31                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  32                         default-state = "off";
  33                 };
  34         };
  35
  36         pps {
  37                 compatible = "pps-gpio";
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&pinctrl_pps>;
  40                 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
  41                 status = "okay";
  42         };
  43
  44         reg_3p3v: regulator-3p3v {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "3P3V";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49                 regulator-always-on;
  50         };
  51
  52         reg_usb_otg1_vbus: regulator-usb-otg1 {
  53                 pinctrl-names = "default";
  54                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "usb_otg1_vbus";
  57                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  58                 enable-active-high;
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61         };
  62
  63         reg_usb_otg2_vbus: regulator-usb-otg2 {
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "usb_otg2_vbus";
  68                 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  69                 enable-active-high;
  70                 regulator-min-microvolt = <5000000>;
  71                 regulator-max-microvolt = <5000000>;
  72         };
  73 };
  74
  75 /* off-board header */
  76 &ecspi2 {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&pinctrl_spi2>;
  79         cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
  80         status = "okay";
  81 };
  82
  83 &i2c2 {
  84         clock-frequency = <400000>;
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_i2c2>;
  87         status = "okay";
  88
  89         accelerometer@19 {
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&pinctrl_accel>;
  92                 compatible = "st,lis2de12";
  93                 reg = <0x19>;
  94                 st,drdy-int-pin = <1>;
  95                 interrupt-parent = <&gpio4>;
  96                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
  97                 interrupt-names = "INT1";
  98         };
  99 };
 100
 101 /* off-board header */
 102 &i2c3 {
 103         clock-frequency = <400000>;
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_i2c3>;
 106         status = "okay";
 107 };
 108
 109 /* off-board header */
 110 &sai3 {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_sai3>;
 113         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 114         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 115         assigned-clock-rates = <24576000>;
 116         status = "okay";
 117 };
 118
 119 /* GPS */
 120 &uart1 {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&pinctrl_uart1>;
 123         status = "okay";
 124 };
 125
 126 /* off-board header */
 127 &uart3 {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_uart3>;
 130         status = "okay";
 131 };
 132
 133 /* RS232 */
 134 &uart4 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_uart4>;
 137         status = "okay";
 138 };
 139
 140 &usbotg1 {
 141         dr_mode = "otg";
 142         vbus-supply = <&reg_usb_otg1_vbus>;
 143         status = "okay";
 144 };
 145
 146 &usbotg2 {
 147         dr_mode = "host";
 148         vbus-supply = <&reg_usb_otg2_vbus>;
 149         status = "okay";
 150 };
 151
 152 /* microSD */
 153 &usdhc2 {
 154         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 155         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 156         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 157         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 158         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 159         bus-width = <4>;
 160         vmmc-supply = <&reg_3p3v>;
 161         status = "okay";
 162 };
 163
 164 &iomuxc {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_hog>;
 167
 168         pinctrl_hog: hoggrp {
 169                 fsl,pins = <
 170                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* PLUG_TEST */
 171                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* PCI_USBSEL */
 172                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000041 /* PCIE_WDIS# */
 173                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIO0 */
 174                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000041 /* DIO1 */
 175                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0       0x40000104 /* RS485_TERM */
 176                         MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0        0x40000104 /* RS485 */
 177                         MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2        0x40000104 /* RS485_HALF */
 178                 >;
 179         };
 180
 181         pinctrl_accel: accelgrp {
 182                 fsl,pins = <
 183                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x159
 184                 >;
 185         };
 186
 187         pinctrl_gpio_leds: gpioledgrp {
 188                 fsl,pins = <
 189                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x19
 190                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x19
 191                 >;
 192         };
 193
 194         pinctrl_i2c3: i2c3grp {
 195                 fsl,pins = <
 196                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 197                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 198                 >;
 199         };
 200
 201         pinctrl_pps: ppsgrp {
 202                 fsl,pins = <
 203                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x41
 204                 >;
 205         };
 206
 207         pinctrl_reg_usb1_en: regusb1grp {
 208                 fsl,pins = <
 209                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x41
 210                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x41
 211                 >;
 212         };
 213
 214         pinctrl_reg_usb2_en: regusb2grp {
 215                 fsl,pins = <
 216                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8       0x41
 217                 >;
 218         };
 219
 220         pinctrl_sai3: sai3grp {
 221                 fsl,pins = <
 222                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 223                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 224                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 225                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 226                         MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
 227                 >;
 228         };
 229
 230         pinctrl_spi2: spi2grp {
 231                 fsl,pins = <
 232                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 233                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
 234                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
 235                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
 236                 >;
 237         };
 238
 239         pinctrl_uart1: uart1grp {
 240                 fsl,pins = <
 241                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 242                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 243                 >;
 244         };
 245
 246         pinctrl_uart3: uart3grp {
 247                 fsl,pins = <
 248                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 249                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 250                 >;
 251         };
 252
 253         pinctrl_uart4: uart4grp {
 254                 fsl,pins = <
 255                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 256                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 257                 >;
 258         };
 259
 260         pinctrl_usdhc1: usdhc1grp {
 261                 fsl,pins = <
 262                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 263                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 264                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 265                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 266                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 267                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 268                 >;
 269         };
 270
 271         pinctrl_usdhc2: usdhc2grp {
 272                 fsl,pins = <
 273                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 274                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 275                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 276                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 277                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 278                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 279                 >;
 280         };
 281
 282         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 283                 fsl,pins = <
 284                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 285                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 286                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 287                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 288                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 289                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 290                 >;
 291         };
 292
 293         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 294                 fsl,pins = <
 295                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 296                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 297                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 298                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 299                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 300                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 301                 >;
 302         };
 303
 304         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 305                 fsl,pins = <
 306                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 307                         MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
 308                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 309                 >;
 310         };
 311 };