arch/arm/dts/imx8mm-venice-gw700x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2020 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/net/ti-dp83867.h>
   9
  10 / {
  11         memory@40000000 {
  12                 device_type = "memory";
  13                 reg = <0x0 0x40000000 0 0x80000000>;
  14         };
  15
  16         gpio-keys {
  17                 compatible = "gpio-keys";
  18
  19                 user-pb {
  20                         label = "user_pb";
  21                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  22                         linux,code = <BTN_0>;
  23                 };
  24
  25                 user-pb1x {
  26                         label = "user_pb1x";
  27                         linux,code = <BTN_1>;
  28                         interrupt-parent = <&gsc>;
  29                         interrupts = <0>;
  30                 };
  31
  32                 key-erased {
  33                         label = "key_erased";
  34                         linux,code = <BTN_2>;
  35                         interrupt-parent = <&gsc>;
  36                         interrupts = <1>;
  37                 };
  38
  39                 eeprom-wp {
  40                         label = "eeprom_wp";
  41                         linux,code = <BTN_3>;
  42                         interrupt-parent = <&gsc>;
  43                         interrupts = <2>;
  44                 };
  45
  46                 tamper {
  47                         label = "tamper";
  48                         linux,code = <BTN_4>;
  49                         interrupt-parent = <&gsc>;
  50                         interrupts = <5>;
  51                 };
  52
  53                 switch-hold {
  54                         label = "switch_hold";
  55                         linux,code = <BTN_5>;
  56                         interrupt-parent = <&gsc>;
  57                         interrupts = <7>;
  58                 };
  59         };
  60 };
  61
  62 &A53_0 {
  63         cpu-supply = <&buck3_reg>;
  64 };
  65
  66 &A53_1 {
  67         cpu-supply = <&buck3_reg>;
  68 };
  69
  70 &A53_2 {
  71         cpu-supply = <&buck3_reg>;
  72 };
  73
  74 &A53_3 {
  75         cpu-supply = <&buck3_reg>;
  76 };
  77
  78 &ddrc {
  79         operating-points-v2 = <&ddrc_opp_table>;
  80
  81         ddrc_opp_table: opp-table {
  82                 compatible = "operating-points-v2";
  83
  84                 opp-25M {
  85                         opp-hz = /bits/ 64 <25000000>;
  86                 };
  87
  88                 opp-100M {
  89                         opp-hz = /bits/ 64 <100000000>;
  90                 };
  91
  92                 opp-750M {
  93                         opp-hz = /bits/ 64 <750000000>;
  94                 };
  95         };
  96 };
  97
  98 &fec1 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_fec1>;
 101         phy-mode = "rgmii-id";
 102         phy-handle = <&ethphy0>;
 103         status = "okay";
 104
 105         mdio {
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108
 109                 ethphy0: ethernet-phy@0 {
 110                         compatible = "ethernet-phy-ieee802.3-c22";
 111                         reg = <0>;
 112                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 113                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 114                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 115                 };
 116         };
 117 };
 118
 119 &i2c1 {
 120         clock-frequency = <100000>;
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&pinctrl_i2c1>;
 123         status = "okay";
 124
 125         gsc: gsc@20 {
 126                 compatible = "gw,gsc";
 127                 reg = <0x20>;
 128                 pinctrl-0 = <&pinctrl_gsc>;
 129                 interrupt-parent = <&gpio2>;
 130                 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 131                 interrupt-controller;
 132                 #interrupt-cells = <1>;
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135
 136                 adc {
 137                         compatible = "gw,gsc-adc";
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140
 141                         channel@6 {
 142                                 gw,mode = <0>;
 143                                 reg = <0x06>;
 144                                 label = "temp";
 145                         };
 146
 147                         channel@8 {
 148                                 gw,mode = <1>;
 149                                 reg = <0x08>;
 150                                 label = "vdd_bat";
 151                         };
 152
 153                         channel@16 {
 154                                 gw,mode = <4>;
 155                                 reg = <0x16>;
 156                                 label = "fan_tach";
 157                         };
 158
 159                         channel@82 {
 160                                 gw,mode = <2>;
 161                                 reg = <0x82>;
 162                                 label = "vdd_vin";
 163                                 gw,voltage-divider-ohms = <22100 1000>;
 164                         };
 165
 166                         channel@84 {
 167                                 gw,mode = <2>;
 168                                 reg = <0x84>;
 169                                 label = "vdd_adc1";
 170                                 gw,voltage-divider-ohms = <10000 10000>;
 171                         };
 172
 173                         channel@86 {
 174                                 gw,mode = <2>;
 175                                 reg = <0x86>;
 176                                 label = "vdd_adc2";
 177                                 gw,voltage-divider-ohms = <10000 10000>;
 178                         };
 179
 180                         channel@88 {
 181                                 gw,mode = <2>;
 182                                 reg = <0x88>;
 183                                 label = "vdd_dram";
 184                         };
 185
 186                         channel@8c {
 187                                 gw,mode = <2>;
 188                                 reg = <0x8c>;
 189                                 label = "vdd_1p2";
 190                         };
 191
 192                         channel@8e {
 193                                 gw,mode = <2>;
 194                                 reg = <0x8e>;
 195                                 label = "vdd_1p0";
 196                         };
 197
 198                         channel@90 {
 199                                 gw,mode = <2>;
 200                                 reg = <0x90>;
 201                                 label = "vdd_2p5";
 202                                 gw,voltage-divider-ohms = <10000 10000>;
 203                         };
 204
 205                         channel@92 {
 206                                 gw,mode = <2>;
 207                                 reg = <0x92>;
 208                                 label = "vdd_3p3";
 209                                 gw,voltage-divider-ohms = <10000 10000>;
 210                         };
 211
 212                         channel@98 {
 213                                 gw,mode = <2>;
 214                                 reg = <0x98>;
 215                                 label = "vdd_0p95";
 216                         };
 217
 218                         channel@9a {
 219                                 gw,mode = <2>;
 220                                 reg = <0x9a>;
 221                                 label = "vdd_1p8";
 222                         };
 223
 224                         channel@a2 {
 225                                 gw,mode = <2>;
 226                                 reg = <0xa2>;
 227                                 label = "vdd_gsc";
 228                                 gw,voltage-divider-ohms = <10000 10000>;
 229                         };
 230                 };
 231
 232                 fan-controller@0 {
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         compatible = "gw,gsc-fan";
 236                         reg = <0x0a>;
 237                 };
 238         };
 239
 240         gpio: gpio@23 {
 241                 compatible = "nxp,pca9555";
 242                 reg = <0x23>;
 243                 gpio-controller;
 244                 #gpio-cells = <2>;
 245                 interrupt-parent = <&gsc>;
 246                 interrupts = <4>;
 247         };
 248
 249         eeprom@50 {
 250                 compatible = "atmel,24c02";
 251                 reg = <0x50>;
 252                 pagesize = <16>;
 253         };
 254
 255         eeprom@51 {
 256                 compatible = "atmel,24c02";
 257                 reg = <0x51>;
 258                 pagesize = <16>;
 259         };
 260
 261         eeprom@52 {
 262                 compatible = "atmel,24c02";
 263                 reg = <0x52>;
 264                 pagesize = <16>;
 265         };
 266
 267         eeprom@53 {
 268                 compatible = "atmel,24c02";
 269                 reg = <0x53>;
 270                 pagesize = <16>;
 271         };
 272
 273         rtc@68 {
 274                 compatible = "dallas,ds1672";
 275                 reg = <0x68>;
 276         };
 277
 278         pmic@69 {
 279                 compatible = "mps,mp5416";
 280                 pinctrl-names = "default";
 281                 pinctrl-0 = <&pinctrl_pmic>;
 282                 reg = <0x69>;
 283
 284                 regulators {
 285                         /* vdd_0p95: DRAM/GPU/VPU */
 286                         buck1 {
 287                                 regulator-name = "buck1";
 288                                 regulator-min-microvolt = <800000>;
 289                                 regulator-max-microvolt = <1000000>;
 290                                 regulator-min-microamp  = <3800000>;
 291                                 regulator-max-microamp  = <6800000>;
 292                                 regulator-boot-on;
 293                                 regulator-always-on;
 294                         };
 295
 296                         /* vdd_soc */
 297                         buck2 {
 298                                 regulator-name = "buck2";
 299                                 regulator-min-microvolt = <800000>;
 300                                 regulator-max-microvolt = <900000>;
 301                                 regulator-min-microamp  = <2200000>;
 302                                 regulator-max-microamp  = <5200000>;
 303                                 regulator-boot-on;
 304                                 regulator-always-on;
 305                         };
 306
 307                         /* vdd_arm */
 308                         buck3_reg: buck3 {
 309                                 regulator-name = "buck3";
 310                                 regulator-min-microvolt = <800000>;
 311                                 regulator-max-microvolt = <1000000>;
 312                                 regulator-min-microamp  = <3800000>;
 313                                 regulator-max-microamp  = <6800000>;
 314                                 regulator-always-on;
 315                         };
 316
 317                         /* vdd_1p8 */
 318                         buck4 {
 319                                 regulator-name = "buck4";
 320                                 regulator-min-microvolt = <1800000>;
 321                                 regulator-max-microvolt = <1800000>;
 322                                 regulator-min-microamp  = <2200000>;
 323                                 regulator-max-microamp  = <5200000>;
 324                                 regulator-boot-on;
 325                                 regulator-always-on;
 326                         };
 327
 328                         /* nvcc_snvs_1p8 */
 329                         ldo1 {
 330                                 regulator-name = "ldo1";
 331                                 regulator-min-microvolt = <1800000>;
 332                                 regulator-max-microvolt = <1800000>;
 333                                 regulator-boot-on;
 334                                 regulator-always-on;
 335                         };
 336
 337                         /* vdd_snvs_0p8 */
 338                         ldo2 {
 339                                 regulator-name = "ldo2";
 340                                 regulator-min-microvolt = <800000>;
 341                                 regulator-max-microvolt = <800000>;
 342                                 regulator-boot-on;
 343                                 regulator-always-on;
 344                         };
 345
 346                         /* vdd_0p9 */
 347                         ldo3 {
 348                                 regulator-name = "ldo3";
 349                                 regulator-min-microvolt = <900000>;
 350                                 regulator-max-microvolt = <900000>;
 351                                 regulator-boot-on;
 352                                 regulator-always-on;
 353                         };
 354
 355                         /* vdd_1p8 */
 356                         ldo4 {
 357                                 regulator-name = "ldo4";
 358                                 regulator-min-microvolt = <1800000>;
 359                                 regulator-max-microvolt = <1800000>;
 360                                 regulator-boot-on;
 361                                 regulator-always-on;
 362                         };
 363                 };
 364         };
 365 };
 366
 367 &i2c2 {
 368         clock-frequency = <400000>;
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_i2c2>;
 371         status = "okay";
 372
 373         eeprom@52 {
 374                 compatible = "atmel,24c32";
 375                 reg = <0x52>;
 376                 pagesize = <32>;
 377         };
 378 };
 379
 380 /* console */
 381 &uart2 {
 382         pinctrl-names = "default";
 383         pinctrl-0 = <&pinctrl_uart2>;
 384         status = "okay";
 385 };
 386
 387 /* eMMC */
 388 &usdhc3 {
 389         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 390         pinctrl-0 = <&pinctrl_usdhc3>;
 391         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 392         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 393         bus-width = <8>;
 394         non-removable;
 395         status = "okay";
 396 };
 397
 398 &wdog1 {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_wdog>;
 401         fsl,ext-reset-output;
 402         status = "okay";
 403 };
 404
 405 &iomuxc {
 406         pinctrl_fec1: fec1grp {
 407                 fsl,pins = <
 408                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 409                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 410                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 411                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 412                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 413                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 414                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 415                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 416                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 417                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 418                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 419                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 420                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 421                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 422                         MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0                 0x19
 423                 >;
 424         };
 425
 426         pinctrl_gsc: gscgrp {
 427                 fsl,pins = <
 428                         MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x159
 429                 >;
 430         };
 431
 432         pinctrl_i2c1: i2c1grp {
 433                 fsl,pins = <
 434                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 435                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 436                 >;
 437         };
 438
 439         pinctrl_i2c2: i2c2grp {
 440                 fsl,pins = <
 441                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 442                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 443                 >;
 444         };
 445
 446         pinctrl_pmic: pmicgrp {
 447                 fsl,pins = <
 448                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
 449                 >;
 450         };
 451
 452         pinctrl_uart2: uart2grp {
 453                 fsl,pins = <
 454                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 455                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 456                 >;
 457         };
 458
 459         pinctrl_usdhc3: usdhc3grp {
 460                 fsl,pins = <
 461                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 462                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 463                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 464                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 465                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 466                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 467                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 468                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 469                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 470                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 471                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 472                 >;
 473         };
 474
 475         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 476                 fsl,pins = <
 477                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 478                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 479                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 480                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 481                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 482                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 483                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 484                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 485                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 486                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 487                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 488                 >;
 489         };
 490
 491         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 492                 fsl,pins = <
 493                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 494                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 495                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 496                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 497                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 498                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 499                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 500                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 501                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 502                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 503                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 504                 >;
 505         };
 506
 507         pinctrl_wdog: wdoggrp {
 508                 fsl,pins = <
 509                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 510                 >;
 511         };
 512 };