arch/arm/dts/imx8mm-kontron-n801x-s.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright (C) 2019 Kontron Electronics GmbH
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mm-kontron-n801x-som.dtsi"
   9 #include <dt-bindings/net/mscc-phy-vsc8531.h>
  10
  11 / {
  12         model = "Kontron i.MX8MM N801X S";
  13         compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
  14
  15         aliases {
  16                 ethernet1 = &usbnet;
  17         };
  18
  19         /* fixed crystal dedicated to mcp2515 */
  20         osc_can: clock-osc-can {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <16000000>;
  24                 clock-output-names = "osc-can";
  25         };
  26
  27         leds {
  28                 compatible = "gpio-leds";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_gpio_led>;
  31
  32                 led1 {
  33                         label = "led1";
  34                         gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
  35                         linux,default-trigger = "heartbeat";
  36                 };
  37
  38                 led2 {
  39                         label = "led2";
  40                         gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
  41                 };
  42
  43                 led3 {
  44                         label = "led3";
  45                         gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
  46                 };
  47
  48                 led4 {
  49                         label = "led4";
  50                         gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
  51                 };
  52
  53                 led5 {
  54                         label = "led5";
  55                         gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
  56                 };
  57
  58                 led6 {
  59                         label = "led6";
  60                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
  61                 };
  62         };
  63
  64         pwm-beeper {
  65                 compatible = "pwm-beeper";
  66                 pwms = <&pwm2 0 5000 0>;
  67         };
  68
  69         reg_rst_eth2: regulator-rst-eth2 {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "rst-usb-eth2";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_usb_eth2>;
  74                 gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
  75                 enable-active-high;
  76                 regulator-always-on;
  77         };
  78
  79         reg_vdd_5v: regulator-5v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "vdd-5v";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 regulator-always-on;
  85         };
  86 };
  87
  88 &ecspi2 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_ecspi2>;
  91         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  92         status = "okay";
  93
  94         can0: can@0 {
  95                 compatible = "microchip,mcp2515";
  96                 reg = <0>;
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_can>;
  99                 clocks = <&osc_can>;
 100                 interrupt-parent = <&gpio4>;
 101                 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
 102                 spi-max-frequency = <10000000>;
 103                 vdd-supply = <&reg_vdd_3v3>;
 104                 xceiver-supply = <&reg_vdd_5v>;
 105         };
 106 };
 107
 108 &ecspi3 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_ecspi3>;
 111         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 112         status = "okay";
 113 };
 114
 115 &fec1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_enet>;
 118         phy-connection-type = "rgmii-rxid";
 119         phy-handle = <&ethphy>;
 120         status = "okay";
 121
 122         mdio {
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125
 126                 ethphy: ethernet-phy@0 {
 127                         compatible = "ethernet-phy-id0007.0570";
 128                         reg = <0>;
 129                         reset-assert-us = <100>;
 130                         reset-deassert-us = <100>;
 131                         reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
 132                         vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
 133                         vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
 134                         vsc8531,led-0-combine-disable;
 135                 };
 136         };
 137 };
 138
 139 &gpio4 {
 140         dsi_mux_sel: dsi_mux_sel {
 141                 gpio-hog;
 142                 gpios = <14 GPIO_ACTIVE_HIGH>;
 143                 output-high;
 144                 line-name = "dsi-mux-sel";
 145                 pinctrl-names = "default";
 146                 pinctrl-0 = <&pinctrl_dsi_sel>;
 147         };
 148
 149         dsi_mux_oe {
 150                 gpio-hog;
 151                 gpios = <15 GPIO_ACTIVE_LOW>;
 152                 output-high;
 153                 line-name = "dsi-mux-oe";
 154                 pinctrl-names = "default";
 155                 pinctrl-0 = <&pinctrl_dsi_oe>;
 156         };
 157 };
 158
 159 &i2c4 {
 160         clock-frequency = <100000>;
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_i2c4>;
 163         status = "okay";
 164
 165         rtc@32 {
 166                 compatible = "epson,rx8900";
 167                 reg = <0x32>;
 168         };
 169 };
 170
 171 &pwm2 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_pwm2>;
 174         status = "okay";
 175 };
 176
 177 &uart1 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_uart1>;
 180         uart-has-rtscts;
 181         status = "okay";
 182 };
 183
 184 &uart2 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart2>;
 187         linux,rs485-enabled-at-boot-time;
 188         uart-has-rtscts;
 189         status = "okay";
 190 };
 191
 192 &usbotg1 {
 193         dr_mode = "otg";
 194         over-current-active-low;
 195         status = "okay";
 196 };
 197
 198 &usbotg2 {
 199         dr_mode = "host";
 200         disable-over-current;
 201         #address-cells = <1>;
 202         #size-cells = <0>;
 203         status = "okay";
 204
 205         usb1@1 {
 206                 compatible = "usb424,9514";
 207                 reg = <1>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210
 211                 usbnet: usbether@1 {
 212                         compatible = "usb424,ec00";
 213                         reg = <1>;
 214                         local-mac-address = [ 00 00 00 00 00 00 ];
 215                 };
 216         };
 217 };
 218
 219 &usdhc2 {
 220         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 221         pinctrl-0 = <&pinctrl_usdhc2>;
 222         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 223         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 224         vmmc-supply = <&reg_vdd_3v3>;
 225         vqmmc-supply = <&reg_nvcc_sd>;
 226         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 227         status = "okay";
 228 };
 229
 230 &iomuxc {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_gpio>;
 233
 234         pinctrl_can: cangrp {
 235                 fsl,pins = <
 236                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28               0x19
 237                 >;
 238         };
 239
 240         pinctrl_dsi_sel: dsiselgrp {
 241                 fsl,pins = <
 242                         MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14               0x19
 243                 >;
 244         };
 245
 246         pinctrl_dsi_oe: dsioegrp {
 247                 fsl,pins = <
 248                         MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15               0x19
 249                 >;
 250         };
 251
 252         pinctrl_ecspi2: ecspi2grp {
 253                 fsl,pins = <
 254                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x82
 255                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x82
 256                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x82
 257                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x19
 258                 >;
 259         };
 260
 261         pinctrl_ecspi3: ecspi3grp {
 262                 fsl,pins = <
 263                         MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO              0x82
 264                         MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI              0x82
 265                         MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK              0x82
 266                         MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25               0x19
 267                 >;
 268         };
 269
 270         pinctrl_enet: enetgrp {
 271                 fsl,pins = <
 272                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 273                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 274                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 275                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 276                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 277                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 278                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 279                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 280                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 281                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 282                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 283                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 284                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 285                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 286                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19 /* PHY RST */
 287                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                0x19 /* ETH IRQ */
 288                 >;
 289         };
 290
 291         pinctrl_gpio_led: gpioledgrp {
 292                 fsl,pins = <
 293                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
 294                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                0x19
 295                         MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                0x19
 296                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                0x19
 297                         MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17               0x19
 298                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18               0x19
 299                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19               0x19
 300                 >;
 301         };
 302
 303         pinctrl_gpio: gpiogrp {
 304                 fsl,pins = <
 305                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x19
 306                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x19
 307                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 308                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x19
 309                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
 310                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x19
 311                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x19
 312                         MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                0x19
 313                 >;
 314         };
 315
 316         pinctrl_i2c4: i2c4grp {
 317                 fsl,pins = <
 318                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                  0x400001c3
 319                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                  0x400001c3
 320                 >;
 321         };
 322
 323         pinctrl_pwm2: pwm2grp {
 324                 fsl,pins = <
 325                         MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                  0x19
 326                 >;
 327         };
 328
 329         pinctrl_uart1: uart1grp {
 330                 fsl,pins = <
 331                         MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x140
 332                         MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x140
 333                         MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x140
 334                         MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x140
 335                 >;
 336         };
 337
 338         pinctrl_uart2: uart2grp {
 339                 fsl,pins = <
 340                         MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x140
 341                         MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x140
 342                         MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x140
 343                         MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x140
 344                 >;
 345         };
 346
 347         pinctrl_usb_eth2: usbeth2grp {
 348                 fsl,pins = <
 349                         MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2               0x19
 350                 >;
 351         };
 352
 353         pinctrl_usdhc2: usdhc2grp {
 354                 fsl,pins = <
 355                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x190
 356                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
 357                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
 358                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
 359                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
 360                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
 361                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
 362                 >;
 363         };
 364
 365         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 366                 fsl,pins = <
 367                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
 368                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
 369                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
 370                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
 371                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
 372                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
 373                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
 374                 >;
 375         };
 376
 377         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 378                 fsl,pins = <
 379                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
 380                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
 381                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
 382                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
 383                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
 384                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
 385                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
 386                 >;
 387         };
 388 };