1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/usb/pd.h>
12 model = "FSL i.MX8MM EVK board";
13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_led>;
26 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
31 reg_usdhc2_vmmc: regulator-usdhc2 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
35 regulator-name = "VSD_3V3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
43 #sound-dai-cells = <0>;
44 compatible = "wlf,wm8524";
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_gpio_wlf>;
47 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
51 compatible = "simple-audio-card";
52 simple-audio-card,name = "wm8524-audio";
53 simple-audio-card,format = "i2s";
54 simple-audio-card,frame-master = <&cpudai>;
55 simple-audio-card,bitclock-master = <&cpudai>;
56 simple-audio-card,widgets =
57 "Line", "Left Line Out Jack",
58 "Line", "Right Line Out Jack";
59 simple-audio-card,routing =
60 "Left Line Out Jack", "LINEVOUTL",
61 "Right Line Out Jack", "LINEVOUTR";
63 cpudai: simple-audio-card,cpu {
67 simple-audio-card,codec {
68 sound-dai = <&wm8524>;
69 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
75 cpu-supply = <&buck2_reg>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_fec1>;
81 phy-mode = "rgmii-id";
82 phy-handle = <ðphy0>;
90 ethphy0: ethernet-phy@0 {
91 compatible = "ethernet-phy-ieee802.3-c22";
98 clock-frequency = <400000>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_i2c1>;
104 compatible = "rohm,bd71847";
106 pinctrl-0 = <&pinctrl_pmic>;
107 interrupt-parent = <&gpio1>;
108 interrupts = <3 GPIO_ACTIVE_LOW>;
109 rohm,reset-snvs-powered;
113 regulator-name = "BUCK1";
114 regulator-min-microvolt = <700000>;
115 regulator-max-microvolt = <1300000>;
118 regulator-ramp-delay = <1250>;
122 regulator-name = "BUCK2";
123 regulator-min-microvolt = <700000>;
124 regulator-max-microvolt = <1300000>;
127 regulator-ramp-delay = <1250>;
128 rohm,dvs-run-voltage = <1000000>;
129 rohm,dvs-idle-voltage = <900000>;
133 // BUCK5 in datasheet
134 regulator-name = "BUCK3";
135 regulator-min-microvolt = <700000>;
136 regulator-max-microvolt = <1350000>;
142 // BUCK6 in datasheet
143 regulator-name = "BUCK4";
144 regulator-min-microvolt = <3000000>;
145 regulator-max-microvolt = <3300000>;
151 // BUCK7 in datasheet
152 regulator-name = "BUCK5";
153 regulator-min-microvolt = <1605000>;
154 regulator-max-microvolt = <1995000>;
160 // BUCK8 in datasheet
161 regulator-name = "BUCK6";
162 regulator-min-microvolt = <800000>;
163 regulator-max-microvolt = <1400000>;
169 regulator-name = "LDO1";
170 regulator-min-microvolt = <3000000>;
171 regulator-max-microvolt = <3300000>;
177 regulator-name = "LDO2";
178 regulator-min-microvolt = <900000>;
179 regulator-max-microvolt = <900000>;
185 regulator-name = "LDO3";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <3300000>;
193 regulator-name = "LDO4";
194 regulator-min-microvolt = <900000>;
195 regulator-max-microvolt = <1800000>;
201 regulator-name = "LDO6";
202 regulator-min-microvolt = <900000>;
203 regulator-max-microvolt = <1800000>;
212 clock-frequency = <400000>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_i2c2>;
218 compatible = "nxp,ptn5110";
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_typec1>;
222 interrupt-parent = <&gpio2>;
227 typec1_dr_sw: endpoint {
228 remote-endpoint = <&usb1_drd_sw>;
232 typec1_con: connector {
233 compatible = "usb-c-connector";
237 try-power-role = "sink";
238 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
239 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
240 PDO_VAR(5000, 20000, 3000)>;
241 op-sink-microwatt = <15000000>;
248 clock-frequency = <400000>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_i2c3>;
254 compatible = "ti,tca6416";
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_sai3>;
264 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
265 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
266 assigned-clock-rates = <24576000>;
274 &uart2 { /* console */
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_uart2>;
289 usb1_drd_sw: endpoint {
290 remote-endpoint = <&typec1_dr_sw>;
296 pinctrl-names = "default", "state_100mhz", "state_200mhz";
297 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
298 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
299 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
300 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
302 vmmc-supply = <®_usdhc2_vmmc>;
307 pinctrl-names = "default", "state_100mhz", "state_200mhz";
308 pinctrl-0 = <&pinctrl_usdhc3>;
309 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
310 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_wdog>;
319 fsl,ext-reset-output;
324 pinctrl-names = "default";
326 pinctrl_fec1: fec1grp {
328 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
329 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
330 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
331 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
332 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
333 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
334 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
335 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
336 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
337 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
338 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
339 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
340 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
341 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
342 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
346 pinctrl_gpio_led: gpioledgrp {
348 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
352 pinctrl_gpio_wlf: gpiowlfgrp {
354 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
358 pinctrl_i2c1: i2c1grp {
360 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
361 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
365 pinctrl_i2c2: i2c2grp {
367 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
368 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
372 pinctrl_i2c3: i2c3grp {
374 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
375 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
379 pinctrl_pmic: pmicirq {
381 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
385 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
387 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
391 pinctrl_sai3: sai3grp {
393 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
394 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
395 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
396 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
400 pinctrl_typec1: typec1grp {
402 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
406 pinctrl_uart2: uart2grp {
408 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
409 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
413 pinctrl_usdhc2_gpio: usdhc2grpgpio {
415 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
419 pinctrl_usdhc2: usdhc2grp {
421 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
422 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
423 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
424 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
425 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
426 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
427 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
431 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
433 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
434 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
435 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
436 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
437 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
438 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
439 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
443 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
445 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
446 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
447 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
448 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
449 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
450 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
451 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
455 pinctrl_usdhc3: usdhc3grp {
457 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
458 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
459 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
460 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
461 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
462 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
463 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
464 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
465 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
466 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
467 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
471 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
473 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
474 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
475 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
476 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
477 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
478 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
479 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
480 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
481 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
482 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
483 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
487 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
489 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
490 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
491 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
492 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
493 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
494 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
495 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
496 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
497 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
498 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
499 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
503 pinctrl_wdog: wdoggrp {
505 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6