arch/arm/dts/imx8mm-evk-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 / {
   7         wdt-reboot {
   8                 compatible = "wdt-reboot";
   9                 wdt = <&wdog1>;
  10                 u-boot,dm-spl;
  11         };
  12 };
  13
  14 &{/soc@0} {
  15         u-boot,dm-pre-reloc;
  16         u-boot,dm-spl;
  17 };
  18
  19 &clk {
  20         u-boot,dm-spl;
  21         u-boot,dm-pre-reloc;
  22         /delete-property/ assigned-clocks;
  23         /delete-property/ assigned-clock-parents;
  24         /delete-property/ assigned-clock-rates;
  25 };
  26
  27 &osc_24m {
  28         u-boot,dm-spl;
  29         u-boot,dm-pre-reloc;
  30 };
  31
  32 &aips1 {
  33         u-boot,dm-spl;
  34         u-boot,dm-pre-reloc;
  35 };
  36
  37 &aips2 {
  38         u-boot,dm-spl;
  39 };
  40
  41 &aips3 {
  42         u-boot,dm-spl;
  43 };
  44
  45 &iomuxc {
  46         u-boot,dm-spl;
  47 };
  48
  49 &reg_usdhc2_vmmc {
  50         u-boot,off-on-delay-us = <20000>;
  51 };
  52
  53 &pinctrl_reg_usdhc2_vmmc {
  54         u-boot,dm-spl;
  55 };
  56
  57 &pinctrl_uart2 {
  58         u-boot,dm-spl;
  59 };
  60
  61 &pinctrl_usdhc2_gpio {
  62         u-boot,dm-spl;
  63 };
  64
  65 &pinctrl_usdhc2 {
  66         u-boot,dm-spl;
  67 };
  68
  69 &pinctrl_usdhc3 {
  70         u-boot,dm-spl;
  71 };
  72
  73 &gpio1 {
  74         u-boot,dm-spl;
  75 };
  76
  77 &gpio2 {
  78         u-boot,dm-spl;
  79 };
  80
  81 &gpio3 {
  82         u-boot,dm-spl;
  83 };
  84
  85 &gpio4 {
  86         u-boot,dm-spl;
  87 };
  88
  89 &gpio5 {
  90         u-boot,dm-spl;
  91 };
  92
  93 &uart2 {
  94         u-boot,dm-spl;
  95 };
  96
  97 &usdhc1 {
  98         u-boot,dm-spl;
  99 };
 100
 101 &usdhc2 {
 102         u-boot,dm-spl;
 103         sd-uhs-sdr104;
 104         sd-uhs-ddr50;
 105 };
 106
 107 &usdhc3 {
 108         u-boot,dm-spl;
 109         mmc-hs400-1_8v;
 110         mmc-hs400-enhanced-strobe;
 111 };
 112
 113 &i2c1 {
 114         u-boot,dm-spl;
 115 };
 116
 117 &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
 118         u-boot,dm-spl;
 119 };
 120
 121 &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
 122         u-boot,dm-spl;
 123 };
 124
 125 &pinctrl_i2c1 {
 126         u-boot,dm-spl;
 127 };
 128
 129 &pinctrl_pmic {
 130         u-boot,dm-spl;
 131 };
 132
 133 &fec1 {
 134         phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 135 };
 136
 137 &wdog1 {
 138         u-boot,dm-spl;
 139 };