arch/arm/dts/imx8mm-evk-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 / {
   7         wdt-reboot {
   8                 compatible = "wdt-reboot";
   9                 wdt = <&wdog1>;
  10                 u-boot,dm-spl;
  11         };
  12
  13         firmware {
  14                 optee {
  15                         compatible = "linaro,optee-tz";
  16                         method = "smc";
  17                 };
  18         };
  19 };
  20
  21 &{/soc@0} {
  22         u-boot,dm-pre-reloc;
  23         u-boot,dm-spl;
  24 };
  25
  26 &clk {
  27         u-boot,dm-spl;
  28         u-boot,dm-pre-reloc;
  29         /delete-property/ assigned-clocks;
  30         /delete-property/ assigned-clock-parents;
  31         /delete-property/ assigned-clock-rates;
  32 };
  33
  34 &osc_24m {
  35         u-boot,dm-spl;
  36         u-boot,dm-pre-reloc;
  37 };
  38
  39 &aips1 {
  40         u-boot,dm-spl;
  41         u-boot,dm-pre-reloc;
  42 };
  43
  44 &aips2 {
  45         u-boot,dm-spl;
  46 };
  47
  48 &aips3 {
  49         u-boot,dm-spl;
  50 };
  51
  52 &iomuxc {
  53         u-boot,dm-spl;
  54 };
  55
  56 &reg_usdhc2_vmmc {
  57         u-boot,off-on-delay-us = <20000>;
  58 };
  59
  60 &pinctrl_reg_usdhc2_vmmc {
  61         u-boot,dm-spl;
  62 };
  63
  64 &pinctrl_uart2 {
  65         u-boot,dm-spl;
  66 };
  67
  68 &pinctrl_usdhc2_gpio {
  69         u-boot,dm-spl;
  70 };
  71
  72 &pinctrl_usdhc2 {
  73         u-boot,dm-spl;
  74 };
  75
  76 &pinctrl_usdhc3 {
  77         u-boot,dm-spl;
  78 };
  79
  80 &gpio1 {
  81         u-boot,dm-spl;
  82 };
  83
  84 &gpio2 {
  85         u-boot,dm-spl;
  86 };
  87
  88 &gpio3 {
  89         u-boot,dm-spl;
  90 };
  91
  92 &gpio4 {
  93         u-boot,dm-spl;
  94 };
  95
  96 &gpio5 {
  97         u-boot,dm-spl;
  98 };
  99
 100 &uart2 {
 101         u-boot,dm-spl;
 102 };
 103
 104 &usdhc1 {
 105         u-boot,dm-spl;
 106 };
 107
 108 &usdhc2 {
 109         u-boot,dm-spl;
 110         sd-uhs-sdr104;
 111         sd-uhs-ddr50;
 112 };
 113
 114 &usdhc3 {
 115         u-boot,dm-spl;
 116         mmc-hs400-1_8v;
 117         mmc-hs400-enhanced-strobe;
 118 };
 119
 120 &i2c1 {
 121         u-boot,dm-spl;
 122 };
 123
 124 &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
 125         u-boot,dm-spl;
 126 };
 127
 128 &{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
 129         u-boot,dm-spl;
 130 };
 131
 132 &pinctrl_i2c1 {
 133         u-boot,dm-spl;
 134 };
 135
 136 &pinctrl_pmic {
 137         u-boot,dm-spl;
 138 };
 139
 140 &fec1 {
 141         phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 142 };
 143
 144 &wdog1 {
 145         u-boot,dm-spl;
 146 };