arch/arm/dts/imx7s-warp.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 NXP Semiconductors.
   4  * Author: Fabio Estevam <fabio.estevam@nxp.com>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/input/input.h>
  10 #include "imx7s.dtsi"
  11
  12 / {
  13         model = "Warp i.MX7 Board";
  14         compatible = "warp,imx7s-warp", "fsl,imx7s";
  15
  16         memory@80000000 {
  17                 reg = <0x80000000 0x20000000>;
  18         };
  19
  20         gpio-keys {
  21                 compatible = "gpio-keys";
  22                 pinctrl-0 = <&pinctrl_gpio>;
  23                 autorepeat;
  24
  25                 back {
  26                         label = "Back";
  27                         gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
  28                         linux,code = <KEY_BACK>;
  29                         wakeup-source;
  30                 };
  31         };
  32
  33         reg_brcm: regulator-brcm {
  34                 compatible = "regulator-fixed";
  35                 enable-active-high;
  36                 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&pinctrl_brcm_reg>;
  39                 regulator-name = "brcm_reg";
  40                 regulator-min-microvolt = <3300000>;
  41                 regulator-max-microvolt = <3300000>;
  42                 startup-delay-us = <200000>;
  43         };
  44
  45         reg_bt: regulator-bt {
  46                 compatible = "regulator-fixed";
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&pinctrl_bt_reg>;
  49                 enable-active-high;
  50                 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
  51                 regulator-name = "bt_reg";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 regulator-always-on;
  55         };
  56
  57         sound {
  58                 compatible = "simple-audio-card";
  59                 simple-audio-card,name = "imx7-sgtl5000";
  60                 simple-audio-card,format = "i2s";
  61                 simple-audio-card,bitclock-master = <&dailink_master>;
  62                 simple-audio-card,frame-master = <&dailink_master>;
  63                 simple-audio-card,cpu {
  64                         sound-dai = <&sai1>;
  65                 };
  66
  67                 dailink_master: simple-audio-card,codec {
  68                         sound-dai = <&codec>;
  69                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  70                 };
  71         };
  72 };
  73
  74 &clks {
  75         assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
  76         assigned-clock-rates = <884736000>;
  77 };
  78
  79 &i2c1 {
  80         pinctrl-names = "default";
  81         pinctrl-0 = <&pinctrl_i2c1>;
  82         status = "okay";
  83
  84         pmic: pfuze3000@8 {
  85                 compatible = "fsl,pfuze3000";
  86                 reg = <0x08>;
  87
  88                 regulators {
  89                         sw1a_reg: sw1a {
  90                                 regulator-min-microvolt = <700000>;
  91                                 regulator-max-microvolt = <1475000>;
  92                                 regulator-boot-on;
  93                                 regulator-always-on;
  94                                 regulator-ramp-delay = <6250>;
  95                         };
  96
  97                         /* use sw1c_reg to align with pfuze100/pfuze200 */
  98                         sw1c_reg: sw1b {
  99                                 regulator-min-microvolt = <700000>;
 100                                 regulator-max-microvolt = <1475000>;
 101                                 regulator-boot-on;
 102                                 regulator-always-on;
 103                                 regulator-ramp-delay = <6250>;
 104                         };
 105
 106                         sw2_reg: sw2 {
 107                                 regulator-min-microvolt = <1500000>;
 108                                 regulator-max-microvolt = <1850000>;
 109                                 regulator-boot-on;
 110                                 regulator-always-on;
 111                         };
 112
 113                         sw3a_reg: sw3 {
 114                                 regulator-min-microvolt = <900000>;
 115                                 regulator-max-microvolt = <1650000>;
 116                                 regulator-boot-on;
 117                                 regulator-always-on;
 118                         };
 119
 120                         swbst_reg: swbst {
 121                                 regulator-min-microvolt = <5000000>;
 122                                 regulator-max-microvolt = <5150000>;
 123                         };
 124
 125                         snvs_reg: vsnvs {
 126                                 regulator-min-microvolt = <1000000>;
 127                                 regulator-max-microvolt = <3000000>;
 128                                 regulator-boot-on;
 129                                 regulator-always-on;
 130                         };
 131
 132                         vref_reg: vrefddr {
 133                                 regulator-boot-on;
 134                                 regulator-always-on;
 135                         };
 136
 137                         vgen1_reg: vldo1 {
 138                                 regulator-min-microvolt = <1800000>;
 139                                 regulator-max-microvolt = <3300000>;
 140                                 regulator-always-on;
 141                         };
 142
 143                         vgen2_reg: vldo2 {
 144                                 regulator-min-microvolt = <800000>;
 145                                 regulator-max-microvolt = <1550000>;
 146                         };
 147
 148                         vgen3_reg: vccsd {
 149                                 regulator-min-microvolt = <2850000>;
 150                                 regulator-max-microvolt = <3300000>;
 151                                 regulator-always-on;
 152                         };
 153
 154                         vgen4_reg: v33 {
 155                                 regulator-min-microvolt = <2850000>;
 156                                 regulator-max-microvolt = <3300000>;
 157                                 regulator-always-on;
 158                         };
 159
 160                         vgen5_reg: vldo3 {
 161                                 regulator-min-microvolt = <1800000>;
 162                                 regulator-max-microvolt = <3300000>;
 163                                 regulator-always-on;
 164                         };
 165
 166                         vgen6_reg: vldo4 {
 167                                 regulator-min-microvolt = <1800000>;
 168                                 regulator-max-microvolt = <3300000>;
 169                                 regulator-always-on;
 170                         };
 171                 };
 172         };
 173 };
 174
 175 &i2c2 {
 176         clock-frequency = <100000>;
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_i2c2>;
 179         status = "okay";
 180 };
 181
 182 &i2c3 {
 183         clock-frequency = <100000>;
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_i2c3>;
 186         status = "okay";
 187 };
 188
 189 &i2c4 {
 190         clock-frequency = <100000>;
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_i2c4>;
 193         status = "okay";
 194
 195         codec: sgtl5000@a {
 196                 #sound-dai-cells = <0>;
 197                 reg = <0x0a>;
 198                 compatible = "fsl,sgtl5000";
 199                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 202                 VDDA-supply = <&vgen4_reg>;
 203                 VDDIO-supply = <&vgen4_reg>;
 204                 VDDD-supply = <&vgen2_reg>;
 205         };
 206
 207         mpl3115@60 {
 208                 compatible = "fsl,mpl3115";
 209                 reg = <0x60>;
 210         };
 211 };
 212
 213 &sai1 {
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&pinctrl_sai1>;
 216         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 217                           <&clks IMX7D_SAI1_ROOT_CLK>;
 218         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 219         assigned-clock-rates = <0>, <36864000>;
 220         status = "okay";
 221 };
 222
 223 &uart1 {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pinctrl_uart1>;
 226         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 227         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 228         status = "okay";
 229 };
 230
 231 &uart3  {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_uart3>;
 234         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 235         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 236         uart-has-rtscts;
 237         status = "okay";
 238 };
 239
 240 &uart6 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_uart6>;
 243         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 244         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 245         fsl,dte-mode;
 246         status = "okay";
 247 };
 248
 249 &usbotg1 {
 250         dr_mode = "peripheral";
 251         status = "okay";
 252 };
 253
 254 &usdhc1 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_usdhc1>;
 257         bus-width = <4>;
 258         keep-power-in-suspend;
 259         no-1-8-v;
 260         non-removable;
 261         vmmc-supply = <&reg_brcm>;
 262         status = "okay";
 263 };
 264
 265 &usdhc3 {
 266         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 267         pinctrl-0 = <&pinctrl_usdhc3>;
 268         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 269         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 270         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 271         assigned-clock-rates = <400000000>;
 272         bus-width = <8>;
 273         no-1-8-v;
 274         fsl,tuning-step = <2>;
 275         non-removable;
 276         status = "okay";
 277 };
 278
 279 &wdog1 {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_wdog>;
 282         fsl,ext-reset-output;
 283         status = "okay";
 284 };
 285
 286 &iomuxc {
 287         pinctrl_brcm_reg: brcmreggrp {
 288                 fsl,pins = <
 289                         MX7D_PAD_SD2_WP__GPIO5_IO10     0x14 /* WL_REG_ON */
 290                 >;
 291         };
 292
 293         pinctrl_bt_reg: btreggrp {
 294                 fsl,pins = <
 295                         MX7D_PAD_SD2_DATA3__GPIO5_IO17  0x14 /* BT_REG_ON */
 296                 >;
 297         };
 298
 299         pinctrl_gpio: gpiogrp {
 300                 fsl,pins = <
 301                         MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1     0x14
 302                 >;
 303         };
 304
 305         pinctrl_i2c1: i2c1grp {
 306                 fsl,pins = <
 307                         MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 308                         MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 309                 >;
 310         };
 311
 312         pinctrl_i2c2: i2c2grp {
 313                 fsl,pins = <
 314                         MX7D_PAD_I2C2_SDA__I2C2_SDA     0x4000007f
 315                         MX7D_PAD_I2C2_SCL__I2C2_SCL     0x4000007f
 316                 >;
 317         };
 318
 319         pinctrl_i2c3: i2c3grp {
 320                 fsl,pins = <
 321                         MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
 322                         MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
 323                 >;
 324         };
 325
 326         pinctrl_i2c4: i2c4grp {
 327                 fsl,pins = <
 328                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
 329                         MX7D_PAD_I2C4_SDA__I2C4_SDA     0x4000007f
 330                 >;
 331         };
 332
 333         pinctrl_sai1: sai1grp {
 334                 fsl,pins = <
 335                         MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
 336                         MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
 337                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 338                         MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0x30
 339                 >;
 340         };
 341
 342         pinctrl_sai1_mclk: sai1mclkgrp {
 343                 fsl,pins = <
 344                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 345                 >;
 346         };
 347
 348         pinctrl_uart1: uart1grp {
 349                 fsl,pins = <
 350                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 351                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 352                 >;
 353         };
 354
 355         pinctrl_uart3: uart3grp {
 356                 fsl,pins = <
 357                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
 358                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
 359                         MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
 360                         MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
 361                 >;
 362         };
 363
 364         pinctrl_uart6: uart6grp {
 365                 fsl,pins = <
 366                         MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
 367                         MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
 368                 >;
 369         };
 370
 371         pinctrl_usdhc1: usdhc1grp {
 372                 fsl,pins = <
 373                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 374                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 375                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 376                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 377                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 378                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 379                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
 380                 >;
 381         };
 382
 383         pinctrl_usdhc3: usdhc3grp {
 384                 fsl,pins = <
 385                         MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 386                         MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 387                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 388                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 389                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 390                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 391                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 392                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 393                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 394                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 395                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x19
 396                 >;
 397         };
 398
 399         pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 400                 fsl,pins = <
 401                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 402                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 403                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 404                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 405                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 406                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 407                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 408                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 409                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 410                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 411                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1a
 412                 >;
 413         };
 414
 415         pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 416                 fsl,pins = <
 417                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 418                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 419                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 420                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 421                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 422                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 423                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 424                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 425                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 426                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 427                         MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x1b
 428                 >;
 429         };
 430 };
 431
 432 &iomuxc_lpsr {
 433         pinctrl_wdog: wdoggrp {
 434                 fsl,pins = <
 435                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B  0x74
 436                 >;
 437         };
 438 };