arch/arm/dts/imx6ull-dart-6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
   4  * Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
   5  */
   6
   7 / {
   8         model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
   9         compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
  10
  11         memory {
  12                 reg = <0x80000000 0x20000000>;
  13         };
  14
  15         chosen {
  16                 stdout-path = &uart1;
  17         };
  18
  19         aliases {
  20                 eeprom0 = &eeprom_som;
  21         };
  22 };
  23
  24 &fec1 {
  25         pinctrl-names = "default";
  26         pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_rst &pinctrl_enet1_mdio>;
  27         phy-mode = "rmii";
  28         phy-handle = <&ethphy0>;
  29         phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
  30         phy-reset-duration = <100>;
  31         status = "okay";
  32
  33         mdio1: mdio {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 /* KSZ8081RNB (SoM) */
  38                 ethphy0: ethernet-phy@1 {
  39                         compatible = "ethernet-phy-ieee802.3-c22";
  40                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
  41                         clock-names = "rmii-ref";
  42                         micrel,led-mode = <1>;
  43                         max-speed = <100>;
  44                         reg = <1>;
  45                 };
  46         };
  47 };
  48
  49 &gpio1 {
  50         u-boot,dm-pre-reloc;
  51 };
  52
  53 &gpmi {
  54         pinctrl-names = "default";
  55         pinctrl-0 = <&pinctrl_gpmi_nand>;
  56         nand-on-flash-bbt;
  57         fsl,no-blockmark-swap;
  58         status = "disabled";
  59
  60         #address-cells = <1>;
  61         #size-cells = <1>;
  62
  63         partition@0 {
  64                 label = "uboot";
  65                 reg = <0x0 0x400000>;
  66         };
  67
  68         partition@400000 {
  69                 label = "uboot-env";
  70                 reg = <0x400000 0x100000>;
  71         };
  72
  73         partition@500000 {
  74                 label = "root";
  75                 reg = <0x500000 0x0>;
  76         };
  77 };
  78
  79 &i2c1 {
  80         clock-frequency = <100000>;
  81         pinctrl-names = "default", "gpio";
  82         pinctrl-0 = <&pinctrl_i2c1>;
  83         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  84         scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  85         sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  86         status = "okay";
  87 };
  88
  89 &i2c2 {
  90         clock-frequency = <100000>;
  91         pinctrl-names = "default", "gpio";
  92         pinctrl-0 = <&pinctrl_i2c2>;
  93         pinctrl-1 = <&pinctrl_i2c2_gpio>;
  94         scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  95         sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
  96         status = "okay";
  97         u-boot,dm-pre-reloc;
  98
  99         eeprom_som: eeprom@50 {
 100                 u-boot,dm-pre-reloc;
 101                 compatible = "atmel,24c04";
 102                 reg = <0x50>;
 103                 status = "okay";
 104         };
 105 };
 106
 107 &pwm1 {
 108         pinctrl-names = "default";
 109         pinctrl-0 = <&pinctrl_pwm1>;
 110         #pwm-cells = <3>;
 111         status = "okay";
 112 };
 113
 114 &uart1 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_uart1>;
 117         status = "okay";
 118 };
 119
 120 &usdhc1 {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&pinctrl_usdhc1>;
 123         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 124         bus-width = <0x4>;
 125         no-1-8-v;
 126         status = "okay";
 127 };
 128
 129 &usdhc2 {
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_usdhc2>;
 132         bus-width = <8>;
 133         no-1-8-v;
 134         non-removable;
 135         keep-power-in-suspend;
 136         status = "disabled";
 137 };
 138
 139 &iomuxc {
 140         pinctrl-names = "default";
 141
 142
 143         pinctrl_enet1: enet1grp {
 144                 fsl,pins = <
 145                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 146                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 147                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 148                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 149                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 150                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 151                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 152                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 153                 >;
 154         };
 155
 156         pinctrl_enet1_mdio: enet1-mdio-grp {
 157                 fsl,pins = <
 158                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
 159                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 160                 >;
 161         };
 162
 163         pinctrl_gpmi_nand: gpminandgrp {
 164                 fsl,pins = <
 165                         MX6UL_PAD_NAND_DQS__RAWNAND_DQS         0x0b0b1
 166                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 167                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 168                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 169                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 170                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 171                         MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0x0b0b1
 172                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 173                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 174                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 175                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 176                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 177                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 178                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 179                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 180                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 181                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 182                 >;
 183         };
 184
 185         pinctrl_i2c1: i2cgrp {
 186                 fsl,pins = <
 187                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 188                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 189                 >;
 190         };
 191
 192         pinctrl_i2c1_gpio: i2c1grp_gpio {
 193                 fsl,pins = <
 194                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
 195                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
 196                 >;
 197         };
 198
 199         pinctrl_i2c2: i2cgrp {
 200                 u-boot,dm-pre-reloc;
 201                 fsl,pins = <
 202                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 203                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
 204                 >;
 205         };
 206
 207         pinctrl_i2c2_gpio: i2c2grp_gpio {
 208                 u-boot,dm-pre-reloc;
 209                 fsl,pins = <
 210                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x1b8b0
 211                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31     0x1b8b0
 212                 >;
 213         };
 214
 215         pinctrl_pwm1: pwm1grp {
 216                 fsl,pins = <
 217                         MX6UL_PAD_LCD_DATA00__GPIO3_IO05        0x1b0b1
 218                 >;
 219         };
 220
 221         pinctrl_uart1: uart1grp {
 222                 fsl,pins = <
 223                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 224                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 225                 >;
 226         };
 227
 228         pinctrl_usdhc1: usdhc1grp {
 229                 fsl,pins = <
 230                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 231                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 232                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 233                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 234                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 235                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 236                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
 237
 238                 >;
 239         };
 240
 241         pinctrl_usdhc2: usdhc2grp {
 242                 fsl,pins = <
 243                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
 244                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
 245                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170f9
 246                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170f9
 247                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170f9
 248                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170f9
 249                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x170f9
 250                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x170f9
 251                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x170f9
 252                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x170f9
 253                 >;
 254         };
 255 };
 256
 257 &iomuxc_snvs {
 258         pinctrl_enet1_rst: enet1-rst-grp {
 259                 fsl,pins = <
 260                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0
 261                 >;
 262         };
 263 };