arch/arm/dts/imx6ull-colibri.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2018-2019 Toradex AG
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include "imx6ull.dtsi"
   9
  10 / {
  11         model = "Toradex Colibri iMX6ULL";
  12         compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
  13
  14         aliases {
  15                 mmc0 = &usdhc1;
  16                 usb0 = &usbotg1; /* required for ums */
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         reg_module_3v3: regulator-module-3v3 {
  24                 compatible = "regulator-fixed";
  25                 regulator-always-on;
  26                 regulator-name = "+V3.3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29         };
  30
  31         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  32                 compatible = "regulator-fixed";
  33                 regulator-always-on;
  34                 regulator-name = "+V3.3_AVDD_AUDIO";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37         };
  38
  39         reg_5v0: regulator-5v0 {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "5V";
  42                 regulator-min-microvolt = <5000000>;
  43                 regulator-max-microvolt = <5000000>;
  44         };
  45
  46         reg_sd1_vmmc: regulator-sd1-vmmc {
  47                 compatible = "regulator-gpio";
  48                 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
  51                 regulator-always-on;
  52                 regulator-name = "+V3.3_1.8_SD";
  53                 regulator-min-microvolt = <1800000>;
  54                 regulator-max-microvolt = <3300000>;
  55                 states = <1800000 0x1 3300000 0x0>;
  56                 vin-supply = <&reg_module_3v3>;
  57         };
  58
  59         reg_usbh_vbus: regulator-usbh-vbus {
  60                 compatible = "regulator-fixed";
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&pinctrl_usbh_reg>;
  63                 regulator-name = "VCC_USB[1-4]";
  64                 regulator-min-microvolt = <5000000>;
  65                 regulator-max-microvolt = <5000000>;
  66                 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
  67                 vin-supply = <&reg_5v0>;
  68         };
  69 };
  70
  71 &adc1 {
  72         num-channels = <10>;
  73         vref-supply = <&reg_module_3v3_avdd>;
  74 };
  75
  76 /* Colibri SPI */
  77 &ecspi1 {
  78         cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  81 };
  82
  83 /* Ethernet */
  84 &fec2 {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_enet2>;
  87         phy-mode = "rmii";
  88         phy-handle = <&ethphy1>;
  89         status = "okay";
  90
  91         mdio {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94
  95                 ethphy1: ethernet-phy@2 {
  96                         compatible = "ethernet-phy-ieee802.3-c22";
  97                         max-speed = <100>;
  98                         reg = <2>;
  99                 };
 100         };
 101 };
 102
 103 &gpmi {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_gpmi_nand>;
 106         nand-on-flash-bbt;
 107         nand-ecc-mode = "hw";
 108         nand-ecc-strength = <8>;
 109         nand-ecc-step-size = <512>;
 110         status = "okay";
 111 };
 112
 113 &i2c1 {
 114         pinctrl-names = "default", "gpio";
 115         pinctrl-0 = <&pinctrl_i2c1>;
 116         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 117         sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
 118         scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
 119         status = "okay";
 120 };
 121
 122 &i2c2 {
 123         pinctrl-names = "default", "gpio";
 124         pinctrl-0 = <&pinctrl_i2c2>;
 125         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 126         sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
 127         scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 128         status = "okay";
 129
 130         ad7879@2c {
 131                 compatible = "adi,ad7879-1";
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
 134                 reg = <0x2c>;
 135                 interrupt-parent = <&gpio5>;
 136                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 137                 touchscreen-max-pressure = <4096>;
 138                 adi,resistance-plate-x = <120>;
 139                 adi,first-conversion-delay = /bits/ 8 <3>;
 140                 adi,acquisition-time = /bits/ 8 <1>;
 141                 adi,median-filter-size = /bits/ 8 <2>;
 142                 adi,averaging = /bits/ 8 <1>;
 143                 adi,conversion-interval = /bits/ 8 <255>;
 144         };
 145 };
 146
 147 &lcdif {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_lcdif_dat
 150                      &pinctrl_lcdif_ctrl>;
 151 };
 152
 153 &pwm4 {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_pwm4>;
 156         #pwm-cells = <3>;
 157 };
 158
 159 &pwm5 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_pwm5>;
 162         #pwm-cells = <3>;
 163 };
 164
 165 &pwm6 {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_pwm6>;
 168         #pwm-cells = <3>;
 169 };
 170
 171 &pwm7 {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_pwm7>;
 174         #pwm-cells = <3>;
 175 };
 176
 177 &sdma {
 178         status = "okay";
 179 };
 180
 181 &snvs_pwrkey {
 182         status = "disabled";
 183 };
 184
 185 /* Colibri UART_A */
 186 &uart1 {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
 189         uart-has-rtscts;
 190         fsl,dte-mode;
 191         status = "okay";
 192 };
 193
 194 /* Colibri UART_B */
 195 &uart2 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_uart2>;
 198         uart-has-rtscts;
 199         fsl,dte-mode;
 200 };
 201
 202 /* Colibri UART_C */
 203 &uart5 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_uart5>;
 206         fsl,dte-mode;
 207 };
 208
 209 /* Colibri USBC */
 210 &usbotg1 {
 211         dr_mode = "otg";
 212         srp-disable;
 213         hnp-disable;
 214         adp-disable;
 215         status = "okay";
 216 };
 217
 218 /* Colibri USBH */
 219 &usbotg2 {
 220         dr_mode = "host";
 221         vbus-supply = <&reg_usbh_vbus>;
 222         status = "okay";
 223 };
 224
 225 /* Colibri MMC */
 226 &usdhc1 {
 227         assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
 228         assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 229         assigned-clock-rates = <0>, <198000000>;
 230         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
 231         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 232         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
 233         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 234         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 235         vmmc-supply = <&reg_sd1_vmmc>;
 236         status = "okay";
 237 };
 238
 239 &iomuxc {
 240         pinctrl_enet2: enet2-grp {
 241                 fsl,pins = <
 242                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 243                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 244                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 245                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 246                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 247                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 248                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 249                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 250                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 251                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 252                 >;
 253         };
 254
 255         pinctrl_gpio1: gpio1-grp {
 256                 fsl,pins = <
 257                         MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
 258                         MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
 259                         MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0X14 /* SODIMM 77 */
 260                         MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x14 /* SODIMM 99 */
 261                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x14 /* SODIMM 133 */
 262                         MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24     0x14 /* SODIMM 135 */
 263                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x14 /* SODIMM 100 */
 264                         MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x14 /* SODIMM 102 */
 265                         MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x14 /* SODIMM 104 */
 266                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x14 /* SODIMM 186 */
 267                 >;
 268         };
 269
 270         pinctrl_gpio2: gpio2-grp { /* Camera */
 271                 fsl,pins = <
 272                         MX6UL_PAD_CSI_DATA04__GPIO4_IO25        0x74 /* SODIMM 69 */
 273                         MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x14 /* SODIMM 75 */
 274                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x14 /* SODIMM 85 */
 275                         MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x14 /* SODIMM 96 */
 276                         MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x14 /* SODIMM 98 */
 277                 >;
 278         };
 279
 280         pinctrl_gpio3: gpio3-grp { /* CAN2 */
 281                 fsl,pins = <
 282                         MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x14 /* SODIMM 178 */
 283                         MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x14 /* SODIMM 188 */
 284                 >;
 285         };
 286
 287         pinctrl_gpio4: gpio4-grp {
 288                 fsl,pins = <
 289                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x74 /* SODIMM 65 */
 290                 >;
 291         };
 292
 293         pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
 294                 fsl,pins = <
 295                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x74 /* SODIMM 106 */
 296                 >;
 297         };
 298
 299         pinctrl_gpio6: gpio6-grp { /* Wifi pins */
 300                 fsl,pins = <
 301                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x14 /* SODIMM 89 */
 302                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x14 /* SODIMM 79 */
 303                         MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x14 /* SODIMM 81 */
 304                         MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x14 /* SODIMM 97 */
 305                         MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x14 /* SODIMM 101 */
 306                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x14 /* SODIMM 103 */
 307                         MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x14 /* SODIMM 94 */
 308                 >;
 309         };
 310
 311         pinctrl_can_int: canint-grp {
 312                 fsl,pins = <
 313                         MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0X14 /* SODIMM 73 */
 314                 >;
 315         };
 316
 317         pinctrl_ecspi1_cs: ecspi1-cs-grp {
 318                 fsl,pins = <
 319                         MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x000a0
 320                 >;
 321         };
 322
 323         pinctrl_ecspi1: ecspi1-grp {
 324                 fsl,pins = <
 325                         MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x000a0
 326                         MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x000a0
 327                         MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x100a0
 328                 >;
 329         };
 330
 331         pinctrl_flexcan2: flexcan2-grp {
 332                 fsl,pins = <
 333                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 334                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 335                 >;
 336         };
 337
 338         pinctrl_gpio_bl_on: gpio-bl-on-grp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x000a0
 341                 >;
 342         };
 343
 344         pinctrl_gpmi_nand: gpmi-nand-grp {
 345                 fsl,pins = <
 346                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
 347                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x100a9
 348                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x100a9
 349                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x100a9
 350                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x100a9
 351                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x100a9
 352                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x100a9
 353                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x100a9
 354                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x100a9
 355                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x100a9
 356                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x100a9
 357                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x100a9
 358                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x100a9
 359                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
 360                 >;
 361         };
 362
 363         pinctrl_i2c1: i2c1-grp {
 364                 fsl,pins = <
 365                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 366                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 367                 >;
 368         };
 369
 370         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 371                 fsl,pins = <
 372                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
 373                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
 374                 >;
 375         };
 376
 377         pinctrl_i2c2: i2c2-grp {
 378                 fsl,pins = <
 379                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 380                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 381                 >;
 382         };
 383
 384         pinctrl_i2c2_gpio: i2c2-gpio-grp {
 385                 fsl,pins = <
 386                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
 387                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
 388                 >;
 389         };
 390
 391         pinctrl_lcdif_dat: lcdif-dat-grp {
 392                 fsl,pins = <
 393                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
 394                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
 395                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
 396                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
 397                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
 398                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
 399                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
 400                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
 401                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
 402                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
 403                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
 404                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
 405                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
 406                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
 407                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
 408                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
 409                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
 410                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
 411                 >;
 412         };
 413
 414         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 415                 fsl,pins = <
 416                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x00079
 417                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
 418                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
 419                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
 420                 >;
 421         };
 422
 423         pinctrl_pwm4: pwm4-grp {
 424                 fsl,pins = <
 425                         MX6UL_PAD_NAND_WP_B__PWM4_OUT   0x00079
 426                 >;
 427         };
 428
 429         pinctrl_pwm5: pwm5-grp {
 430                 fsl,pins = <
 431                         MX6UL_PAD_NAND_DQS__PWM5_OUT    0x00079
 432                 >;
 433         };
 434
 435         pinctrl_pwm6: pwm6-grp {
 436                 fsl,pins = <
 437                         MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
 438                 >;
 439         };
 440
 441         pinctrl_pwm7: pwm7-grp {
 442                 fsl,pins = <
 443                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x00079
 444                 >;
 445         };
 446
 447         pinctrl_uart1: uart1-grp {
 448                 fsl,pins = <
 449                         MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX   0x1b0b1
 450                         MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX   0x1b0b1
 451                         MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS    0x1b0b1
 452                         MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS    0x1b0b1
 453                 >;
 454         };
 455
 456         pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
 457                 fsl,pins = <
 458                         MX6UL_PAD_JTAG_TDI__GPIO1_IO13          0x1b0b1 /* DCD */
 459                         MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x1b0b1 /* DSR */
 460                         MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x1b0b1 /* DTR */
 461                         MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
 462                 >;
 463         };
 464
 465         pinctrl_uart2: uart2-grp {
 466                 fsl,pins = <
 467                         MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
 468                         MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
 469                         MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1
 470                         MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1
 471                 >;
 472         };
 473         pinctrl_uart5: uart5-grp {
 474                 fsl,pins = <
 475                         MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX      0x1b0b1
 476                         MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX      0x1b0b1
 477                 >;
 478         };
 479
 480         pinctrl_usbh_reg: gpio-usbh-reg {
 481                 fsl,pins = <
 482                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x1b0b1 /* SODIMM 129 USBH PEN */
 483                 >;
 484         };
 485
 486         pinctrl_usdhc1: usdhc1-grp {
 487                 fsl,pins = <
 488                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17059
 489                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x10059
 490                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 491                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 492                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 493                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 494                 >;
 495         };
 496
 497         pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
 498                 fsl,pins = <
 499                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170b9
 500                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100b9
 501                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 502                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 503                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 504                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 505                 >;
 506         };
 507
 508         pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
 509                 fsl,pins = <
 510                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170f9
 511                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100f9
 512                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 513                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 514                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 515                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 516                 >;
 517         };
 518
 519         pinctrl_usdhc2: usdhc2-grp {
 520                 fsl,pins = <
 521                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
 522                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
 523                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
 524                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
 525                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
 526                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x17059
 527
 528                         MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT    0x14
 529                 >;
 530         };
 531 };
 532
 533 &iomuxc_snvs {
 534         pinctrl_snvs_gpio1: snvs-gpio1-grp {
 535                 fsl,pins = <
 536                         MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x14 /* SODIMM 93 */
 537                         MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x14 /* SODIMM 95 */
 538                         MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x74 /* SODIMM 105 */
 539                         MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x14 /* SODIMM 131 USBH OC */
 540                         MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x74 /* SODIMM 138 */
 541                 >;
 542         };
 543
 544         pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
 545                 fsl,pins = <
 546                         MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0x74 /* SODIMM 107 */
 547                 >;
 548         };
 549
 550         pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
 551                 fsl,pins = <
 552                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14 /* SODIMM 127 */
 553                 >;
 554         };
 555
 556         pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
 557                 fsl,pins = <
 558                         MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x1b0b0
 559                 >;
 560         };
 561
 562         pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
 563                 fsl,pins = <
 564                         MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x4001b8b0
 565                 >;
 566         };
 567
 568         pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
 569                 fsl,pins = <
 570                         MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x1b0b0
 571                 >;
 572         };
 573
 574         pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
 575                 fsl,pins = <
 576                         MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x130b0
 577                 >;
 578         };
 579
 580         pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
 581                 fsl,pins = <
 582                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0 /* CD */
 583                 >;
 584         };
 585
 586         pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
 587                 fsl,pins = <
 588                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14
 589                 >;
 590         };
 591 };