arch/arm/dts/imx6ul.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6ul-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6ul-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 ethernet1 = &fec2;
  24                 gpio0 = &gpio1;
  25                 gpio1 = &gpio2;
  26                 gpio2 = &gpio3;
  27                 gpio3 = &gpio4;
  28                 gpio4 = &gpio5;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 i2c3 = &i2c4;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 serial5 = &uart6;
  41                 serial6 = &uart7;
  42                 serial7 = &uart8;
  43                 sai1 = &sai1;
  44                 sai2 = &sai2;
  45                 sai3 = &sai3;
  46                 spi0 = &qspi;
  47                 spi1 = &ecspi1;
  48                 spi2 = &ecspi2;
  49                 spi3 = &ecspi3;
  50                 spi4 = &ecspi4;
  51                 usbphy0 = &usbphy1;
  52                 usbphy1 = &usbphy2;
  53                 usb0 = &usbotg1;
  54                 usb1 = &usbotg2;
  55         };
  56
  57         cpus {
  58                 #address-cells = <1>;
  59                 #size-cells = <0>;
  60
  61                 cpu0: cpu@0 {
  62                         compatible = "arm,cortex-a7";
  63                         device_type = "cpu";
  64                         reg = <0>;
  65                         clock-latency = <61036>; /* two CLK32 periods */
  66                         #cooling-cells = <2>;
  67                         operating-points = <
  68                                 /* kHz  uV */
  69                                 696000  1275000
  70                                 528000  1175000
  71                                 396000  1025000
  72                                 198000  950000
  73                         >;
  74                         fsl,soc-operating-points = <
  75                                 /* KHz  uV */
  76                                 696000  1275000
  77                                 528000  1175000
  78                                 396000  1175000
  79                                 198000  1175000
  80                         >;
  81                         clocks = <&clks IMX6UL_CLK_ARM>,
  82                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  83                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  84                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  85                                  <&clks IMX6UL_CLK_STEP>,
  86                                  <&clks IMX6UL_CLK_PLL1_SW>,
  87                                  <&clks IMX6UL_CLK_PLL1_SYS>;
  88                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  89                                       "secondary_sel", "step", "pll1_sw",
  90                                       "pll1_sys";
  91                         arm-supply = <&reg_arm>;
  92                         soc-supply = <&reg_soc>;
  93                         nvmem-cells = <&cpu_speed_grade>;
  94                         nvmem-cell-names = "speed_grade";
  95                 };
  96         };
  97
  98         intc: interrupt-controller@a01000 {
  99                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
 100                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 101                 #interrupt-cells = <3>;
 102                 interrupt-controller;
 103                 interrupt-parent = <&intc>;
 104                 reg = <0x00a01000 0x1000>,
 105                       <0x00a02000 0x2000>,
 106                       <0x00a04000 0x2000>,
 107                       <0x00a06000 0x2000>;
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv7-timer";
 112                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 113                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 114                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 115                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 116                 interrupt-parent = <&intc>;
 117                 status = "disabled";
 118         };
 119
 120         ckil: clock-cli {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <32768>;
 124                 clock-output-names = "ckil";
 125         };
 126
 127         osc: clock-osc {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <24000000>;
 131                 clock-output-names = "osc";
 132         };
 133
 134         ipp_di0: clock-di0 {
 135                 compatible = "fixed-clock";
 136                 #clock-cells = <0>;
 137                 clock-frequency = <0>;
 138                 clock-output-names = "ipp_di0";
 139         };
 140
 141         ipp_di1: clock-di1 {
 142                 compatible = "fixed-clock";
 143                 #clock-cells = <0>;
 144                 clock-frequency = <0>;
 145                 clock-output-names = "ipp_di1";
 146         };
 147
 148         tempmon: tempmon {
 149                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 150                 interrupt-parent = <&gpc>;
 151                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 152                 fsl,tempmon = <&anatop>;
 153                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 154                 nvmem-cell-names = "calib", "temp_grade";
 155                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 156         };
 157
 158         pmu {
 159                 compatible = "arm,cortex-a7-pmu";
 160                 interrupt-parent = <&gpc>;
 161                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 162         };
 163
 164         soc {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 compatible = "simple-bus";
 168                 interrupt-parent = <&gpc>;
 169                 ranges;
 170
 171                 ocram: sram@900000 {
 172                         compatible = "mmio-sram";
 173                         reg = <0x00900000 0x20000>;
 174                 };
 175
 176                 dma_apbh: dma-apbh@1804000 {
 177                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 178                         reg = <0x01804000 0x2000>;
 179                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 183                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 184                         #dma-cells = <1>;
 185                         dma-channels = <4>;
 186                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 187                 };
 188
 189                 gpmi: gpmi-nand@1806000 {
 190                         compatible = "fsl,imx6q-gpmi-nand";
 191                         #address-cells = <1>;
 192                         #size-cells = <1>;
 193                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 194                         reg-names = "gpmi-nand", "bch";
 195                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 196                         interrupt-names = "bch";
 197                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 198                                  <&clks IMX6UL_CLK_GPMI_APB>,
 199                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 200                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 201                                  <&clks IMX6UL_CLK_PER_BCH>;
 202                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 203                                       "gpmi_bch_apb", "per1_bch";
 204                         dmas = <&dma_apbh 0>;
 205                         dma-names = "rx-tx";
 206                         status = "disabled";
 207                 };
 208
 209                 aips1: aips-bus@2000000 {
 210                         compatible = "fsl,aips-bus", "simple-bus";
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         reg = <0x02000000 0x100000>;
 214                         ranges;
 215
 216                         spba-bus@2000000 {
 217                                 compatible = "fsl,spba-bus", "simple-bus";
 218                                 #address-cells = <1>;
 219                                 #size-cells = <1>;
 220                                 reg = <0x02000000 0x40000>;
 221                                 ranges;
 222
 223                                 ecspi1: spi@2008000 {
 224                                         #address-cells = <1>;
 225                                         #size-cells = <0>;
 226                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 227                                         reg = <0x02008000 0x4000>;
 228                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 229                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 230                                                  <&clks IMX6UL_CLK_ECSPI1>;
 231                                         clock-names = "ipg", "per";
 232                                         status = "disabled";
 233                                 };
 234
 235                                 ecspi2: spi@200c000 {
 236                                         #address-cells = <1>;
 237                                         #size-cells = <0>;
 238                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 239                                         reg = <0x0200c000 0x4000>;
 240                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 241                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 242                                                  <&clks IMX6UL_CLK_ECSPI2>;
 243                                         clock-names = "ipg", "per";
 244                                         status = "disabled";
 245                                 };
 246
 247                                 ecspi3: spi@2010000 {
 248                                         #address-cells = <1>;
 249                                         #size-cells = <0>;
 250                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 251                                         reg = <0x02010000 0x4000>;
 252                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 253                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 254                                                  <&clks IMX6UL_CLK_ECSPI3>;
 255                                         clock-names = "ipg", "per";
 256                                         status = "disabled";
 257                                 };
 258
 259                                 ecspi4: spi@2014000 {
 260                                         #address-cells = <1>;
 261                                         #size-cells = <0>;
 262                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 263                                         reg = <0x02014000 0x4000>;
 264                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 265                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 266                                                  <&clks IMX6UL_CLK_ECSPI4>;
 267                                         clock-names = "ipg", "per";
 268                                         status = "disabled";
 269                                 };
 270
 271                                 uart7: serial@2018000 {
 272                                         compatible = "fsl,imx6ul-uart",
 273                                                      "fsl,imx6q-uart";
 274                                         reg = <0x02018000 0x4000>;
 275                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 276                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 277                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 278                                         clock-names = "ipg", "per";
 279                                         status = "disabled";
 280                                 };
 281
 282                                 uart1: serial@2020000 {
 283                                         compatible = "fsl,imx6ul-uart",
 284                                                      "fsl,imx6q-uart";
 285                                         reg = <0x02020000 0x4000>;
 286                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 287                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 288                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 289                                         clock-names = "ipg", "per";
 290                                         status = "disabled";
 291                                 };
 292
 293                                 uart8: serial@2024000 {
 294                                         compatible = "fsl,imx6ul-uart",
 295                                                      "fsl,imx6q-uart";
 296                                         reg = <0x02024000 0x4000>;
 297                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 298                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 299                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 300                                         clock-names = "ipg", "per";
 301                                         status = "disabled";
 302                                 };
 303
 304                                 sai1: sai@2028000 {
 305                                         #sound-dai-cells = <0>;
 306                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 307                                         reg = <0x02028000 0x4000>;
 308                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 309                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 310                                                  <&clks IMX6UL_CLK_SAI1>,
 311                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 312                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 313                                         dmas = <&sdma 35 24 0>,
 314                                                <&sdma 36 24 0>;
 315                                         dma-names = "rx", "tx";
 316                                         status = "disabled";
 317                                 };
 318
 319                                 sai2: sai@202c000 {
 320                                         #sound-dai-cells = <0>;
 321                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 322                                         reg = <0x0202c000 0x4000>;
 323                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 324                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 325                                                  <&clks IMX6UL_CLK_SAI2>,
 326                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 327                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 328                                         dmas = <&sdma 37 24 0>,
 329                                                <&sdma 38 24 0>;
 330                                         dma-names = "rx", "tx";
 331                                         status = "disabled";
 332                                 };
 333
 334                                 sai3: sai@2030000 {
 335                                         #sound-dai-cells = <0>;
 336                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 337                                         reg = <0x02030000 0x4000>;
 338                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 339                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 340                                                  <&clks IMX6UL_CLK_SAI3>,
 341                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 342                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 343                                         dmas = <&sdma 39 24 0>,
 344                                                <&sdma 40 24 0>;
 345                                         dma-names = "rx", "tx";
 346                                         status = "disabled";
 347                                 };
 348                         };
 349
 350                         tsc: tsc@2040000 {
 351                                 compatible = "fsl,imx6ul-tsc";
 352                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 353                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 354                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 355                                 clocks = <&clks IMX6UL_CLK_IPG>,
 356                                          <&clks IMX6UL_CLK_ADC2>;
 357                                 clock-names = "tsc", "adc";
 358                                 status = "disabled";
 359                         };
 360
 361                         pwm1: pwm@2080000 {
 362                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 363                                 reg = <0x02080000 0x4000>;
 364                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 365                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 366                                          <&clks IMX6UL_CLK_PWM1>;
 367                                 clock-names = "ipg", "per";
 368                                 #pwm-cells = <2>;
 369                                 status = "disabled";
 370                         };
 371
 372                         pwm2: pwm@2084000 {
 373                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 374                                 reg = <0x02084000 0x4000>;
 375                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 377                                          <&clks IMX6UL_CLK_PWM2>;
 378                                 clock-names = "ipg", "per";
 379                                 #pwm-cells = <2>;
 380                                 status = "disabled";
 381                         };
 382
 383                         pwm3: pwm@2088000 {
 384                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 385                                 reg = <0x02088000 0x4000>;
 386                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 387                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 388                                          <&clks IMX6UL_CLK_PWM3>;
 389                                 clock-names = "ipg", "per";
 390                                 #pwm-cells = <2>;
 391                                 status = "disabled";
 392                         };
 393
 394                         pwm4: pwm@208c000 {
 395                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 396                                 reg = <0x0208c000 0x4000>;
 397                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 398                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 399                                          <&clks IMX6UL_CLK_PWM4>;
 400                                 clock-names = "ipg", "per";
 401                                 #pwm-cells = <2>;
 402                                 status = "disabled";
 403                         };
 404
 405                         can1: flexcan@2090000 {
 406                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 407                                 reg = <0x02090000 0x4000>;
 408                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 409                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 410                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 411                                 clock-names = "ipg", "per";
 412                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
 413                                 status = "disabled";
 414                         };
 415
 416                         can2: flexcan@2094000 {
 417                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 418                                 reg = <0x02094000 0x4000>;
 419                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 420                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 421                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 422                                 clock-names = "ipg", "per";
 423                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
 424                                 status = "disabled";
 425                         };
 426
 427                         gpt1: gpt@2098000 {
 428                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 429                                 reg = <0x02098000 0x4000>;
 430                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 431                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 432                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 433                                 clock-names = "ipg", "per";
 434                         };
 435
 436                         gpio1: gpio@209c000 {
 437                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 438                                 reg = <0x0209c000 0x4000>;
 439                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 440                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&clks IMX6UL_CLK_GPIO1>;
 442                                 gpio-controller;
 443                                 #gpio-cells = <2>;
 444                                 interrupt-controller;
 445                                 #interrupt-cells = <2>;
 446                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 447                                               <&iomuxc 16 33 16>;
 448                         };
 449
 450                         gpio2: gpio@20a0000 {
 451                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 452                                 reg = <0x020a0000 0x4000>;
 453                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 454                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 455                                 clocks = <&clks IMX6UL_CLK_GPIO2>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 461                         };
 462
 463                         gpio3: gpio@20a4000 {
 464                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 465                                 reg = <0x020a4000 0x4000>;
 466                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 467                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 468                                 clocks = <&clks IMX6UL_CLK_GPIO3>;
 469                                 gpio-controller;
 470                                 #gpio-cells = <2>;
 471                                 interrupt-controller;
 472                                 #interrupt-cells = <2>;
 473                                 gpio-ranges = <&iomuxc 0 65 29>;
 474                         };
 475
 476                         gpio4: gpio@20a8000 {
 477                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 478                                 reg = <0x020a8000 0x4000>;
 479                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 480                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 481                                 clocks = <&clks IMX6UL_CLK_GPIO4>;
 482                                 gpio-controller;
 483                                 #gpio-cells = <2>;
 484                                 interrupt-controller;
 485                                 #interrupt-cells = <2>;
 486                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 487                         };
 488
 489                         gpio5: gpio@20ac000 {
 490                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 491                                 reg = <0x020ac000 0x4000>;
 492                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 493                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 494                                 clocks = <&clks IMX6UL_CLK_GPIO5>;
 495                                 gpio-controller;
 496                                 #gpio-cells = <2>;
 497                                 interrupt-controller;
 498                                 #interrupt-cells = <2>;
 499                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 500                         };
 501
 502                         fec2: ethernet@20b4000 {
 503                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 504                                 reg = <0x020b4000 0x4000>;
 505                                 interrupt-names = "int0", "pps";
 506                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 508                                 clocks = <&clks IMX6UL_CLK_ENET>,
 509                                          <&clks IMX6UL_CLK_ENET_AHB>,
 510                                          <&clks IMX6UL_CLK_ENET_PTP>,
 511                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 512                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 513                                 clock-names = "ipg", "ahb", "ptp",
 514                                               "enet_clk_ref", "enet_out";
 515                                 fsl,num-tx-queues=<1>;
 516                                 fsl,num-rx-queues=<1>;
 517                                 status = "disabled";
 518                         };
 519
 520                         kpp: kpp@20b8000 {
 521                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 522                                 reg = <0x020b8000 0x4000>;
 523                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 524                                 clocks = <&clks IMX6UL_CLK_KPP>;
 525                                 status = "disabled";
 526                         };
 527
 528                         wdog1: wdog@20bc000 {
 529                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 530                                 reg = <0x020bc000 0x4000>;
 531                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 532                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 533                         };
 534
 535                         wdog2: wdog@20c0000 {
 536                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 537                                 reg = <0x020c0000 0x4000>;
 538                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 539                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 540                                 status = "disabled";
 541                         };
 542
 543                         clks: ccm@20c4000 {
 544                                 compatible = "fsl,imx6ul-ccm";
 545                                 reg = <0x020c4000 0x4000>;
 546                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 547                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 548                                 #clock-cells = <1>;
 549                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 550                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 551                         };
 552
 553                         anatop: anatop@20c8000 {
 554                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 555                                              "syscon", "simple-bus";
 556                                 reg = <0x020c8000 0x1000>;
 557                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 558                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 559                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 560
 561                                 reg_3p0: regulator-3p0 {
 562                                         compatible = "fsl,anatop-regulator";
 563                                         regulator-name = "vdd3p0";
 564                                         regulator-min-microvolt = <2625000>;
 565                                         regulator-max-microvolt = <3400000>;
 566                                         anatop-reg-offset = <0x120>;
 567                                         anatop-vol-bit-shift = <8>;
 568                                         anatop-vol-bit-width = <5>;
 569                                         anatop-min-bit-val = <0>;
 570                                         anatop-min-voltage = <2625000>;
 571                                         anatop-max-voltage = <3400000>;
 572                                         anatop-enable-bit = <0>;
 573                                 };
 574
 575                                 reg_arm: regulator-vddcore {
 576                                         compatible = "fsl,anatop-regulator";
 577                                         regulator-name = "cpu";
 578                                         regulator-min-microvolt = <725000>;
 579                                         regulator-max-microvolt = <1450000>;
 580                                         regulator-always-on;
 581                                         anatop-reg-offset = <0x140>;
 582                                         anatop-vol-bit-shift = <0>;
 583                                         anatop-vol-bit-width = <5>;
 584                                         anatop-delay-reg-offset = <0x170>;
 585                                         anatop-delay-bit-shift = <24>;
 586                                         anatop-delay-bit-width = <2>;
 587                                         anatop-min-bit-val = <1>;
 588                                         anatop-min-voltage = <725000>;
 589                                         anatop-max-voltage = <1450000>;
 590                                 };
 591
 592                                 reg_soc: regulator-vddsoc {
 593                                         compatible = "fsl,anatop-regulator";
 594                                         regulator-name = "vddsoc";
 595                                         regulator-min-microvolt = <725000>;
 596                                         regulator-max-microvolt = <1450000>;
 597                                         regulator-always-on;
 598                                         anatop-reg-offset = <0x140>;
 599                                         anatop-vol-bit-shift = <18>;
 600                                         anatop-vol-bit-width = <5>;
 601                                         anatop-delay-reg-offset = <0x170>;
 602                                         anatop-delay-bit-shift = <28>;
 603                                         anatop-delay-bit-width = <2>;
 604                                         anatop-min-bit-val = <1>;
 605                                         anatop-min-voltage = <725000>;
 606                                         anatop-max-voltage = <1450000>;
 607                                 };
 608                         };
 609
 610                         usbphy1: usbphy@20c9000 {
 611                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 612                                 reg = <0x020c9000 0x1000>;
 613                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 615                                 phy-3p0-supply = <&reg_3p0>;
 616                                 fsl,anatop = <&anatop>;
 617                         };
 618
 619                         usbphy2: usbphy@20ca000 {
 620                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 621                                 reg = <0x020ca000 0x1000>;
 622                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 623                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 624                                 phy-3p0-supply = <&reg_3p0>;
 625                                 fsl,anatop = <&anatop>;
 626                         };
 627
 628                         snvs: snvs@20cc000 {
 629                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 630                                 reg = <0x020cc000 0x4000>;
 631
 632                                 snvs_rtc: snvs-rtc-lp {
 633                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 634                                         regmap = <&snvs>;
 635                                         offset = <0x34>;
 636                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 637                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 638                                 };
 639
 640                                 snvs_poweroff: snvs-poweroff {
 641                                         compatible = "syscon-poweroff";
 642                                         regmap = <&snvs>;
 643                                         offset = <0x38>;
 644                                         value = <0x60>;
 645                                         mask = <0x60>;
 646                                         status = "disabled";
 647                                 };
 648
 649                                 snvs_pwrkey: snvs-powerkey {
 650                                         compatible = "fsl,sec-v4.0-pwrkey";
 651                                         regmap = <&snvs>;
 652                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 653                                         linux,keycode = <KEY_POWER>;
 654                                         wakeup-source;
 655                                 };
 656
 657                                 snvs_lpgpr: snvs-lpgpr {
 658                                         compatible = "fsl,imx6ul-snvs-lpgpr";
 659                                 };
 660                         };
 661
 662                         epit1: epit@20d0000 {
 663                                 reg = <0x020d0000 0x4000>;
 664                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 665                         };
 666
 667                         epit2: epit@20d4000 {
 668                                 reg = <0x020d4000 0x4000>;
 669                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 670                         };
 671
 672                         src: src@20d8000 {
 673                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 674                                 reg = <0x020d8000 0x4000>;
 675                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 676                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 677                                 #reset-cells = <1>;
 678                         };
 679
 680                         gpc: gpc@20dc000 {
 681                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 682                                 reg = <0x020dc000 0x4000>;
 683                                 interrupt-controller;
 684                                 #interrupt-cells = <3>;
 685                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 686                                 interrupt-parent = <&intc>;
 687                         };
 688
 689                         iomuxc: iomuxc@20e0000 {
 690                                 compatible = "fsl,imx6ul-iomuxc";
 691                                 reg = <0x020e0000 0x4000>;
 692                         };
 693
 694                         gpr: iomuxc-gpr@20e4000 {
 695                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 696                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 697                                 reg = <0x020e4000 0x4000>;
 698                         };
 699
 700                         gpt2: gpt@20e8000 {
 701                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 702                                 reg = <0x020e8000 0x4000>;
 703                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 705                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 706                                 clock-names = "ipg", "per";
 707                         };
 708
 709                         sdma: sdma@20ec000 {
 710                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 711                                              "fsl,imx35-sdma";
 712                                 reg = <0x020ec000 0x4000>;
 713                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clks IMX6UL_CLK_IPG>,
 715                                          <&clks IMX6UL_CLK_SDMA>;
 716                                 clock-names = "ipg", "ahb";
 717                                 #dma-cells = <3>;
 718                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 719                         };
 720
 721                         pwm5: pwm@20f0000 {
 722                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 723                                 reg = <0x020f0000 0x4000>;
 724                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 725                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 726                                          <&clks IMX6UL_CLK_PWM5>;
 727                                 clock-names = "ipg", "per";
 728                                 #pwm-cells = <2>;
 729                                 status = "disabled";
 730                         };
 731
 732                         pwm6: pwm@20f4000 {
 733                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 734                                 reg = <0x020f4000 0x4000>;
 735                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 736                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 737                                          <&clks IMX6UL_CLK_PWM6>;
 738                                 clock-names = "ipg", "per";
 739                                 #pwm-cells = <2>;
 740                                 status = "disabled";
 741                         };
 742
 743                         pwm7: pwm@20f8000 {
 744                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 745                                 reg = <0x020f8000 0x4000>;
 746                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 747                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 748                                          <&clks IMX6UL_CLK_PWM7>;
 749                                 clock-names = "ipg", "per";
 750                                 #pwm-cells = <2>;
 751                                 status = "disabled";
 752                         };
 753
 754                         pwm8: pwm@20fc000 {
 755                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 756                                 reg = <0x020fc000 0x4000>;
 757                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 759                                          <&clks IMX6UL_CLK_PWM8>;
 760                                 clock-names = "ipg", "per";
 761                                 #pwm-cells = <2>;
 762                                 status = "disabled";
 763                         };
 764                 };
 765
 766                 aips2: aips-bus@2100000 {
 767                         compatible = "fsl,aips-bus", "simple-bus";
 768                         #address-cells = <1>;
 769                         #size-cells = <1>;
 770                         reg = <0x02100000 0x100000>;
 771                         ranges;
 772
 773                         crypto: caam@2140000 {
 774                                 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
 775                                 #address-cells = <1>;
 776                                 #size-cells = <1>;
 777                                 reg = <0x2140000 0x3c000>;
 778                                 ranges = <0 0x2140000 0x3c000>;
 779                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 780                                 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
 781                                          <&clks IMX6UL_CLK_CAAM_MEM>;
 782                                 clock-names = "ipg", "aclk", "mem";
 783
 784                                 sec_jr0: jr0@1000 {
 785                                         compatible = "fsl,sec-v4.0-job-ring";
 786                                         reg = <0x1000 0x1000>;
 787                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 788                                 };
 789
 790                                 sec_jr1: jr1@2000 {
 791                                         compatible = "fsl,sec-v4.0-job-ring";
 792                                         reg = <0x2000 0x1000>;
 793                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 794                                 };
 795
 796                                 sec_jr2: jr2@3000 {
 797                                         compatible = "fsl,sec-v4.0-job-ring";
 798                                         reg = <0x3000 0x1000>;
 799                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 800                                 };
 801                         };
 802
 803                         usbotg1: usb@2184000 {
 804                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 805                                 reg = <0x02184000 0x200>;
 806                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 808                                 fsl,usbphy = <&usbphy1>;
 809                                 fsl,usbmisc = <&usbmisc 0>;
 810                                 fsl,anatop = <&anatop>;
 811                                 ahb-burst-config = <0x0>;
 812                                 tx-burst-size-dword = <0x10>;
 813                                 rx-burst-size-dword = <0x10>;
 814                                 status = "disabled";
 815                         };
 816
 817                         usbotg2: usb@2184200 {
 818                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 819                                 reg = <0x02184200 0x200>;
 820                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 821                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 822                                 fsl,usbphy = <&usbphy2>;
 823                                 fsl,usbmisc = <&usbmisc 1>;
 824                                 ahb-burst-config = <0x0>;
 825                                 tx-burst-size-dword = <0x10>;
 826                                 rx-burst-size-dword = <0x10>;
 827                                 status = "disabled";
 828                         };
 829
 830                         usbmisc: usbmisc@2184800 {
 831                                 #index-cells = <1>;
 832                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 833                                 reg = <0x02184800 0x200>;
 834                         };
 835
 836                         fec1: ethernet@2188000 {
 837                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 838                                 reg = <0x02188000 0x4000>;
 839                                 interrupt-names = "int0", "pps";
 840                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 841                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 842                                 clocks = <&clks IMX6UL_CLK_ENET>,
 843                                          <&clks IMX6UL_CLK_ENET_AHB>,
 844                                          <&clks IMX6UL_CLK_ENET_PTP>,
 845                                          <&clks IMX6UL_CLK_ENET_REF>,
 846                                          <&clks IMX6UL_CLK_ENET_REF>;
 847                                 clock-names = "ipg", "ahb", "ptp",
 848                                               "enet_clk_ref", "enet_out";
 849                                 fsl,num-tx-queues=<1>;
 850                                 fsl,num-rx-queues=<1>;
 851                                 status = "disabled";
 852                         };
 853
 854                         usdhc1: usdhc@2190000 {
 855                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 856                                 reg = <0x02190000 0x4000>;
 857                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 859                                          <&clks IMX6UL_CLK_USDHC1>,
 860                                          <&clks IMX6UL_CLK_USDHC1>;
 861                                 clock-names = "ipg", "ahb", "per";
 862                                 bus-width = <4>;
 863                                 status = "disabled";
 864                         };
 865
 866                         usdhc2: usdhc@2194000 {
 867                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 868                                 reg = <0x02194000 0x4000>;
 869                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 870                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 871                                          <&clks IMX6UL_CLK_USDHC2>,
 872                                          <&clks IMX6UL_CLK_USDHC2>;
 873                                 clock-names = "ipg", "ahb", "per";
 874                                 bus-width = <4>;
 875                                 status = "disabled";
 876                         };
 877
 878                         adc1: adc@2198000 {
 879                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 880                                 reg = <0x02198000 0x4000>;
 881                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 882                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 883                                 num-channels = <2>;
 884                                 clock-names = "adc";
 885                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 886                                                          <20000000>;
 887                                 status = "disabled";
 888                         };
 889
 890                         i2c1: i2c@21a0000 {
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 894                                 reg = <0x021a0000 0x4000>;
 895                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 897                                 status = "disabled";
 898                         };
 899
 900                         i2c2: i2c@21a4000 {
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 904                                 reg = <0x021a4000 0x4000>;
 905                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c3: i2c@21a8000 {
 911                                 #address-cells = <1>;
 912                                 #size-cells = <0>;
 913                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 914                                 reg = <0x021a8000 0x4000>;
 915                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 916                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 917                                 status = "disabled";
 918                         };
 919
 920                         memory-controller@21b0000 {
 921                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 922                                 reg = <0x021b0000 0x4000>;
 923                                 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
 924                         };
 925
 926                         weim: weim@21b8000 {
 927                                 #address-cells = <2>;
 928                                 #size-cells = <1>;
 929                                 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
 930                                 reg = <0x021b8000 0x4000>;
 931                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clks IMX6UL_CLK_EIM>;
 933                                 fsl,weim-cs-gpr = <&gpr>;
 934                                 status = "disabled";
 935                         };
 936
 937                         ocotp: ocotp-ctrl@21bc000 {
 938                                 #address-cells = <1>;
 939                                 #size-cells = <1>;
 940                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 941                                 reg = <0x021bc000 0x4000>;
 942                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 943
 944                                 tempmon_calib: calib@38 {
 945                                         reg = <0x38 4>;
 946                                 };
 947
 948                                 tempmon_temp_grade: temp-grade@20 {
 949                                         reg = <0x20 4>;
 950                                 };
 951
 952                                 cpu_speed_grade: speed-grade@10 {
 953                                         reg = <0x10 4>;
 954                                 };
 955                         };
 956
 957                         lcdif: lcdif@21c8000 {
 958                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 959                                 reg = <0x021c8000 0x4000>;
 960                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 961                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 962                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 963                                          <&clks IMX6UL_CLK_DUMMY>;
 964                                 clock-names = "pix", "axi", "disp_axi";
 965                                 status = "disabled";
 966                         };
 967
 968                         qspi: spi@21e0000 {
 969                                 #address-cells = <1>;
 970                                 #size-cells = <0>;
 971                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 972                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 973                                 reg-names = "QuadSPI", "QuadSPI-memory";
 974                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 975                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 976                                          <&clks IMX6UL_CLK_QSPI>;
 977                                 clock-names = "qspi_en", "qspi";
 978                                 status = "disabled";
 979                         };
 980
 981                         wdog3: wdog@21e4000 {
 982                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 983                                 reg = <0x021e4000 0x4000>;
 984                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 985                                 clocks = <&clks IMX6UL_CLK_WDOG3>;
 986                                 status = "disabled";
 987                         };
 988
 989                         uart2: serial@21e8000 {
 990                                 compatible = "fsl,imx6ul-uart",
 991                                              "fsl,imx6q-uart";
 992                                 reg = <0x021e8000 0x4000>;
 993                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 994                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 995                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 996                                 clock-names = "ipg", "per";
 997                                 status = "disabled";
 998                         };
 999
1000                         uart3: serial@21ec000 {
1001                                 compatible = "fsl,imx6ul-uart",
1002                                              "fsl,imx6q-uart";
1003                                 reg = <0x021ec000 0x4000>;
1004                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1005                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1006                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
1007                                 clock-names = "ipg", "per";
1008                                 status = "disabled";
1009                         };
1010
1011                         uart4: serial@21f0000 {
1012                                 compatible = "fsl,imx6ul-uart",
1013                                              "fsl,imx6q-uart";
1014                                 reg = <0x021f0000 0x4000>;
1015                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1017                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
1018                                 clock-names = "ipg", "per";
1019                                 status = "disabled";
1020                         };
1021
1022                         uart5: serial@21f4000 {
1023                                 compatible = "fsl,imx6ul-uart",
1024                                              "fsl,imx6q-uart";
1025                                 reg = <0x021f4000 0x4000>;
1026                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1027                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1028                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
1029                                 clock-names = "ipg", "per";
1030                                 status = "disabled";
1031                         };
1032
1033                         i2c4: i2c@21f8000 {
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1037                                 reg = <0x021f8000 0x4000>;
1038                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1039                                 clocks = <&clks IMX6UL_CLK_I2C4>;
1040                                 status = "disabled";
1041                         };
1042
1043                         uart6: serial@21fc000 {
1044                                 compatible = "fsl,imx6ul-uart",
1045                                              "fsl,imx6q-uart";
1046                                 reg = <0x021fc000 0x4000>;
1047                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1049                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
1050                                 clock-names = "ipg", "per";
1051                                 status = "disabled";
1052                         };
1053                 };
1054         };
1055 };