arch/arm/dts/imx6ul-kontron-n6x1x-s.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 exceet electronics GmbH
   4  * Copyright (C) 2018 Kontron Electronics GmbH
   5  * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
   6  */
   7
   8 /dts-v1/;
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "imx6ul-kontron-n6x1x-som.dtsi"
  12
  13 / {
  14         gpio-leds {
  15                 compatible = "gpio-leds";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_leds>;
  18
  19                 led1 {
  20                         label = "debug-led1";
  21                         gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  22                         default-state = "off";
  23                         linux,default-trigger = "heartbeat";
  24                 };
  25
  26                 led2 {
  27                         label = "debug-led2";
  28                         gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
  29                         default-state = "off";
  30                 };
  31
  32                 led3 {
  33                         label = "debug-led3";
  34                         gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
  35                         default-state = "off";
  36                 };
  37         };
  38
  39         pwm-beeper {
  40                 compatible = "pwm-beeper";
  41                 pwms = <&pwm8 0 5000>;
  42         };
  43
  44         reg_3v3: regulator-3v3 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "3v3";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49         };
  50
  51         reg_5v: regulator-5v {
  52                 compatible = "regulator-fixed";
  53                 regulator-name = "5v";
  54                 regulator-min-microvolt = <5000000>;
  55                 regulator-max-microvolt = <5000000>;
  56         };
  57
  58         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "usb_otg1_vbus";
  61                 regulator-min-microvolt = <5000000>;
  62                 regulator-max-microvolt = <5000000>;
  63                 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  64                 enable-active-high;
  65         };
  66
  67         reg_vref_adc: regulator-vref-adc {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "vref-adc";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72         };
  73 };
  74
  75 &adc1 {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_adc1>;
  78         num-channels = <3>;
  79         vref-supply = <&reg_vref_adc>;
  80         status = "okay";
  81 };
  82
  83 &can2 {
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&pinctrl_flexcan2>;
  86         status = "okay";
  87 };
  88
  89 &ecspi1 {
  90         cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_ecspi1>;
  93         status = "okay";
  94
  95         eeprom@0 {
  96                 compatible = "anvo,anv32e61w", "atmel,at25";
  97                 reg = <0>;
  98                 spi-max-frequency = <20000000>;
  99                 spi-cpha;
 100                 spi-cpol;
 101                 pagesize = <1>;
 102                 size = <8192>;
 103                 address-width = <16>;
 104         };
 105 };
 106
 107 &fec1 {
 108         pinctrl-0 = <&pinctrl_enet1>;
 109         /delete-node/ mdio;
 110 };
 111
 112 &fec2 {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
 115         phy-mode = "rmii";
 116         phy-handle = <&ethphy2>;
 117         status = "okay";
 118
 119         mdio {
 120                 #address-cells = <1>;
 121                 #size-cells = <0>;
 122
 123                 ethphy1: ethernet-phy@1 {
 124                         reg = <1>;
 125                         micrel,led-mode = <0>;
 126                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
 127                         clock-names = "rmii-ref";
 128                 };
 129
 130                 ethphy2: ethernet-phy@2 {
 131                         reg = <2>;
 132                         micrel,led-mode = <0>;
 133                         clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 134                         clock-names = "rmii-ref";
 135                 };
 136         };
 137 };
 138
 139 &i2c1 {
 140         clock-frequency = <100000>;
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&pinctrl_i2c1>;
 143         status = "okay";
 144 };
 145
 146 &i2c4 {
 147         clock-frequency = <100000>;
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_i2c4>;
 150         status = "okay";
 151
 152         rtc@32 {
 153                 compatible = "epson,rx8900";
 154                 reg = <0x32>;
 155         };
 156 };
 157
 158 &pwm8 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_pwm8>;
 161         status = "okay";
 162 };
 163
 164 &uart1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_uart1>;
 167         status = "okay";
 168 };
 169
 170 &uart2 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_uart2>;
 173         linux,rs485-enabled-at-boot-time;
 174         rs485-rx-during-tx;
 175         rs485-rts-active-low;
 176         uart-has-rtscts;
 177         status = "okay";
 178 };
 179
 180 &uart3 {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_uart3>;
 183         fsl,uart-has-rtscts;
 184         status = "okay";
 185 };
 186
 187 &uart4 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_uart4>;
 190         status = "okay";
 191 };
 192
 193 &usbotg1 {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_usbotg1>;
 196         dr_mode = "otg";
 197         srp-disable;
 198         hnp-disable;
 199         adp-disable;
 200         over-current-active-low;
 201         vbus-supply = <&reg_usb_otg1_vbus>;
 202         status = "okay";
 203 };
 204
 205 &usbotg2 {
 206         dr_mode = "host";
 207         disable-over-current;
 208         vbus-supply = <&reg_5v>;
 209         status = "okay";
 210 };
 211
 212 &usdhc1 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_usdhc1>;
 215         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 216         keep-power-in-suspend;
 217         wakeup-source;
 218         vmmc-supply = <&reg_3v3>;
 219         voltage-ranges = <3300 3300>;
 220         bus-width = <4>;
 221         no-1-8-v;
 222         status = "okay";
 223 };
 224
 225 &usdhc2 {
 226         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 227         pinctrl-0 = <&pinctrl_usdhc2>;
 228         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 229         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 230         non-removable;
 231         keep-power-in-suspend;
 232         wakeup-source;
 233         vmmc-supply = <&reg_3v3>;
 234         voltage-ranges = <3300 3300>;
 235         bus-width = <4>;
 236         no-1-8-v;
 237         status = "okay";
 238 };
 239
 240 &wdog1 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_wdog>;
 243         fsl,ext-reset-output;
 244         status = "okay";
 245 };
 246
 247 &iomuxc {
 248         pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
 249
 250         pinctrl_adc1: adc1grp {
 251                 fsl,pins = <
 252                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0xb0
 253                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
 254                         MX6UL_PAD_GPIO1_IO08__GPIO1_IO08        0xb0
 255                 >;
 256         };
 257
 258         pinctrl_ecspi1: ecspi1grp {
 259                 fsl,pins = <
 260                         MX6UL_PAD_CSI_DATA07__ECSPI1_MISO       0x100b1
 261                         MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI       0x100b1
 262                         MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK       0x100b1
 263                         MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x100b1 /* ECSPI1-CS1 */
 264                 >;
 265         };
 266
 267         pinctrl_enet2: enet2grp {
 268                 fsl,pins = <
 269                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 270                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 271                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 272                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 273                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 274                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 275                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 276                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b009
 277                 >;
 278         };
 279
 280         pinctrl_enet2_mdio: enet2mdiogrp {
 281                 fsl,pins = <
 282                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 283                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 284                 >;
 285         };
 286
 287         pinctrl_flexcan2: flexcan2grp{
 288                 fsl,pins = <
 289                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 290                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 291                 >;
 292         };
 293
 294         pinctrl_gpio: gpiogrp {
 295                 fsl,pins = <
 296                         MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05      0x1b0b0 /* DOUT1 */
 297                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x1b0b0 /* DIN1 */
 298                         MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x1b0b0 /* DOUT2 */
 299                         MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x1b0b0 /* DIN2 */
 300                 >;
 301         };
 302
 303         pinctrl_gpio_leds: gpioledsgrp {
 304                 fsl,pins = <
 305                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30     0x1b0b0 /* LED H14 */
 306                         MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x1b0b0 /* LED H15 */
 307                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0 /* LED H16 */
 308                 >;
 309         };
 310
 311         pinctrl_i2c1: i2c1grp {
 312                 fsl,pins = <
 313                         MX6UL_PAD_CSI_PIXCLK__I2C1_SCL          0x4001b8b0
 314                         MX6UL_PAD_CSI_MCLK__I2C1_SDA            0x4001b8b0
 315                 >;
 316         };
 317
 318         pinctrl_i2c4: i2c4grp {
 319                 fsl,pins = <
 320                         MX6UL_PAD_UART2_TX_DATA__I2C4_SCL       0x4001f8b0
 321                         MX6UL_PAD_UART2_RX_DATA__I2C4_SDA       0x4001f8b0
 322                 >;
 323         };
 324
 325         pinctrl_pwm8: pwm8grp {
 326                 fsl,pins = <
 327                         MX6UL_PAD_CSI_HSYNC__PWM8_OUT           0x110b0
 328                 >;
 329         };
 330
 331         pinctrl_uart1: uart1grp {
 332                 fsl,pins = <
 333                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 334                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 335                 >;
 336         };
 337
 338         pinctrl_uart2: uart2grp {
 339                 fsl,pins = <
 340                         MX6UL_PAD_NAND_DATA04__UART2_DCE_TX     0x1b0b1
 341                         MX6UL_PAD_NAND_DATA05__UART2_DCE_RX     0x1b0b1
 342                         MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS    0x1b0b1
 343                         /*
 344                          * mux unused RTS to make sure it doesn't cause
 345                          * any interrupts when it is undefined
 346                          */
 347                         MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS    0x1b0b1
 348                 >;
 349         };
 350
 351         pinctrl_uart3: uart3grp {
 352                 fsl,pins = <
 353                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
 354                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
 355                         MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b1
 356                         MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b1
 357                 >;
 358         };
 359
 360         pinctrl_uart4: uart4grp {
 361                 fsl,pins = <
 362                         MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX   0x1b0b1
 363                         MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x1b0b1
 364                 >;
 365         };
 366
 367         pinctrl_usbotg1: usbotg1 {
 368                 fsl,pins = <
 369                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x1b0b0
 370                 >;
 371         };
 372
 373         pinctrl_usdhc1: usdhc1grp {
 374                 fsl,pins = <
 375                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 376                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 377                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 378                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 379                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 380                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 381                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x100b1 /* SD1_CD */
 382                 >;
 383         };
 384
 385         pinctrl_usdhc2: usdhc2grp {
 386                 fsl,pins = <
 387                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10059
 388                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
 389                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
 390                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
 391                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
 392                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
 393                 >;
 394         };
 395
 396         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 397                 fsl,pins = <
 398                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100b9
 399                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170b9
 400                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170b9
 401                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170b9
 402                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170b9
 403                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170b9
 404                 >;
 405         };
 406
 407         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 408                 fsl,pins = <
 409                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
 410                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
 411                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170f9
 412                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170f9
 413                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170f9
 414                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170f9
 415                 >;
 416         };
 417
 418         pinctrl_wdog: wdoggrp {
 419                 fsl,pins = <
 420                         MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x30b0
 421                 >;
 422         };
 423 };