1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
12 model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
13 compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
24 reg = <0x80000000 0x20000000>;
28 compatible = "simple-bus";
32 reg_can_3v3: regulator@0 {
33 compatible = "regulator-fixed";
35 regulator-name = "can-3v3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
41 reg_gpio_dvfs: regulator-gpio {
42 compatible = "regulator-gpio";
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_dvfs>;
45 regulator-min-microvolt = <1300000>;
46 regulator-max-microvolt = <1400000>;
47 regulator-name = "gpio_dvfs";
48 regulator-type = "voltage";
49 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
50 states = <1300000 0x1 1400000 0x0>;
53 reg_sd1_vmmc: regulator@1 {
54 compatible = "regulator-fixed";
55 regulator-name = "VSD_3V3";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
59 off-on-delay = <20000>;
65 compatible = "spi-gpio";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_spi4>;
68 pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
70 gpio-sck = <&gpio5 11 0>;
71 gpio-mosi = <&gpio5 10 0>;
72 cs-gpios = <&gpio5 7 0>;
73 num-chipselects = <1>;
77 gpio_spi: gpio_spi@0 {
78 compatible = "fairchild,74hc595";
82 registers-number = <1>;
83 registers-default = /bits/ 8 <0x57>;
84 spi-max-frequency = <100000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet1>;
93 phy-handle = <ðphy0>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_enet2>;
101 phy-handle = <ðphy1>;
105 #address-cells = <1>;
108 ethphy0: ethernet-phy@2 {
109 compatible = "ethernet-phy-ieee802.3-c22";
113 ethphy1: ethernet-phy@1 {
114 compatible = "ethernet-phy-ieee802.3-c22";
121 clock-frequency = <100000>;
122 pinctrl-names = "default", "gpio";
123 pinctrl-0 = <&pinctrl_i2c1>;
124 pinctrl-1 = <&pinctrl_i2c1_gpio>;
125 scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
126 sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
130 compatible = "fsl,pfuze3000";
135 regulator-min-microvolt = <700000>;
136 regulator-max-microvolt = <3300000>;
139 regulator-ramp-delay = <6250>;
142 /* use sw1c_reg to align with pfuze100/pfuze200 */
144 regulator-min-microvolt = <700000>;
145 regulator-max-microvolt = <1475000>;
148 regulator-ramp-delay = <6250>;
152 regulator-min-microvolt = <2500000>;
153 regulator-max-microvolt = <3300000>;
159 regulator-min-microvolt = <900000>;
160 regulator-max-microvolt = <1650000>;
166 regulator-min-microvolt = <5000000>;
167 regulator-max-microvolt = <5150000>;
171 regulator-min-microvolt = <1000000>;
172 regulator-max-microvolt = <3000000>;
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <3300000>;
189 regulator-min-microvolt = <800000>;
190 regulator-max-microvolt = <1550000>;
195 regulator-min-microvolt = <2850000>;
196 regulator-max-microvolt = <3300000>;
201 regulator-min-microvolt = <2850000>;
202 regulator-max-microvolt = <3300000>;
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3300000>;
213 regulator-min-microvolt = <1800000>;
214 regulator-max-microvolt = <3300000>;
221 compatible = "fsl,mag3110";
227 compatible = "fsl,fxls8471";
230 interrupt-parent = <&gpio5>;
236 clock_frequency = <100000>;
237 pinctrl-names = "default", "gpio";
238 pinctrl-0 = <&pinctrl_i2c2>;
239 pinctrl-1 = <&pinctrl_i2c2_gpio>;
240 scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
241 sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_hog_1>;
250 pinctrl_dvfs: dvfsgrp {
252 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
256 pinctrl_enet1: enet1grp {
258 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
259 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
260 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
261 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
262 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
263 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
264 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
265 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
269 pinctrl_enet2: enet2grp {
271 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
272 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
273 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
274 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
275 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
276 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
277 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
278 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
279 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
280 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
281 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
285 pinctrl_hog_1: hoggrp-1 {
287 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
288 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
289 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
293 pinctrl_i2c1: i2c1grp {
295 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
296 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
300 pinctrl_i2c1_gpio: i2c1grp_gpio {
302 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
303 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
307 pinctrl_i2c2: i2c2grp {
309 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
310 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
314 pinctrl_i2c2_gpio: i2c2grp_gpio {
316 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
317 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
321 pinctrl_qspi: qspigrp {
323 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
324 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
325 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
326 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
327 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
328 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
333 pinctrl_spi4: spi4grp {
335 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
336 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
337 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
338 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
342 pinctrl_uart1: uart1grp {
344 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
345 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
349 pinctrl_usb_otg1_id: usbotg1idgrp {
351 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
355 pinctrl_usdhc1: usdhc1grp {
357 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
358 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
359 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
360 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
361 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
362 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
366 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
368 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
369 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
370 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
371 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
372 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
373 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
377 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
379 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
380 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
381 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
382 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
383 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
384 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
388 pinctrl_usdhc2: usdhc2grp {
390 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
391 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
392 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
393 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
394 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
395 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
399 pinctrl_wdog: wdoggrp {
401 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_qspi>;
414 #address-cells = <1>;
416 compatible = "micron,n25q256a";
417 spi-max-frequency = <29000000>;
418 spi-nor,ddr-quad-read-dummy = <6>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart1>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_usb_otg1_id>;
441 disable-over-current;
446 pinctrl-names = "default", "state_100mhz", "state_200mhz";
447 pinctrl-0 = <&pinctrl_usdhc1>;
448 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
449 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
450 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
451 keep-power-in-suspend;
453 vmmc-supply = <®_sd1_vmmc>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_usdhc2>;
462 keep-power-in-suspend;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_wdog>;
470 fsl,ext-reset-output;