arch/arm/dts/imx6sx-sdb.dtsi

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include "imx6sx.dtsi"
  14
  15 / {
  16         model = "Freescale i.MX6 SoloX SDB Board";
  17         compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
  18
  19         chosen {
  20                 stdout-path = &uart1;
  21         };
  22
  23         memory {
  24                 reg = <0x80000000 0x40000000>;
  25         };
  26
  27         backlight {
  28                 compatible = "pwm-backlight";
  29                 pwms = <&pwm3 0 5000000>;
  30                 brightness-levels = <0 4 8 16 32 64 128 255>;
  31                 default-brightness-level = <6>;
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36                 pinctrl-names = "default";
  37                 pinctrl-0 = <&pinctrl_gpio_keys>;
  38
  39                 volume-up {
  40                         label = "Volume Up";
  41                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_VOLUMEUP>;
  43                 };
  44
  45                 volume-down {
  46                         label = "Volume Down";
  47                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_VOLUMEDOWN>;
  49                 };
  50         };
  51
  52         regulators {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 vcc_sd3: regulator@0 {
  58                         compatible = "regulator-fixed";
  59                         reg = <0>;
  60                         pinctrl-names = "default";
  61                         pinctrl-0 = <&pinctrl_vcc_sd3>;
  62                         regulator-name = "VCC_SD3";
  63                         regulator-min-microvolt = <3000000>;
  64                         regulator-max-microvolt = <3000000>;
  65                         gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  66                         enable-active-high;
  67                 };
  68
  69                 reg_usb_otg1_vbus: regulator@1 {
  70                         compatible = "regulator-fixed";
  71                         reg = <1>;
  72                         pinctrl-names = "default";
  73                         pinctrl-0 = <&pinctrl_usb_otg1>;
  74                         regulator-name = "usb_otg1_vbus";
  75                         regulator-min-microvolt = <5000000>;
  76                         regulator-max-microvolt = <5000000>;
  77                         gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  78                         enable-active-high;
  79                 };
  80
  81                 reg_usb_otg2_vbus: regulator@2 {
  82                         compatible = "regulator-fixed";
  83                         reg = <2>;
  84                         pinctrl-names = "default";
  85                         pinctrl-0 = <&pinctrl_usb_otg2>;
  86                         regulator-name = "usb_otg2_vbus";
  87                         regulator-min-microvolt = <5000000>;
  88                         regulator-max-microvolt = <5000000>;
  89                         gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  90                         enable-active-high;
  91                 };
  92
  93                 reg_psu_5v: regulator@3 {
  94                         compatible = "regulator-fixed";
  95                         reg = <3>;
  96                         regulator-name = "PSU-5V0";
  97                         regulator-min-microvolt = <5000000>;
  98                         regulator-max-microvolt = <5000000>;
  99                 };
 100
 101                 reg_lcd_3v3: regulator@4 {
 102                         compatible = "regulator-fixed";
 103                         reg = <4>;
 104                         regulator-name = "lcd-3v3";
 105                         gpio = <&gpio3 27 0>;
 106                         enable-active-high;
 107                 };
 108
 109                 reg_peri_3v3: regulator@5 {
 110                         compatible = "regulator-fixed";
 111                         reg = <5>;
 112                         pinctrl-names = "default";
 113                         pinctrl-0 = <&pinctrl_peri_3v3>;
 114                         regulator-name = "peri_3v3";
 115                         regulator-min-microvolt = <3300000>;
 116                         regulator-max-microvolt = <3300000>;
 117                         gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 118                         enable-active-high;
 119                         regulator-always-on;
 120                 };
 121
 122                 reg_enet_3v3: regulator@6 {
 123                         compatible = "regulator-fixed";
 124                         reg = <6>;
 125                         pinctrl-names = "default";
 126                         pinctrl-0 = <&pinctrl_enet_3v3>;
 127                         regulator-name = "enet_3v3";
 128                         regulator-min-microvolt = <3300000>;
 129                         regulator-max-microvolt = <3300000>;
 130                         gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
 131                 };
 132         };
 133
 134         sound {
 135                 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
 136                 model = "wm8962-audio";
 137                 ssi-controller = <&ssi2>;
 138                 audio-codec = <&codec>;
 139                 audio-routing =
 140                         "Headphone Jack", "HPOUTL",
 141                         "Headphone Jack", "HPOUTR",
 142                         "Ext Spk", "SPKOUTL",
 143                         "Ext Spk", "SPKOUTR",
 144                         "AMIC", "MICBIAS",
 145                         "IN3R", "AMIC";
 146                 mux-int-port = <2>;
 147                 mux-ext-port = <6>;
 148         };
 149 };
 150
 151 &audmux {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&pinctrl_audmux>;
 154         status = "okay";
 155 };
 156
 157 &fec1 {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_enet1>;
 160         phy-supply = <&reg_enet_3v3>;
 161         phy-mode = "rgmii";
 162         phy-handle = <&ethphy1>;
 163         status = "okay";
 164
 165         mdio {
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168
 169                 ethphy1: ethernet-phy@1 {
 170                         reg = <1>;
 171                 };
 172
 173                 ethphy2: ethernet-phy@2 {
 174                         reg = <2>;
 175                 };
 176         };
 177 };
 178
 179 &fec2 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_enet2>;
 182         phy-mode = "rgmii";
 183         phy-handle = <&ethphy2>;
 184         status = "okay";
 185 };
 186
 187 &i2c3 {
 188         clock-frequency = <100000>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_i2c3>;
 191         status = "okay";
 192 };
 193
 194 &i2c4 {
 195         clock-frequency = <100000>;
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_i2c4>;
 198         status = "okay";
 199
 200         codec: wm8962@1a {
 201                 compatible = "wlf,wm8962";
 202                 reg = <0x1a>;
 203                 clocks = <&clks IMX6SX_CLK_AUDIO>;
 204                 DCVDD-supply = <&vgen4_reg>;
 205                 DBVDD-supply = <&vgen4_reg>;
 206                 AVDD-supply = <&vgen4_reg>;
 207                 CPVDD-supply = <&vgen4_reg>;
 208                 MICVDD-supply = <&vgen3_reg>;
 209                 PLLVDD-supply = <&vgen4_reg>;
 210                 SPKVDD1-supply = <&reg_psu_5v>;
 211                 SPKVDD2-supply = <&reg_psu_5v>;
 212         };
 213 };
 214
 215 &lcdif1 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_lcd>;
 218         lcd-supply = <&reg_lcd_3v3>;
 219         display = <&display0>;
 220         status = "okay";
 221
 222         display0: display0 {
 223                 bits-per-pixel = <16>;
 224                 bus-width = <24>;
 225
 226                 display-timings {
 227                         native-mode = <&timing0>;
 228                         timing0: timing0 {
 229                                 clock-frequency = <33500000>;
 230                                 hactive = <800>;
 231                                 vactive = <480>;
 232                                 hback-porch = <89>;
 233                                 hfront-porch = <164>;
 234                                 vback-porch = <23>;
 235                                 vfront-porch = <10>;
 236                                 hsync-len = <10>;
 237                                 vsync-len = <10>;
 238                                 hsync-active = <0>;
 239                                 vsync-active = <0>;
 240                                 de-active = <1>;
 241                                 pixelclk-active = <0>;
 242                         };
 243                 };
 244         };
 245 };
 246
 247 &pwm3 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_pwm3>;
 250         status = "okay";
 251 };
 252
 253 &snvs_poweroff {
 254         status = "okay";
 255 };
 256
 257 &sai1 {
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_sai1>;
 260         status = "disabled";
 261 };
 262
 263 &ssi2 {
 264         status = "okay";
 265 };
 266
 267 &uart1 {
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_uart1>;
 270         status = "okay";
 271 };
 272
 273 &uart5 { /* for bluetooth */
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_uart5>;
 276         uart-has-rtscts;
 277         status = "okay";
 278 };
 279
 280 &usbotg1 {
 281         vbus-supply = <&reg_usb_otg1_vbus>;
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 284         status = "okay";
 285 };
 286
 287 &usbotg2 {
 288         vbus-supply = <&reg_usb_otg2_vbus>;
 289         dr_mode = "host";
 290         status = "okay";
 291 };
 292
 293 &usbphy1 {
 294         fsl,tx-d-cal = <106>;
 295 };
 296
 297 &usbphy2 {
 298         fsl,tx-d-cal = <106>;
 299 };
 300
 301 &usdhc2 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_usdhc2>;
 304         non-removable;
 305         no-1-8-v;
 306         keep-power-in-suspend;
 307         wakeup-source;
 308         status = "okay";
 309 };
 310
 311 &usdhc3 {
 312         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 313         pinctrl-0 = <&pinctrl_usdhc3>;
 314         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 315         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 316         bus-width = <8>;
 317         cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 318         wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 319         keep-power-in-suspend;
 320         wakeup-source;
 321         vmmc-supply = <&vcc_sd3>;
 322         status = "okay";
 323 };
 324
 325 &usdhc4 {
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&pinctrl_usdhc4>;
 328         cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
 329         wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
 330         status = "okay";
 331 };
 332
 333 &wdog1 {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&pinctrl_wdog>;
 336         fsl,ext-reset-output;
 337 };
 338
 339 &iomuxc {
 340         imx6x-sdb {
 341                 pinctrl_audmux: audmuxgrp {
 342                         fsl,pins = <
 343                                 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
 344                                 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
 345                                 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
 346                                 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
 347                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 348                         >;
 349                 };
 350
 351                 pinctrl_enet1: enet1grp {
 352                         fsl,pins = <
 353                                 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
 354                                 MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
 355                                 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
 356                                 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
 357                                 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
 358                                 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
 359                                 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
 360                                 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
 361                                 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
 362                                 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
 363                                 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
 364                                 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
 365                                 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
 366                                 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
 367                                 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
 368                         >;
 369                 };
 370
 371                 pinctrl_enet_3v3: enet3v3grp {
 372                         fsl,pins = <
 373                                 MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
 374                         >;
 375                 };
 376
 377                 pinctrl_enet2: enet2grp {
 378                         fsl,pins = <
 379                                 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
 380                                 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
 381                                 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
 382                                 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
 383                                 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
 384                                 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
 385                                 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
 386                                 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
 387                                 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
 388                                 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
 389                                 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
 390                                 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
 391                         >;
 392                 };
 393
 394                 pinctrl_gpio_keys: gpio_keysgrp {
 395                         fsl,pins = <
 396                                 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
 397                                 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
 398                         >;
 399                 };
 400
 401                 pinctrl_i2c1: i2c1grp {
 402                         fsl,pins = <
 403                                 MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
 404                                 MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
 405                         >;
 406                 };
 407
 408                 pinctrl_i2c3: i2c3grp {
 409                         fsl,pins = <
 410                                 MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
 411                                 MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
 412                         >;
 413                 };
 414
 415                 pinctrl_i2c4: i2c4grp {
 416                         fsl,pins = <
 417                                 MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
 418                                 MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
 419                         >;
 420                 };
 421
 422                 pinctrl_lcd: lcdgrp {
 423                         fsl,pins = <
 424                                 MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
 425                                 MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
 426                                 MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
 427                                 MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
 428                                 MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
 429                                 MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
 430                                 MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
 431                                 MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
 432                                 MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
 433                                 MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
 434                                 MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
 435                                 MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
 436                                 MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
 437                                 MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
 438                                 MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
 439                                 MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
 440                                 MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
 441                                 MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
 442                                 MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
 443                                 MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
 444                                 MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
 445                                 MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
 446                                 MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
 447                                 MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
 448                                 MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
 449                                 MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
 450                                 MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
 451                                 MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
 452                                 MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
 453                         >;
 454                 };
 455
 456                 pinctrl_peri_3v3: peri3v3grp {
 457                         fsl,pins = <
 458                                 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
 459                         >;
 460                 };
 461
 462                 pinctrl_pwm3: pwm3grp-1 {
 463                         fsl,pins = <
 464                                 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
 465                         >;
 466                 };
 467
 468                 pinctrl_qspi2: qspi2grp {
 469                         fsl,pins = <
 470                                 MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
 471                                 MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
 472                                 MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
 473                                 MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
 474                                 MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
 475                                 MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
 476                                 MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
 477                                 MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
 478                                 MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
 479                                 MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
 480                                 MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
 481                                 MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
 482                         >;
 483                 };
 484
 485                 pinctrl_vcc_sd3: vccsd3grp {
 486                         fsl,pins = <
 487                                 MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
 488                         >;
 489                 };
 490
 491                 pinctrl_sai1: sai1grp {
 492                         fsl,pins = <
 493                                 MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK      0x130b0
 494                                 MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC      0x130b0
 495                                 MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0     0x120b0
 496                                 MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0     0x130b0
 497                                 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
 498                         >;
 499                 };
 500
 501                 pinctrl_uart1: uart1grp {
 502                         fsl,pins = <
 503                                 MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
 504                                 MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
 505                         >;
 506                 };
 507
 508                 pinctrl_uart5: uart5grp {
 509                         fsl,pins = <
 510                                 MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
 511                                 MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
 512                                 MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
 513                                 MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
 514                         >;
 515                 };
 516
 517                 pinctrl_usb_otg1: usbotg1grp {
 518                         fsl,pins = <
 519                                 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
 520                         >;
 521                 };
 522
 523                 pinctrl_usb_otg1_id: usbotg1idgrp {
 524                         fsl,pins = <
 525                                 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
 526                         >;
 527                 };
 528
 529                 pinctrl_usb_otg2: usbot2ggrp {
 530                         fsl,pins = <
 531                                 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
 532                         >;
 533                 };
 534
 535                 pinctrl_usdhc2: usdhc2grp {
 536                         fsl,pins = <
 537                                 MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
 538                                 MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
 539                                 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
 540                                 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
 541                                 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
 542                                 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
 543                         >;
 544                 };
 545
 546                 pinctrl_usdhc3: usdhc3grp {
 547                         fsl,pins = <
 548                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
 549                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
 550                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
 551                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
 552                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
 553                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
 554                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
 555                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
 556                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
 557                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
 558                                 MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
 559                                 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
 560                         >;
 561                 };
 562
 563                 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
 564                         fsl,pins = <
 565                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
 566                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
 567                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
 568                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
 569                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
 570                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
 571                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
 572                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
 573                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
 574                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
 575                         >;
 576                 };
 577
 578                 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
 579                         fsl,pins = <
 580                                 MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
 581                                 MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
 582                                 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
 583                                 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
 584                                 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
 585                                 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
 586                                 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
 587                                 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
 588                                 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
 589                                 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
 590                         >;
 591                 };
 592
 593                 pinctrl_usdhc4: usdhc4grp {
 594                         fsl,pins = <
 595                                 MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
 596                                 MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
 597                                 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
 598                                 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
 599                                 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
 600                                 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
 601                                 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
 602                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
 603                         >;
 604                 };
 605
 606                 pinctrl_wdog: wdoggrp {
 607                         fsl,pins = <
 608                                 MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
 609                         >;
 610                 };
 611         };
 612 };