arch/arm/dts/imx6qdl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/clock/imx6qdl-clock.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         /*
  13          * The decompressor and also some bootloaders rely on a
  14          * pre-existing /chosen node to be available to insert the
  15          * command line and merge other ATAGS info.
  16          * Also for U-Boot there must be a pre-existing /memory node.
  17          */
  18         chosen {};
  19         memory { device_type = "memory"; };
  20
  21         aliases {
  22                 ethernet0 = &fec;
  23                 can0 = &can1;
  24                 can1 = &can2;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 gpio6 = &gpio7;
  32                 i2c0 = &i2c1;
  33                 i2c1 = &i2c2;
  34                 i2c2 = &i2c3;
  35                 ipu0 = &ipu1;
  36                 mmc0 = &usdhc1;
  37                 mmc1 = &usdhc2;
  38                 mmc2 = &usdhc3;
  39                 mmc3 = &usdhc4;
  40                 serial0 = &uart1;
  41                 serial1 = &uart2;
  42                 serial2 = &uart3;
  43                 serial3 = &uart4;
  44                 serial4 = &uart5;
  45                 spi0 = &ecspi1;
  46                 spi1 = &ecspi2;
  47                 spi2 = &ecspi3;
  48                 spi3 = &ecspi4;
  49                 usbphy0 = &usbphy1;
  50                 usbphy1 = &usbphy2;
  51         };
  52
  53         clocks {
  54                 ckil {
  55                         compatible = "fsl,imx-ckil", "fixed-clock";
  56                         #clock-cells = <0>;
  57                         clock-frequency = <32768>;
  58                 };
  59
  60                 ckih1 {
  61                         compatible = "fsl,imx-ckih1", "fixed-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <0>;
  64                 };
  65
  66                 osc {
  67                         compatible = "fsl,imx-osc", "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <24000000>;
  70                 };
  71         };
  72
  73         tempmon: tempmon {
  74                 compatible = "fsl,imx6q-tempmon";
  75                 interrupt-parent = <&gpc>;
  76                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
  77                 fsl,tempmon = <&anatop>;
  78                 fsl,tempmon-data = <&ocotp>;
  79                 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
  80         };
  81
  82         ldb: ldb {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
  86                 gpr = <&gpr>;
  87                 status = "disabled";
  88
  89                 lvds-channel@0 {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                         reg = <0>;
  93                         status = "disabled";
  94
  95                         port@0 {
  96                                 reg = <0>;
  97
  98                                 lvds0_mux_0: endpoint {
  99                                         remote-endpoint = <&ipu1_di0_lvds0>;
 100                                 };
 101                         };
 102
 103                         port@1 {
 104                                 reg = <1>;
 105
 106                                 lvds0_mux_1: endpoint {
 107                                         remote-endpoint = <&ipu1_di1_lvds0>;
 108                                 };
 109                         };
 110                 };
 111
 112                 lvds-channel@1 {
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         reg = <1>;
 116                         status = "disabled";
 117
 118                         port@0 {
 119                                 reg = <0>;
 120
 121                                 lvds1_mux_0: endpoint {
 122                                         remote-endpoint = <&ipu1_di0_lvds1>;
 123                                 };
 124                         };
 125
 126                         port@1 {
 127                                 reg = <1>;
 128
 129                                 lvds1_mux_1: endpoint {
 130                                         remote-endpoint = <&ipu1_di1_lvds1>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         pmu: pmu {
 137                 compatible = "arm,cortex-a9-pmu";
 138                 interrupt-parent = <&gpc>;
 139                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 140         };
 141
 142         soc {
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 compatible = "simple-bus";
 146                 interrupt-parent = <&gpc>;
 147                 ranges;
 148                 u-boot,dm-pre-reloc;
 149
 150                 dma_apbh: dma-apbh@110000 {
 151                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 152                         reg = <0x00110000 0x2000>;
 153                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 154                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 156                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 157                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 158                         #dma-cells = <1>;
 159                         dma-channels = <4>;
 160                         clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 161                 };
 162
 163                 gpmi: gpmi-nand@112000 {
 164                         compatible = "fsl,imx6q-gpmi-nand";
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
 168                         reg-names = "gpmi-nand", "bch";
 169                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 170                         interrupt-names = "bch";
 171                         clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
 172                                  <&clks IMX6QDL_CLK_GPMI_APB>,
 173                                  <&clks IMX6QDL_CLK_GPMI_BCH>,
 174                                  <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
 175                                  <&clks IMX6QDL_CLK_PER1_BCH>;
 176                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 177                                       "gpmi_bch_apb", "per1_bch";
 178                         dmas = <&dma_apbh 0>;
 179                         dma-names = "rx-tx";
 180                         status = "disabled";
 181                 };
 182
 183                 hdmi: hdmi@120000 {
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         reg = <0x00120000 0x9000>;
 187                         interrupts = <0 115 0x04>;
 188                         gpr = <&gpr>;
 189                         clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
 190                                  <&clks IMX6QDL_CLK_HDMI_ISFR>;
 191                         clock-names = "iahb", "isfr";
 192                         status = "disabled";
 193
 194                         port@0 {
 195                                 reg = <0>;
 196
 197                                 hdmi_mux_0: endpoint {
 198                                         remote-endpoint = <&ipu1_di0_hdmi>;
 199                                 };
 200                         };
 201
 202                         port@1 {
 203                                 reg = <1>;
 204
 205                                 hdmi_mux_1: endpoint {
 206                                         remote-endpoint = <&ipu1_di1_hdmi>;
 207                                 };
 208                         };
 209                 };
 210
 211                 gpu_3d: gpu@130000 {
 212                         compatible = "vivante,gc";
 213                         reg = <0x00130000 0x4000>;
 214                         interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 215                         clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
 216                                  <&clks IMX6QDL_CLK_GPU3D_CORE>,
 217                                  <&clks IMX6QDL_CLK_GPU3D_SHADER>;
 218                         clock-names = "bus", "core", "shader";
 219                         power-domains = <&pd_pu>;
 220                 };
 221
 222                 gpu_2d: gpu@134000 {
 223                         compatible = "vivante,gc";
 224                         reg = <0x00134000 0x4000>;
 225                         interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 226                         clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
 227                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 228                         clock-names = "bus", "core";
 229                         power-domains = <&pd_pu>;
 230                 };
 231
 232                 timer@a00600 {
 233                         compatible = "arm,cortex-a9-twd-timer";
 234                         reg = <0x00a00600 0x20>;
 235                         interrupts = <1 13 0xf01>;
 236                         interrupt-parent = <&intc>;
 237                         clocks = <&clks IMX6QDL_CLK_TWD>;
 238                 };
 239
 240                 intc: interrupt-controller@a01000 {
 241                         compatible = "arm,cortex-a9-gic";
 242                         #interrupt-cells = <3>;
 243                         interrupt-controller;
 244                         reg = <0x00a01000 0x1000>,
 245                               <0x00a00100 0x100>;
 246                         interrupt-parent = <&intc>;
 247                 };
 248
 249                 L2: l2-cache@a02000 {
 250                         compatible = "arm,pl310-cache";
 251                         reg = <0x00a02000 0x1000>;
 252                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 253                         cache-unified;
 254                         cache-level = <2>;
 255                         arm,tag-latency = <4 2 3>;
 256                         arm,data-latency = <4 2 3>;
 257                         arm,shared-override;
 258                 };
 259
 260                 pcie: pcie@1ffc000 {
 261                         compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
 262                         reg = <0x01ffc000 0x04000>,
 263                               <0x01f00000 0x80000>;
 264                         reg-names = "dbi", "config";
 265                         #address-cells = <3>;
 266                         #size-cells = <2>;
 267                         device_type = "pci";
 268                         bus-range = <0x00 0xff>;
 269                         ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
 270                                   0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
 271                         num-lanes = <1>;
 272                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 273                         interrupt-names = "msi";
 274                         #interrupt-cells = <1>;
 275                         interrupt-map-mask = <0 0 0 0x7>;
 276                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 277                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 278                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 279                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 280                         clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
 281                                  <&clks IMX6QDL_CLK_LVDS1_GATE>,
 282                                  <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 283                         clock-names = "pcie", "pcie_bus", "pcie_phy";
 284                         status = "disabled";
 285                 };
 286
 287                 aips-bus@2000000 { /* AIPS1 */
 288                         compatible = "fsl,aips-bus", "simple-bus";
 289                         #address-cells = <1>;
 290                         #size-cells = <1>;
 291                         reg = <0x02000000 0x100000>;
 292                         ranges;
 293
 294                         spba-bus@2000000 {
 295                                 compatible = "fsl,spba-bus", "simple-bus";
 296                                 #address-cells = <1>;
 297                                 #size-cells = <1>;
 298                                 reg = <0x02000000 0x40000>;
 299                                 ranges;
 300
 301                                 spdif: spdif@2004000 {
 302                                         compatible = "fsl,imx35-spdif";
 303                                         reg = <0x02004000 0x4000>;
 304                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 305                                         dmas = <&sdma 14 18 0>,
 306                                                <&sdma 15 18 0>;
 307                                         dma-names = "rx", "tx";
 308                                         clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 309                                                  <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 310                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 311                                                  <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
 312                                                  <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 313                                         clock-names = "core",  "rxtx0",
 314                                                       "rxtx1", "rxtx2",
 315                                                       "rxtx3", "rxtx4",
 316                                                       "rxtx5", "rxtx6",
 317                                                       "rxtx7", "spba";
 318                                         status = "disabled";
 319                                 };
 320
 321                                 ecspi1: spi@2008000 {
 322                                         #address-cells = <1>;
 323                                         #size-cells = <0>;
 324                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 325                                         reg = <0x02008000 0x4000>;
 326                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 327                                         clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 328                                                  <&clks IMX6QDL_CLK_ECSPI1>;
 329                                         clock-names = "ipg", "per";
 330                                         dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
 331                                         dma-names = "rx", "tx";
 332                                         status = "disabled";
 333                                 };
 334
 335                                 ecspi2: spi@200c000 {
 336                                         #address-cells = <1>;
 337                                         #size-cells = <0>;
 338                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 339                                         reg = <0x0200c000 0x4000>;
 340                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 341                                         clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 342                                                  <&clks IMX6QDL_CLK_ECSPI2>;
 343                                         clock-names = "ipg", "per";
 344                                         dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
 345                                         dma-names = "rx", "tx";
 346                                         status = "disabled";
 347                                 };
 348
 349                                 ecspi3: spi@2010000 {
 350                                         #address-cells = <1>;
 351                                         #size-cells = <0>;
 352                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 353                                         reg = <0x02010000 0x4000>;
 354                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 355                                         clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 356                                                  <&clks IMX6QDL_CLK_ECSPI3>;
 357                                         clock-names = "ipg", "per";
 358                                         dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
 359                                         dma-names = "rx", "tx";
 360                                         status = "disabled";
 361                                 };
 362
 363                                 ecspi4: spi@2014000 {
 364                                         #address-cells = <1>;
 365                                         #size-cells = <0>;
 366                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 367                                         reg = <0x02014000 0x4000>;
 368                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 369                                         clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 370                                                  <&clks IMX6QDL_CLK_ECSPI4>;
 371                                         clock-names = "ipg", "per";
 372                                         dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
 373                                         dma-names = "rx", "tx";
 374                                         status = "disabled";
 375                                 };
 376
 377                                 uart1: serial@2020000 {
 378                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
 379                                         reg = <0x02020000 0x4000>;
 380                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 381                                         clocks = <&clks IMX6QDL_CLK_UART_IPG>,
 382                                                  <&clks IMX6QDL_CLK_UART_SERIAL>;
 383                                         clock-names = "ipg", "per";
 384                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 385                                         dma-names = "rx", "tx";
 386                                         status = "disabled";
 387                                 };
 388
 389                                 esai: esai@2024000 {
 390                                         #sound-dai-cells = <0>;
 391                                         compatible = "fsl,imx35-esai";
 392                                         reg = <0x02024000 0x4000>;
 393                                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 394                                         clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
 395                                                  <&clks IMX6QDL_CLK_ESAI_MEM>,
 396                                                  <&clks IMX6QDL_CLK_ESAI_EXTAL>,
 397                                                  <&clks IMX6QDL_CLK_ESAI_IPG>,
 398                                                  <&clks IMX6QDL_CLK_SPBA>;
 399                                         clock-names = "core", "mem", "extal", "fsys", "spba";
 400                                         dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
 401                                         dma-names = "rx", "tx";
 402                                         status = "disabled";
 403                                 };
 404
 405                                 ssi1: ssi@2028000 {
 406                                         #sound-dai-cells = <0>;
 407                                         compatible = "fsl,imx6q-ssi",
 408                                                         "fsl,imx51-ssi";
 409                                         reg = <0x02028000 0x4000>;
 410                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 411                                         clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
 412                                                  <&clks IMX6QDL_CLK_SSI1>;
 413                                         clock-names = "ipg", "baud";
 414                                         dmas = <&sdma 37 1 0>,
 415                                                <&sdma 38 1 0>;
 416                                         dma-names = "rx", "tx";
 417                                         fsl,fifo-depth = <15>;
 418                                         status = "disabled";
 419                                 };
 420
 421                                 ssi2: ssi@202c000 {
 422                                         #sound-dai-cells = <0>;
 423                                         compatible = "fsl,imx6q-ssi",
 424                                                         "fsl,imx51-ssi";
 425                                         reg = <0x0202c000 0x4000>;
 426                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 427                                         clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
 428                                                  <&clks IMX6QDL_CLK_SSI2>;
 429                                         clock-names = "ipg", "baud";
 430                                         dmas = <&sdma 41 1 0>,
 431                                                <&sdma 42 1 0>;
 432                                         dma-names = "rx", "tx";
 433                                         fsl,fifo-depth = <15>;
 434                                         status = "disabled";
 435                                 };
 436
 437                                 ssi3: ssi@2030000 {
 438                                         #sound-dai-cells = <0>;
 439                                         compatible = "fsl,imx6q-ssi",
 440                                                         "fsl,imx51-ssi";
 441                                         reg = <0x02030000 0x4000>;
 442                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 443                                         clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
 444                                                  <&clks IMX6QDL_CLK_SSI3>;
 445                                         clock-names = "ipg", "baud";
 446                                         dmas = <&sdma 45 1 0>,
 447                                                <&sdma 46 1 0>;
 448                                         dma-names = "rx", "tx";
 449                                         fsl,fifo-depth = <15>;
 450                                         status = "disabled";
 451                                 };
 452
 453                                 asrc: asrc@2034000 {
 454                                         compatible = "fsl,imx53-asrc";
 455                                         reg = <0x02034000 0x4000>;
 456                                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
 457                                         clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
 458                                                 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
 459                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 460                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 461                                                 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
 462                                                 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
 463                                                 <&clks IMX6QDL_CLK_SPBA>;
 464                                         clock-names = "mem", "ipg", "asrck_0",
 465                                                 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
 466                                                 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
 467                                                 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
 468                                                 "asrck_d", "asrck_e", "asrck_f", "spba";
 469                                         dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
 470                                                 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
 471                                         dma-names = "rxa", "rxb", "rxc",
 472                                                         "txa", "txb", "txc";
 473                                         fsl,asrc-rate  = <48000>;
 474                                         fsl,asrc-width = <16>;
 475                                         status = "okay";
 476                                 };
 477
 478                                 spba@203c000 {
 479                                         reg = <0x0203c000 0x4000>;
 480                                 };
 481                         };
 482
 483                         vpu: vpu@2040000 {
 484                                 compatible = "cnm,coda960";
 485                                 reg = <0x02040000 0x3c000>;
 486                                 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
 487                                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 488                                 interrupt-names = "bit", "jpeg";
 489                                 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
 490                                          <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
 491                                 clock-names = "per", "ahb";
 492                                 power-domains = <&pd_pu>;
 493                                 resets = <&src 1>;
 494                                 iram = <&ocram>;
 495                         };
 496
 497                         aipstz@207c000 { /* AIPSTZ1 */
 498                                 reg = <0x0207c000 0x4000>;
 499                         };
 500
 501                         pwm1: pwm@2080000 {
 502                                 #pwm-cells = <2>;
 503                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 504                                 reg = <0x02080000 0x4000>;
 505                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 506                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 507                                          <&clks IMX6QDL_CLK_PWM1>;
 508                                 clock-names = "ipg", "per";
 509                                 status = "disabled";
 510                         };
 511
 512                         pwm2: pwm@2084000 {
 513                                 #pwm-cells = <2>;
 514                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 515                                 reg = <0x02084000 0x4000>;
 516                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 517                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 518                                          <&clks IMX6QDL_CLK_PWM2>;
 519                                 clock-names = "ipg", "per";
 520                                 status = "disabled";
 521                         };
 522
 523                         pwm3: pwm@2088000 {
 524                                 #pwm-cells = <2>;
 525                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 526                                 reg = <0x02088000 0x4000>;
 527                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 528                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 529                                          <&clks IMX6QDL_CLK_PWM3>;
 530                                 clock-names = "ipg", "per";
 531                                 status = "disabled";
 532                         };
 533
 534                         pwm4: pwm@208c000 {
 535                                 #pwm-cells = <2>;
 536                                 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
 537                                 reg = <0x0208c000 0x4000>;
 538                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 539                                 clocks = <&clks IMX6QDL_CLK_IPG>,
 540                                          <&clks IMX6QDL_CLK_PWM4>;
 541                                 clock-names = "ipg", "per";
 542                                 status = "disabled";
 543                         };
 544
 545                         can1: flexcan@2090000 {
 546                                 compatible = "fsl,imx6q-flexcan";
 547                                 reg = <0x02090000 0x4000>;
 548                                 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 549                                 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 550                                          <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 551                                 clock-names = "ipg", "per";
 552                                 status = "disabled";
 553                         };
 554
 555                         can2: flexcan@2094000 {
 556                                 compatible = "fsl,imx6q-flexcan";
 557                                 reg = <0x02094000 0x4000>;
 558                                 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 559                                 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 560                                          <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 561                                 clock-names = "ipg", "per";
 562                                 status = "disabled";
 563                         };
 564
 565                         gpt: gpt@2098000 {
 566                                 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 567                                 reg = <0x02098000 0x4000>;
 568                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 569                                 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
 570                                          <&clks IMX6QDL_CLK_GPT_IPG_PER>,
 571                                          <&clks IMX6QDL_CLK_GPT_3M>;
 572                                 clock-names = "ipg", "per", "osc_per";
 573                         };
 574
 575                         gpio1: gpio@209c000 {
 576                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 577                                 reg = <0x0209c000 0x4000>;
 578                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 579                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 580                                 gpio-controller;
 581                                 #gpio-cells = <2>;
 582                                 interrupt-controller;
 583                                 #interrupt-cells = <2>;
 584                         };
 585
 586                         gpio2: gpio@20a0000 {
 587                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 588                                 reg = <0x020a0000 0x4000>;
 589                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 591                                 gpio-controller;
 592                                 #gpio-cells = <2>;
 593                                 interrupt-controller;
 594                                 #interrupt-cells = <2>;
 595                         };
 596
 597                         gpio3: gpio@20a4000 {
 598                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 599                                 reg = <0x020a4000 0x4000>;
 600                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 601                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 602                                 gpio-controller;
 603                                 #gpio-cells = <2>;
 604                                 interrupt-controller;
 605                                 #interrupt-cells = <2>;
 606                         };
 607
 608                         gpio4: gpio@20a8000 {
 609                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 610                                 reg = <0x020a8000 0x4000>;
 611                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 612                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 613                                 gpio-controller;
 614                                 #gpio-cells = <2>;
 615                                 interrupt-controller;
 616                                 #interrupt-cells = <2>;
 617                         };
 618
 619                         gpio5: gpio@20ac000 {
 620                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 621                                 reg = <0x020ac000 0x4000>;
 622                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 623                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 624                                 gpio-controller;
 625                                 #gpio-cells = <2>;
 626                                 interrupt-controller;
 627                                 #interrupt-cells = <2>;
 628                         };
 629
 630                         gpio6: gpio@20b0000 {
 631                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 632                                 reg = <0x020b0000 0x4000>;
 633                                 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
 634                                              <0 77 IRQ_TYPE_LEVEL_HIGH>;
 635                                 gpio-controller;
 636                                 #gpio-cells = <2>;
 637                                 interrupt-controller;
 638                                 #interrupt-cells = <2>;
 639                         };
 640
 641                         gpio7: gpio@20b4000 {
 642                                 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
 643                                 reg = <0x020b4000 0x4000>;
 644                                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
 645                                              <0 79 IRQ_TYPE_LEVEL_HIGH>;
 646                                 gpio-controller;
 647                                 #gpio-cells = <2>;
 648                                 interrupt-controller;
 649                                 #interrupt-cells = <2>;
 650                         };
 651
 652                         kpp: kpp@20b8000 {
 653                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 654                                 reg = <0x020b8000 0x4000>;
 655                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 656                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 657                                 status = "disabled";
 658                         };
 659
 660                         wdog1: wdog@20bc000 {
 661                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 662                                 reg = <0x020bc000 0x4000>;
 663                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 664                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 665                         };
 666
 667                         wdog2: wdog@20c0000 {
 668                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 669                                 reg = <0x020c0000 0x4000>;
 670                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 671                                 clocks = <&clks IMX6QDL_CLK_DUMMY>;
 672                                 status = "disabled";
 673                         };
 674
 675                         clks: ccm@20c4000 {
 676                                 compatible = "fsl,imx6q-ccm";
 677                                 reg = <0x020c4000 0x4000>;
 678                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 679                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 680                                 #clock-cells = <1>;
 681                         };
 682
 683                         anatop: anatop@20c8000 {
 684                                 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
 685                                 reg = <0x020c8000 0x1000>;
 686                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 687                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 688                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 689
 690                                 regulator-1p1 {
 691                                         compatible = "fsl,anatop-regulator";
 692                                         regulator-name = "vdd1p1";
 693                                         regulator-min-microvolt = <1000000>;
 694                                         regulator-max-microvolt = <1200000>;
 695                                         regulator-always-on;
 696                                         anatop-reg-offset = <0x110>;
 697                                         anatop-vol-bit-shift = <8>;
 698                                         anatop-vol-bit-width = <5>;
 699                                         anatop-min-bit-val = <4>;
 700                                         anatop-min-voltage = <800000>;
 701                                         anatop-max-voltage = <1375000>;
 702                                         anatop-enable-bit = <0>;
 703                                 };
 704
 705                                 regulator-3p0 {
 706                                         compatible = "fsl,anatop-regulator";
 707                                         regulator-name = "vdd3p0";
 708                                         regulator-min-microvolt = <2800000>;
 709                                         regulator-max-microvolt = <3150000>;
 710                                         regulator-always-on;
 711                                         anatop-reg-offset = <0x120>;
 712                                         anatop-vol-bit-shift = <8>;
 713                                         anatop-vol-bit-width = <5>;
 714                                         anatop-min-bit-val = <0>;
 715                                         anatop-min-voltage = <2625000>;
 716                                         anatop-max-voltage = <3400000>;
 717                                         anatop-enable-bit = <0>;
 718                                 };
 719
 720                                 regulator-2p5 {
 721                                         compatible = "fsl,anatop-regulator";
 722                                         regulator-name = "vdd2p5";
 723                                         regulator-min-microvolt = <2250000>;
 724                                         regulator-max-microvolt = <2750000>;
 725                                         regulator-always-on;
 726                                         anatop-reg-offset = <0x130>;
 727                                         anatop-vol-bit-shift = <8>;
 728                                         anatop-vol-bit-width = <5>;
 729                                         anatop-min-bit-val = <0>;
 730                                         anatop-min-voltage = <2100000>;
 731                                         anatop-max-voltage = <2875000>;
 732                                         anatop-enable-bit = <0>;
 733                                 };
 734
 735                                 reg_arm: regulator-vddcore {
 736                                         compatible = "fsl,anatop-regulator";
 737                                         regulator-name = "vddarm";
 738                                         regulator-min-microvolt = <725000>;
 739                                         regulator-max-microvolt = <1450000>;
 740                                         regulator-always-on;
 741                                         anatop-reg-offset = <0x140>;
 742                                         anatop-vol-bit-shift = <0>;
 743                                         anatop-vol-bit-width = <5>;
 744                                         anatop-delay-reg-offset = <0x170>;
 745                                         anatop-delay-bit-shift = <24>;
 746                                         anatop-delay-bit-width = <2>;
 747                                         anatop-min-bit-val = <1>;
 748                                         anatop-min-voltage = <725000>;
 749                                         anatop-max-voltage = <1450000>;
 750                                 };
 751
 752                                 reg_pu: regulator-vddpu {
 753                                         compatible = "fsl,anatop-regulator";
 754                                         regulator-name = "vddpu";
 755                                         regulator-min-microvolt = <725000>;
 756                                         regulator-max-microvolt = <1450000>;
 757                                         regulator-enable-ramp-delay = <150>;
 758                                         anatop-reg-offset = <0x140>;
 759                                         anatop-vol-bit-shift = <9>;
 760                                         anatop-vol-bit-width = <5>;
 761                                         anatop-delay-reg-offset = <0x170>;
 762                                         anatop-delay-bit-shift = <26>;
 763                                         anatop-delay-bit-width = <2>;
 764                                         anatop-min-bit-val = <1>;
 765                                         anatop-min-voltage = <725000>;
 766                                         anatop-max-voltage = <1450000>;
 767                                 };
 768
 769                                 reg_soc: regulator-vddsoc {
 770                                         compatible = "fsl,anatop-regulator";
 771                                         regulator-name = "vddsoc";
 772                                         regulator-min-microvolt = <725000>;
 773                                         regulator-max-microvolt = <1450000>;
 774                                         regulator-always-on;
 775                                         anatop-reg-offset = <0x140>;
 776                                         anatop-vol-bit-shift = <18>;
 777                                         anatop-vol-bit-width = <5>;
 778                                         anatop-delay-reg-offset = <0x170>;
 779                                         anatop-delay-bit-shift = <28>;
 780                                         anatop-delay-bit-width = <2>;
 781                                         anatop-min-bit-val = <1>;
 782                                         anatop-min-voltage = <725000>;
 783                                         anatop-max-voltage = <1450000>;
 784                                 };
 785                         };
 786
 787                         usbphy1: usbphy@20c9000 {
 788                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 789                                 reg = <0x020c9000 0x1000>;
 790                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 791                                 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
 792                                 fsl,anatop = <&anatop>;
 793                         };
 794
 795                         usbphy2: usbphy@20ca000 {
 796                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 797                                 reg = <0x020ca000 0x1000>;
 798                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 799                                 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
 800                                 fsl,anatop = <&anatop>;
 801                         };
 802
 803                         snvs: snvs@20cc000 {
 804                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 805                                 reg = <0x020cc000 0x4000>;
 806
 807                                 snvs_rtc: snvs-rtc-lp {
 808                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 809                                         regmap = <&snvs>;
 810                                         offset = <0x34>;
 811                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 812                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 813                                 };
 814
 815                                 snvs_poweroff: snvs-poweroff {
 816                                         compatible = "syscon-poweroff";
 817                                         regmap = <&snvs>;
 818                                         offset = <0x38>;
 819                                         value = <0x60>;
 820                                         mask = <0x60>;
 821                                         status = "disabled";
 822                                 };
 823
 824                                 snvs_lpgpr: snvs-lpgpr {
 825                                         compatible = "fsl,imx6q-snvs-lpgpr";
 826                                 };
 827                         };
 828
 829                         epit1: epit@20d0000 { /* EPIT1 */
 830                                 reg = <0x020d0000 0x4000>;
 831                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 832                         };
 833
 834                         epit2: epit@20d4000 { /* EPIT2 */
 835                                 reg = <0x020d4000 0x4000>;
 836                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 837                         };
 838
 839                         src: src@20d8000 {
 840                                 compatible = "fsl,imx6q-src", "fsl,imx51-src";
 841                                 reg = <0x020d8000 0x4000>;
 842                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 843                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 844                                 #reset-cells = <1>;
 845                         };
 846
 847                         gpc: gpc@20dc000 {
 848                                 compatible = "fsl,imx6q-gpc";
 849                                 reg = <0x020dc000 0x4000>;
 850                                 interrupt-controller;
 851                                 #interrupt-cells = <3>;
 852                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
 853                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
 854                                 interrupt-parent = <&intc>;
 855                                 clocks = <&clks IMX6QDL_CLK_IPG>;
 856                                 clock-names = "ipg";
 857
 858                                 pgc {
 859                                         #address-cells = <1>;
 860                                         #size-cells = <0>;
 861
 862                                         power-domain@0 {
 863                                                 reg = <0>;
 864                                                 #power-domain-cells = <0>;
 865                                         };
 866                                         pd_pu: power-domain@1 {
 867                                                 reg = <1>;
 868                                                 #power-domain-cells = <0>;
 869                                                 power-supply = <&reg_pu>;
 870                                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
 871                                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
 872                                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
 873                                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
 874                                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
 875                                                          <&clks IMX6QDL_CLK_VPU_AXI>;
 876                                         };
 877                                 };
 878                         };
 879
 880                         gpr: iomuxc-gpr@20e0000 {
 881                                 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
 882                                 reg = <0x20e0000 0x38>;
 883
 884                                 mux: mux-controller {
 885                                         compatible = "mmio-mux";
 886                                         #mux-control-cells = <1>;
 887                                 };
 888                         };
 889
 890                         iomuxc: iomuxc@20e0000 {
 891                                 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 892                                 reg = <0x20e0000 0x4000>;
 893                         };
 894
 895                         dcic1: dcic@20e4000 {
 896                                 reg = <0x020e4000 0x4000>;
 897                                 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 898                         };
 899
 900                         dcic2: dcic@20e8000 {
 901                                 reg = <0x020e8000 0x4000>;
 902                                 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 903                         };
 904
 905                         sdma: sdma@20ec000 {
 906                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 907                                 reg = <0x020ec000 0x4000>;
 908                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 909                                 clocks = <&clks IMX6QDL_CLK_SDMA>,
 910                                          <&clks IMX6QDL_CLK_SDMA>;
 911                                 clock-names = "ipg", "ahb";
 912                                 #dma-cells = <3>;
 913                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 914                         };
 915                 };
 916
 917                 aips-bus@2100000 { /* AIPS2 */
 918                         compatible = "fsl,aips-bus", "simple-bus";
 919                         #address-cells = <1>;
 920                         #size-cells = <1>;
 921                         reg = <0x02100000 0x100000>;
 922                         ranges;
 923
 924                         crypto: caam@2100000 {
 925                                 compatible = "fsl,sec-v4.0";
 926                                 #address-cells = <1>;
 927                                 #size-cells = <1>;
 928                                 reg = <0x2100000 0x10000>;
 929                                 ranges = <0 0x2100000 0x10000>;
 930                                 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 931                                          <&clks IMX6QDL_CLK_CAAM_ACLK>,
 932                                          <&clks IMX6QDL_CLK_CAAM_IPG>,
 933                                          <&clks IMX6QDL_CLK_EIM_SLOW>;
 934                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 935
 936                                 sec_jr0: jr0@1000 {
 937                                         compatible = "fsl,sec-v4.0-job-ring";
 938                                         reg = <0x1000 0x1000>;
 939                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 940                                 };
 941
 942                                 sec_jr1: jr1@2000 {
 943                                         compatible = "fsl,sec-v4.0-job-ring";
 944                                         reg = <0x2000 0x1000>;
 945                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 946                                 };
 947                         };
 948
 949                         aipstz@217c000 { /* AIPSTZ2 */
 950                                 reg = <0x0217c000 0x4000>;
 951                         };
 952
 953                         usbotg: usb@2184000 {
 954                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 955                                 reg = <0x02184000 0x200>;
 956                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 957                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 958                                 fsl,usbphy = <&usbphy1>;
 959                                 fsl,usbmisc = <&usbmisc 0>;
 960                                 ahb-burst-config = <0x0>;
 961                                 tx-burst-size-dword = <0x10>;
 962                                 rx-burst-size-dword = <0x10>;
 963                                 status = "disabled";
 964                         };
 965
 966                         usbh1: usb@2184200 {
 967                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 968                                 reg = <0x02184200 0x200>;
 969                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 970                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 971                                 fsl,usbphy = <&usbphy2>;
 972                                 fsl,usbmisc = <&usbmisc 1>;
 973                                 dr_mode = "host";
 974                                 ahb-burst-config = <0x0>;
 975                                 tx-burst-size-dword = <0x10>;
 976                                 rx-burst-size-dword = <0x10>;
 977                                 status = "disabled";
 978                         };
 979
 980                         usbh2: usb@2184400 {
 981                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 982                                 reg = <0x02184400 0x200>;
 983                                 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
 984                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 985                                 fsl,usbmisc = <&usbmisc 2>;
 986                                 dr_mode = "host";
 987                                 ahb-burst-config = <0x0>;
 988                                 tx-burst-size-dword = <0x10>;
 989                                 rx-burst-size-dword = <0x10>;
 990                                 status = "disabled";
 991                         };
 992
 993                         usbh3: usb@2184600 {
 994                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 995                                 reg = <0x02184600 0x200>;
 996                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 997                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
 998                                 fsl,usbmisc = <&usbmisc 3>;
 999                                 dr_mode = "host";
1000                                 ahb-burst-config = <0x0>;
1001                                 tx-burst-size-dword = <0x10>;
1002                                 rx-burst-size-dword = <0x10>;
1003                                 status = "disabled";
1004                         };
1005
1006                         usbmisc: usbmisc@2184800 {
1007                                 #index-cells = <1>;
1008                                 compatible = "fsl,imx6q-usbmisc";
1009                                 reg = <0x02184800 0x200>;
1010                                 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1011                         };
1012
1013                         fec: ethernet@2188000 {
1014                                 compatible = "fsl,imx6q-fec";
1015                                 reg = <0x02188000 0x4000>;
1016                                 interrupt-names = "int0", "pps";
1017                                 interrupts-extended =
1018                                         <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1019                                         <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1020                                 clocks = <&clks IMX6QDL_CLK_ENET>,
1021                                          <&clks IMX6QDL_CLK_ENET>,
1022                                          <&clks IMX6QDL_CLK_ENET_REF>;
1023                                 clock-names = "ipg", "ahb", "ptp";
1024                                 status = "disabled";
1025                         };
1026
1027                         mlb@218c000 {
1028                                 reg = <0x0218c000 0x4000>;
1029                                 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1030                                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1031                                              <0 126 IRQ_TYPE_LEVEL_HIGH>;
1032                         };
1033
1034                         usdhc1: usdhc@2190000 {
1035                                 compatible = "fsl,imx6q-usdhc";
1036                                 reg = <0x02190000 0x4000>;
1037                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1038                                 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1039                                          <&clks IMX6QDL_CLK_USDHC1>,
1040                                          <&clks IMX6QDL_CLK_USDHC1>;
1041                                 clock-names = "ipg", "ahb", "per";
1042                                 bus-width = <4>;
1043                                 status = "disabled";
1044                         };
1045
1046                         usdhc2: usdhc@2194000 {
1047                                 compatible = "fsl,imx6q-usdhc";
1048                                 reg = <0x02194000 0x4000>;
1049                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1050                                 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1051                                          <&clks IMX6QDL_CLK_USDHC2>,
1052                                          <&clks IMX6QDL_CLK_USDHC2>;
1053                                 clock-names = "ipg", "ahb", "per";
1054                                 bus-width = <4>;
1055                                 status = "disabled";
1056                         };
1057
1058                         usdhc3: usdhc@2198000 {
1059                                 compatible = "fsl,imx6q-usdhc";
1060                                 reg = <0x02198000 0x4000>;
1061                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1062                                 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1063                                          <&clks IMX6QDL_CLK_USDHC3>,
1064                                          <&clks IMX6QDL_CLK_USDHC3>;
1065                                 clock-names = "ipg", "ahb", "per";
1066                                 bus-width = <4>;
1067                                 status = "disabled";
1068                         };
1069
1070                         usdhc4: usdhc@219c000 {
1071                                 compatible = "fsl,imx6q-usdhc";
1072                                 reg = <0x0219c000 0x4000>;
1073                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1074                                 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1075                                          <&clks IMX6QDL_CLK_USDHC4>,
1076                                          <&clks IMX6QDL_CLK_USDHC4>;
1077                                 clock-names = "ipg", "ahb", "per";
1078                                 bus-width = <4>;
1079                                 status = "disabled";
1080                         };
1081
1082                         i2c1: i2c@21a0000 {
1083                                 #address-cells = <1>;
1084                                 #size-cells = <0>;
1085                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1086                                 reg = <0x021a0000 0x4000>;
1087                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1088                                 clocks = <&clks IMX6QDL_CLK_I2C1>;
1089                                 status = "disabled";
1090                         };
1091
1092                         i2c2: i2c@21a4000 {
1093                                 #address-cells = <1>;
1094                                 #size-cells = <0>;
1095                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1096                                 reg = <0x021a4000 0x4000>;
1097                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1098                                 clocks = <&clks IMX6QDL_CLK_I2C2>;
1099                                 status = "disabled";
1100                         };
1101
1102                         i2c3: i2c@21a8000 {
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1106                                 reg = <0x021a8000 0x4000>;
1107                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1108                                 clocks = <&clks IMX6QDL_CLK_I2C3>;
1109                                 status = "disabled";
1110                         };
1111
1112                         romcp@21ac000 {
1113                                 reg = <0x021ac000 0x4000>;
1114                         };
1115
1116                         mmdc0: mmdc@21b0000 { /* MMDC0 */
1117                                 compatible = "fsl,imx6q-mmdc";
1118                                 reg = <0x021b0000 0x4000>;
1119                         };
1120
1121                         mmdc1: mmdc@21b4000 { /* MMDC1 */
1122                                 reg = <0x021b4000 0x4000>;
1123                         };
1124
1125                         weim: weim@21b8000 {
1126                                 #address-cells = <2>;
1127                                 #size-cells = <1>;
1128                                 compatible = "fsl,imx6q-weim";
1129                                 reg = <0x021b8000 0x4000>;
1130                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1131                                 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1132                                 fsl,weim-cs-gpr = <&gpr>;
1133                                 status = "disabled";
1134                         };
1135
1136                         ocotp: ocotp@21bc000 {
1137                                 compatible = "fsl,imx6q-ocotp", "syscon";
1138                                 reg = <0x021bc000 0x4000>;
1139                                 clocks = <&clks IMX6QDL_CLK_IIM>;
1140                         };
1141
1142                         tzasc@21d0000 { /* TZASC1 */
1143                                 reg = <0x021d0000 0x4000>;
1144                                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1145                         };
1146
1147                         tzasc@21d4000 { /* TZASC2 */
1148                                 reg = <0x021d4000 0x4000>;
1149                                 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1150                         };
1151
1152                         audmux: audmux@21d8000 {
1153                                 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1154                                 reg = <0x021d8000 0x4000>;
1155                                 status = "disabled";
1156                         };
1157
1158                         mipi_csi: mipi@21dc000 {
1159                                 compatible = "fsl,imx6-mipi-csi2";
1160                                 reg = <0x021dc000 0x4000>;
1161                                 #address-cells = <1>;
1162                                 #size-cells = <0>;
1163                                 interrupts = <0 100 0x04>, <0 101 0x04>;
1164                                 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1165                                          <&clks IMX6QDL_CLK_VIDEO_27M>,
1166                                          <&clks IMX6QDL_CLK_EIM_PODF>;
1167                                 clock-names = "dphy", "ref", "pix";
1168                                 status = "disabled";
1169                         };
1170
1171                         mipi_dsi: mipi@21e0000 {
1172                                 reg = <0x021e0000 0x4000>;
1173                                 status = "disabled";
1174
1175                                 ports {
1176                                         #address-cells = <1>;
1177                                         #size-cells = <0>;
1178
1179                                         port@0 {
1180                                                 reg = <0>;
1181
1182                                                 mipi_mux_0: endpoint {
1183                                                         remote-endpoint = <&ipu1_di0_mipi>;
1184                                                 };
1185                                         };
1186
1187                                         port@1 {
1188                                                 reg = <1>;
1189
1190                                                 mipi_mux_1: endpoint {
1191                                                         remote-endpoint = <&ipu1_di1_mipi>;
1192                                                 };
1193                                         };
1194                                 };
1195                         };
1196
1197                         vdoa@21e4000 {
1198                                 compatible = "fsl,imx6q-vdoa";
1199                                 reg = <0x021e4000 0x4000>;
1200                                 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1201                                 clocks = <&clks IMX6QDL_CLK_VDOA>;
1202                         };
1203
1204                         uart2: serial@21e8000 {
1205                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1206                                 reg = <0x021e8000 0x4000>;
1207                                 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1208                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1209                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1210                                 clock-names = "ipg", "per";
1211                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1212                                 dma-names = "rx", "tx";
1213                                 status = "disabled";
1214                         };
1215
1216                         uart3: serial@21ec000 {
1217                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1218                                 reg = <0x021ec000 0x4000>;
1219                                 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1220                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1221                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1222                                 clock-names = "ipg", "per";
1223                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1224                                 dma-names = "rx", "tx";
1225                                 status = "disabled";
1226                         };
1227
1228                         uart4: serial@21f0000 {
1229                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1230                                 reg = <0x021f0000 0x4000>;
1231                                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1232                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1233                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1234                                 clock-names = "ipg", "per";
1235                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1236                                 dma-names = "rx", "tx";
1237                                 status = "disabled";
1238                         };
1239
1240                         uart5: serial@21f4000 {
1241                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1242                                 reg = <0x021f4000 0x4000>;
1243                                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1244                                 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1245                                          <&clks IMX6QDL_CLK_UART_SERIAL>;
1246                                 clock-names = "ipg", "per";
1247                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1248                                 dma-names = "rx", "tx";
1249                                 status = "disabled";
1250                         };
1251                 };
1252
1253                 ipu1: ipu@2400000 {
1254                         #address-cells = <1>;
1255                         #size-cells = <0>;
1256                         compatible = "fsl,imx6q-ipu";
1257                         reg = <0x02400000 0x400000>;
1258                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1259                                      <0 5 IRQ_TYPE_LEVEL_HIGH>;
1260                         clocks = <&clks IMX6QDL_CLK_IPU1>,
1261                                  <&clks IMX6QDL_CLK_IPU1_DI0>,
1262                                  <&clks IMX6QDL_CLK_IPU1_DI1>;
1263                         clock-names = "bus", "di0", "di1";
1264                         resets = <&src 2>;
1265                         u-boot,dm-pre-reloc;
1266
1267                         ipu1_csi0: port@0 {
1268                                 reg = <0>;
1269
1270                                 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1271                                         remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1272                                 };
1273                         };
1274
1275                         ipu1_csi1: port@1 {
1276                                 reg = <1>;
1277                         };
1278
1279                         ipu1_di0: port@2 {
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 reg = <2>;
1283
1284                                 ipu1_di0_disp0: endpoint@0 {
1285                                         reg = <0>;
1286                                 };
1287
1288                                 ipu1_di0_hdmi: endpoint@1 {
1289                                         reg = <1>;
1290                                         remote-endpoint = <&hdmi_mux_0>;
1291                                 };
1292
1293                                 ipu1_di0_mipi: endpoint@2 {
1294                                         reg = <2>;
1295                                         remote-endpoint = <&mipi_mux_0>;
1296                                 };
1297
1298                                 ipu1_di0_lvds0: endpoint@3 {
1299                                         reg = <3>;
1300                                         remote-endpoint = <&lvds0_mux_0>;
1301                                 };
1302
1303                                 ipu1_di0_lvds1: endpoint@4 {
1304                                         reg = <4>;
1305                                         remote-endpoint = <&lvds1_mux_0>;
1306                                 };
1307                         };
1308
1309                         ipu1_di1: port@3 {
1310                                 #address-cells = <1>;
1311                                 #size-cells = <0>;
1312                                 reg = <3>;
1313
1314                                 ipu1_di1_disp1: endpoint@0 {
1315                                         reg = <0>;
1316                                 };
1317
1318                                 ipu1_di1_hdmi: endpoint@1 {
1319                                         reg = <1>;
1320                                         remote-endpoint = <&hdmi_mux_1>;
1321                                 };
1322
1323                                 ipu1_di1_mipi: endpoint@2 {
1324                                         reg = <2>;
1325                                         remote-endpoint = <&mipi_mux_1>;
1326                                 };
1327
1328                                 ipu1_di1_lvds0: endpoint@3 {
1329                                         reg = <3>;
1330                                         remote-endpoint = <&lvds0_mux_1>;
1331                                 };
1332
1333                                 ipu1_di1_lvds1: endpoint@4 {
1334                                         reg = <4>;
1335                                         remote-endpoint = <&lvds1_mux_1>;
1336                                 };
1337                         };
1338                 };
1339         };
1340 };