arch/arm/dts/imx6qdl-gw5904.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 led1 = &led1;
  57                 led2 = &led2;
  58                 mmc0 = &usdhc3;
  59                 usb0 = &usbh1;
  60                 usb1 = &usbotg;
  61         };
  62
  63         chosen {
  64                 stdout-path = &uart2;
  65         };
  66
  67         backlight {
  68                 compatible = "pwm-backlight";
  69                 pwms = <&pwm4 0 5000000>;
  70                 brightness-levels = <0 4 8 16 32 64 128 255>;
  71                 default-brightness-level = <7>;
  72         };
  73
  74         gpio-keys {
  75                 compatible = "gpio-keys";
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78
  79                 user-pb {
  80                         label = "user_pb";
  81                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  82                         linux,code = <BTN_0>;
  83                 };
  84
  85                 user-pb1x {
  86                         label = "user_pb1x";
  87                         linux,code = <BTN_1>;
  88                         interrupt-parent = <&gsc>;
  89                         interrupts = <0>;
  90                 };
  91
  92                 key-erased {
  93                         label = "key-erased";
  94                         linux,code = <BTN_2>;
  95                         interrupt-parent = <&gsc>;
  96                         interrupts = <1>;
  97                 };
  98
  99                 eeprom-wp {
 100                         label = "eeprom_wp";
 101                         linux,code = <BTN_3>;
 102                         interrupt-parent = <&gsc>;
 103                         interrupts = <2>;
 104                 };
 105
 106                 tamper {
 107                         label = "tamper";
 108                         linux,code = <BTN_4>;
 109                         interrupt-parent = <&gsc>;
 110                         interrupts = <5>;
 111                 };
 112
 113                 switch-hold {
 114                         label = "switch_hold";
 115                         linux,code = <BTN_5>;
 116                         interrupt-parent = <&gsc>;
 117                         interrupts = <7>;
 118                 };
 119         };
 120
 121         leds {
 122                 compatible = "gpio-leds";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_gpio_leds>;
 125
 126                 led0: user1 {
 127                         label = "user1";
 128                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 129                         default-state = "on";
 130                         linux,default-trigger = "heartbeat";
 131                 };
 132
 133                 led1: user2 {
 134                         label = "user2";
 135                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 136                         default-state = "off";
 137                 };
 138
 139                 led2: user3 {
 140                         label = "user3";
 141                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 142                         default-state = "off";
 143                 };
 144         };
 145
 146         memory@10000000 {
 147                 device_type = "memory";
 148                 reg = <0x10000000 0x40000000>;
 149         };
 150
 151         pps {
 152                 compatible = "pps-gpio";
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&pinctrl_pps>;
 155                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 156         };
 157
 158         reg_1p0v: regulator-1p0v {
 159                 compatible = "regulator-fixed";
 160                 regulator-name = "1P0V";
 161                 regulator-min-microvolt = <1000000>;
 162                 regulator-max-microvolt = <1000000>;
 163                 regulator-always-on;
 164         };
 165
 166         reg_3p3v: regulator-3p3v {
 167                 compatible = "regulator-fixed";
 168                 regulator-name = "3P3V";
 169                 regulator-min-microvolt = <3300000>;
 170                 regulator-max-microvolt = <3300000>;
 171                 regulator-always-on;
 172         };
 173
 174         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 175                 compatible = "regulator-fixed";
 176                 regulator-name = "usb_h1_vbus";
 177                 regulator-min-microvolt = <5000000>;
 178                 regulator-max-microvolt = <5000000>;
 179                 regulator-always-on;
 180         };
 181
 182         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 183                 compatible = "regulator-fixed";
 184                 regulator-name = "usb_otg_vbus";
 185                 regulator-min-microvolt = <5000000>;
 186                 regulator-max-microvolt = <5000000>;
 187                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 188                 enable-active-high;
 189         };
 190 };
 191
 192 &clks {
 193         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 194                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 195         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 196                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 197 };
 198
 199 &fec {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_enet>;
 202         phy-mode = "rgmii-id";
 203         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 204         phy-reset-duration = <10>;
 205         phy-reset-post-delay = <100>;
 206         status = "okay";
 207
 208         fixed-link {
 209                 speed = <1000>;
 210                 full-duplex;
 211         };
 212
 213         mdio {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 switch@0 {
 218                         compatible = "marvell,mv88e6085";
 219                         reg = <0>;
 220
 221                         ports {
 222                                 #address-cells = <1>;
 223                                 #size-cells = <0>;
 224
 225                                 port@0 {
 226                                         reg = <0>;
 227                                         label = "lan4";
 228                                 };
 229
 230                                 port@1 {
 231                                         reg = <1>;
 232                                         label = "lan3";
 233                                 };
 234
 235                                 port@2 {
 236                                         reg = <2>;
 237                                         label = "lan2";
 238                                 };
 239
 240                                 port@3 {
 241                                         reg = <3>;
 242                                         label = "lan1";
 243                                 };
 244
 245                                 port@5 {
 246                                         reg = <5>;
 247                                         label = "cpu";
 248                                         ethernet = <&fec>;
 249                                 };
 250                         };
 251                 };
 252         };
 253 };
 254
 255 &i2c1 {
 256         clock-frequency = <100000>;
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_i2c1>;
 259         status = "okay";
 260
 261         gsc: gsc@20 {
 262                 compatible = "gw,gsc";
 263                 reg = <0x20>;
 264                 interrupt-parent = <&gpio1>;
 265                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 266                 interrupt-controller;
 267                 #interrupt-cells = <1>;
 268                 #size-cells = <0>;
 269
 270                 adc {
 271                         compatible = "gw,gsc-adc";
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274
 275                         channel@0 {
 276                                 gw,mode = <0>;
 277                                 reg = <0x00>;
 278                                 label = "temp";
 279                         };
 280
 281                         channel@2 {
 282                                 gw,mode = <1>;
 283                                 reg = <0x02>;
 284                                 label = "vdd_vin";
 285                         };
 286
 287                         channel@5 {
 288                                 gw,mode = <1>;
 289                                 reg = <0x05>;
 290                                 label = "vdd_3p3";
 291                         };
 292
 293                         channel@8 {
 294                                 gw,mode = <1>;
 295                                 reg = <0x08>;
 296                                 label = "vdd_bat";
 297                         };
 298
 299                         channel@b {
 300                                 gw,mode = <1>;
 301                                 reg = <0x0b>;
 302                                 label = "vdd_5p0";
 303                         };
 304
 305                         channel@e {
 306                                 gw,mode = <1>;
 307                                 reg = <0xe>;
 308                                 label = "vdd_arm";
 309                         };
 310
 311                         channel@11 {
 312                                 gw,mode = <1>;
 313                                 reg = <0x11>;
 314                                 label = "vdd_soc";
 315                         };
 316
 317                         channel@14 {
 318                                 gw,mode = <1>;
 319                                 reg = <0x14>;
 320                                 label = "vdd_3p0";
 321                         };
 322
 323                         channel@17 {
 324                                 gw,mode = <1>;
 325                                 reg = <0x17>;
 326                                 label = "vdd_1p5";
 327                         };
 328
 329                         channel@1d {
 330                                 gw,mode = <1>;
 331                                 reg = <0x1d>;
 332                                 label = "vdd_1p8";
 333                         };
 334
 335                         channel@20 {
 336                                 gw,mode = <1>;
 337                                 reg = <0x20>;
 338                                 label = "vdd_an1";
 339                         };
 340
 341                         channel@23 {
 342                                 gw,mode = <1>;
 343                                 reg = <0x23>;
 344                                 label = "vdd_2p5";
 345                         };
 346                 };
 347         };
 348
 349         gsc_gpio: gpio@23 {
 350                 compatible = "nxp,pca9555";
 351                 reg = <0x23>;
 352                 gpio-controller;
 353                 #gpio-cells = <2>;
 354                 interrupt-parent = <&gsc>;
 355                 interrupts = <4>;
 356         };
 357
 358         eeprom1: eeprom@50 {
 359                 compatible = "atmel,24c02";
 360                 reg = <0x50>;
 361                 pagesize = <16>;
 362         };
 363
 364         eeprom2: eeprom@51 {
 365                 compatible = "atmel,24c02";
 366                 reg = <0x51>;
 367                 pagesize = <16>;
 368         };
 369
 370         eeprom3: eeprom@52 {
 371                 compatible = "atmel,24c02";
 372                 reg = <0x52>;
 373                 pagesize = <16>;
 374         };
 375
 376         eeprom4: eeprom@53 {
 377                 compatible = "atmel,24c02";
 378                 reg = <0x53>;
 379                 pagesize = <16>;
 380         };
 381
 382         dts1672: rtc@68 {
 383                 compatible = "dallas,ds1672";
 384                 reg = <0x68>;
 385         };
 386 };
 387
 388 &i2c2 {
 389         clock-frequency = <100000>;
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_i2c2>;
 392         status = "okay";
 393
 394         magn@1c {
 395                 compatible = "st,lsm9ds1-magn";
 396                 reg = <0x1c>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&pinctrl_mag>;
 399                 interrupt-parent = <&gpio5>;
 400                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 401         };
 402
 403         ltc3676: pmic@3c {
 404                 compatible = "lltc,ltc3676";
 405                 reg = <0x3c>;
 406                 interrupt-parent = <&gpio1>;
 407                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 408
 409                 regulators {
 410                         /* VDD_SOC (1+R1/R2 = 1.635) */
 411                         reg_vdd_soc: sw1 {
 412                                 regulator-name = "vddsoc";
 413                                 regulator-min-microvolt = <674400>;
 414                                 regulator-max-microvolt = <1308000>;
 415                                 lltc,fb-voltage-divider = <127000 200000>;
 416                                 regulator-ramp-delay = <7000>;
 417                                 regulator-boot-on;
 418                                 regulator-always-on;
 419                         };
 420
 421                         /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
 422                         reg_1p8v: sw2 {
 423                                 regulator-name = "vdd1p8";
 424                                 regulator-min-microvolt = <1033310>;
 425                                 regulator-max-microvolt = <2004000>;
 426                                 lltc,fb-voltage-divider = <301000 200000>;
 427                                 regulator-ramp-delay = <7000>;
 428                                 regulator-boot-on;
 429                                 regulator-always-on;
 430                         };
 431
 432                         /* VDD_ARM (1+R1/R2 = 1.635) */
 433                         reg_vdd_arm: sw3 {
 434                                 regulator-name = "vddarm";
 435                                 regulator-min-microvolt = <674400>;
 436                                 regulator-max-microvolt = <1308000>;
 437                                 lltc,fb-voltage-divider = <127000 200000>;
 438                                 regulator-ramp-delay = <7000>;
 439                                 regulator-boot-on;
 440                                 regulator-always-on;
 441                         };
 442
 443                         /* VDD_DDR (1+R1/R2 = 2.105) */
 444                         reg_vdd_ddr: sw4 {
 445                                 regulator-name = "vddddr";
 446                                 regulator-min-microvolt = <868310>;
 447                                 regulator-max-microvolt = <1684000>;
 448                                 lltc,fb-voltage-divider = <221000 200000>;
 449                                 regulator-ramp-delay = <7000>;
 450                                 regulator-boot-on;
 451                                 regulator-always-on;
 452                         };
 453
 454                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 455                         reg_2p5v: ldo2 {
 456                                 regulator-name = "vdd2p5";
 457                                 regulator-min-microvolt = <2490375>;
 458                                 regulator-max-microvolt = <2490375>;
 459                                 lltc,fb-voltage-divider = <487000 200000>;
 460                                 regulator-boot-on;
 461                                 regulator-always-on;
 462                         };
 463
 464                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 465                         reg_3p0v: ldo4 {
 466                                 regulator-name = "vdd3p0";
 467                                 regulator-min-microvolt = <3023250>;
 468                                 regulator-max-microvolt = <3023250>;
 469                                 lltc,fb-voltage-divider = <634000 200000>;
 470                                 regulator-boot-on;
 471                                 regulator-always-on;
 472                         };
 473                 };
 474         };
 475
 476         imu@6a {
 477                 compatible = "st,lsm9ds1-imu";
 478                 reg = <0x6a>;
 479                 st,drdy-int-pin = <1>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&pinctrl_imu>;
 482                 interrupt-parent = <&gpio4>;
 483                 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
 484         };
 485 };
 486
 487 &i2c3 {
 488         clock-frequency = <100000>;
 489         pinctrl-names = "default";
 490         pinctrl-0 = <&pinctrl_i2c3>;
 491         status = "okay";
 492
 493         egalax_ts: touchscreen@4 {
 494                 compatible = "eeti,egalax_ts";
 495                 reg = <0x04>;
 496                 interrupt-parent = <&gpio1>;
 497                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 498                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 499         };
 500 };
 501
 502 &ldb {
 503         status = "okay";
 504
 505         lvds-channel@0 {
 506                 fsl,data-mapping = "spwg";
 507                 fsl,data-width = <18>;
 508                 status = "okay";
 509
 510                 display-timings {
 511                         native-mode = <&timing0>;
 512                         timing0: hsd100pxn1 {
 513                                 clock-frequency = <65000000>;
 514                                 hactive = <1024>;
 515                                 vactive = <768>;
 516                                 hback-porch = <220>;
 517                                 hfront-porch = <40>;
 518                                 vback-porch = <21>;
 519                                 vfront-porch = <7>;
 520                                 hsync-len = <60>;
 521                                 vsync-len = <10>;
 522                         };
 523                 };
 524         };
 525 };
 526
 527 &pcie {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&pinctrl_pcie>;
 530         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 531         status = "okay";
 532 };
 533
 534 &pwm2 {
 535         pinctrl-names = "default";
 536         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 537         status = "disabled";
 538 };
 539
 540 &pwm3 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 543         status = "disabled";
 544 };
 545
 546 &pwm4 {
 547         #pwm-cells = <2>;
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&pinctrl_pwm4>;
 550         status = "okay";
 551 };
 552
 553 &uart1 {
 554         pinctrl-names = "default";
 555         pinctrl-0 = <&pinctrl_uart1>;
 556         status = "okay";
 557 };
 558
 559 &uart2 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&pinctrl_uart2>;
 562         status = "okay";
 563 };
 564
 565 &uart3 {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&pinctrl_uart3>;
 568         uart-has-rtscts;
 569         status = "okay";
 570 };
 571
 572 &uart4 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&pinctrl_uart4>;
 575         uart-has-rtscts;
 576         status = "okay";
 577 };
 578
 579 &uart5 {
 580         pinctrl-names = "default";
 581         pinctrl-0 = <&pinctrl_uart5>;
 582         status = "okay";
 583 };
 584
 585 &usbotg {
 586         vbus-supply = <&reg_usb_otg_vbus>;
 587         pinctrl-names = "default";
 588         pinctrl-0 = <&pinctrl_usbotg>;
 589         disable-over-current;
 590         dr_mode = "otg";
 591         status = "okay";
 592 };
 593
 594 &usbh1 {
 595         vbus-supply = <&reg_usb_h1_vbus>;
 596         status = "okay";
 597 };
 598
 599 &usdhc3 {
 600         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 601         pinctrl-0 = <&pinctrl_usdhc3>;
 602         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 603         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 604         non-removable;
 605         vmmc-supply = <&reg_3p3v>;
 606         keep-power-in-suspend;
 607         status = "okay";
 608 };
 609
 610 &wdog1 {
 611         pinctrl-names = "default";
 612         pinctrl-0 = <&pinctrl_wdog>;
 613         fsl,ext-reset-output;
 614 };
 615
 616 &iomuxc {
 617         pinctrl_enet: enetgrp {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 620                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 621                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 622                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 623                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 624                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 625                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 626                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 627                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 628                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 629                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 630                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 631                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 632                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 633                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 634                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 635                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 636                 >;
 637         };
 638
 639         pinctrl_gpio_leds: gpioledsgrp {
 640                 fsl,pins = <
 641                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 642                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 643                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 644                 >;
 645         };
 646
 647         pinctrl_i2c1: i2c1grp {
 648                 fsl,pins = <
 649                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 650                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 651                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 652                 >;
 653         };
 654
 655         pinctrl_i2c2: i2c2grp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 658                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 659                 >;
 660         };
 661
 662         pinctrl_i2c3: i2c3grp {
 663                 fsl,pins = <
 664                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 665                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 666                 >;
 667         };
 668
 669         pinctrl_imu: imugrp {
 670                 fsl,pins = <
 671                         MX6QDL_PAD_DI0_PIN2__GPIO4_IO18         0x1b0b0
 672                 >;
 673         };
 674
 675         pinctrl_mag: maggrp {
 676                 fsl,pins = <
 677                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 678                 >;
 679         };
 680
 681         pinctrl_pcie: pciegrp {
 682                 fsl,pins = <
 683                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
 684                 >;
 685         };
 686
 687         pinctrl_pmic: pmicgrp {
 688                 fsl,pins = <
 689                         MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
 690                 >;
 691         };
 692
 693         pinctrl_pps: ppsgrp {
 694                 fsl,pins = <
 695                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 696                 >;
 697         };
 698
 699         pinctrl_pwm2: pwm2grp {
 700                 fsl,pins = <
 701                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 702                 >;
 703         };
 704
 705         pinctrl_pwm3: pwm3grp {
 706                 fsl,pins = <
 707                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 708                 >;
 709         };
 710
 711         pinctrl_pwm4: pwm4grp {
 712                 fsl,pins = <
 713                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 714                 >;
 715         };
 716
 717         pinctrl_uart1: uart1grp {
 718                 fsl,pins = <
 719                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 720                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 721                 >;
 722         };
 723
 724         pinctrl_uart2: uart2grp {
 725                 fsl,pins = <
 726                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 727                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 728                 >;
 729         };
 730
 731         pinctrl_uart3: uart3grp {
 732                 fsl,pins = <
 733                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 734                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 735                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 736                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 737                 >;
 738         };
 739
 740         pinctrl_uart4: uart4grp {
 741                 fsl,pins = <
 742                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 743                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 744                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 745                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 746                 >;
 747         };
 748
 749         pinctrl_uart5: uart5grp {
 750                 fsl,pins = <
 751                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 752                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 753                 >;
 754         };
 755
 756         pinctrl_usbotg: usbotggrp {
 757                 fsl,pins = <
 758                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 759                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 760                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 761                 >;
 762         };
 763
 764         pinctrl_usdhc3: usdhc3grp {
 765                 fsl,pins = <
 766                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 767                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 768                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 769                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 770                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 771                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 772                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 773                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 774                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 775                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 776                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 777                 >;
 778         };
 779
 780         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 781                 fsl,pins = <
 782                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 783                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 784                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 785                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 786                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 787                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 788                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 789                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 790                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 791                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 792                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 793                 >;
 794         };
 795
 796         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 797                 fsl,pins = <
 798                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 799                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 800                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 801                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 802                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 803                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 804                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 805                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 806                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 807                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 808                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 809                 >;
 810         };
 811
 812         pinctrl_wdog: wdoggrp {
 813                 fsl,pins = <
 814                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 815                 >;
 816         };
 817 };