arch/arm/dts/imx6qdl-gw560x.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/input.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 led1 = &led1;
  57                 led2 = &led2;
  58                 mmc0 = &usdhc2;
  59                 mmc1 = &usdhc3;
  60                 ssi0 = &ssi1;
  61                 usb0 = &usbh1;
  62                 usb1 = &usbotg;
  63         };
  64
  65         chosen {
  66                 stdout-path = &uart2;
  67         };
  68
  69         backlight-display {
  70                 compatible = "pwm-backlight";
  71                 pwms = <&pwm4 0 5000000>;
  72                 brightness-levels = <
  73                         0  1  2  3  4  5  6  7  8  9
  74                         10 11 12 13 14 15 16 17 18 19
  75                         20 21 22 23 24 25 26 27 28 29
  76                         30 31 32 33 34 35 36 37 38 39
  77                         40 41 42 43 44 45 46 47 48 49
  78                         50 51 52 53 54 55 56 57 58 59
  79                         60 61 62 63 64 65 66 67 68 69
  80                         70 71 72 73 74 75 76 77 78 79
  81                         80 81 82 83 84 85 86 87 88 89
  82                         90 91 92 93 94 95 96 97 98 99
  83                         100
  84                         >;
  85                 default-brightness-level = <100>;
  86         };
  87
  88         backlight-keypad {
  89                 compatible = "gpio-backlight";
  90                 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
  91                 default-on;
  92         };
  93
  94         gpio-keys {
  95                 compatible = "gpio-keys";
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98
  99                 user-pb {
 100                         label = "user_pb";
 101                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
 102                         linux,code = <BTN_0>;
 103                 };
 104
 105                 user-pb1x {
 106                         label = "user_pb1x";
 107                         linux,code = <BTN_1>;
 108                         interrupt-parent = <&gsc>;
 109                         interrupts = <0>;
 110                 };
 111
 112                 key-erased {
 113                         label = "key-erased";
 114                         linux,code = <BTN_2>;
 115                         interrupt-parent = <&gsc>;
 116                         interrupts = <1>;
 117                 };
 118
 119                 eeprom-wp {
 120                         label = "eeprom_wp";
 121                         linux,code = <BTN_3>;
 122                         interrupt-parent = <&gsc>;
 123                         interrupts = <2>;
 124                 };
 125
 126                 tamper {
 127                         label = "tamper";
 128                         linux,code = <BTN_4>;
 129                         interrupt-parent = <&gsc>;
 130                         interrupts = <5>;
 131                 };
 132
 133                 switch-hold {
 134                         label = "switch_hold";
 135                         linux,code = <BTN_5>;
 136                         interrupt-parent = <&gsc>;
 137                         interrupts = <7>;
 138                 };
 139         };
 140
 141         leds {
 142                 compatible = "gpio-leds";
 143                 pinctrl-names = "default";
 144                 pinctrl-0 = <&pinctrl_gpio_leds>;
 145
 146                 led0: user1 {
 147                         label = "user1";
 148                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 149                         default-state = "on";
 150                         linux,default-trigger = "heartbeat";
 151                 };
 152
 153                 led1: user2 {
 154                         label = "user2";
 155                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 156                         default-state = "off";
 157                 };
 158
 159                 led2: user3 {
 160                         label = "user3";
 161                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 162                         default-state = "off";
 163                 };
 164         };
 165
 166         memory@10000000 {
 167                 device_type = "memory";
 168                 reg = <0x10000000 0x40000000>;
 169         };
 170
 171         pps {
 172                 compatible = "pps-gpio";
 173                 pinctrl-names = "default";
 174                 pinctrl-0 = <&pinctrl_pps>;
 175                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 176         };
 177
 178         reg_2p5v: regulator-2p5v {
 179                 compatible = "regulator-fixed";
 180                 regulator-name = "2P5V";
 181                 regulator-min-microvolt = <2500000>;
 182                 regulator-max-microvolt = <2500000>;
 183                 regulator-always-on;
 184         };
 185
 186         reg_3p3v: regulator-3p3v {
 187                 compatible = "regulator-fixed";
 188                 regulator-name = "3P3V";
 189                 regulator-min-microvolt = <3300000>;
 190                 regulator-max-microvolt = <3300000>;
 191                 regulator-always-on;
 192         };
 193
 194         reg_5p0v: regulator-5p0v {
 195                 compatible = "regulator-fixed";
 196                 regulator-name = "5P0V";
 197                 regulator-min-microvolt = <5000000>;
 198                 regulator-max-microvolt = <5000000>;
 199                 regulator-always-on;
 200         };
 201
 202         reg_12p0v: regulator-12p0v {
 203                 compatible = "regulator-fixed";
 204                 regulator-name = "12P0V";
 205                 regulator-min-microvolt = <12000000>;
 206                 regulator-max-microvolt = <12000000>;
 207                 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 208                 enable-active-high;
 209         };
 210
 211         reg_1p4v: regulator-vddsoc {
 212                 compatible = "regulator-fixed";
 213                 regulator-name = "vdd_soc";
 214                 regulator-min-microvolt = <1400000>;
 215                 regulator-max-microvolt = <1400000>;
 216                 regulator-always-on;
 217         };
 218
 219         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 220                 compatible = "regulator-fixed";
 221                 regulator-name = "usb_h1_vbus";
 222                 regulator-min-microvolt = <5000000>;
 223                 regulator-max-microvolt = <5000000>;
 224                 regulator-always-on;
 225         };
 226
 227         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 228                 compatible = "regulator-fixed";
 229                 regulator-name = "usb_otg_vbus";
 230                 regulator-min-microvolt = <5000000>;
 231                 regulator-max-microvolt = <5000000>;
 232                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 233                 enable-active-high;
 234         };
 235
 236         sound {
 237                 compatible = "fsl,imx6q-ventana-sgtl5000",
 238                              "fsl,imx-audio-sgtl5000";
 239                 model = "sgtl5000-audio";
 240                 ssi-controller = <&ssi1>;
 241                 audio-codec = <&sgtl5000>;
 242                 audio-routing =
 243                         "MIC_IN", "Mic Jack",
 244                         "Mic Jack", "Mic Bias",
 245                         "Headphone Jack", "HP_OUT";
 246                 mux-int-port = <1>;
 247                 mux-ext-port = <4>;
 248         };
 249 };
 250
 251 &audmux {
 252         pinctrl-names = "default";
 253         pinctrl-0 = <&pinctrl_audmux>;
 254         status = "okay";
 255 };
 256
 257 &ecspi3 {
 258         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_ecspi3>;
 261         status = "okay";
 262 };
 263
 264 &can1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_flexcan>;
 267         status = "okay";
 268 };
 269
 270 &clks {
 271         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 272                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 273         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 274                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 275 };
 276
 277 &fec {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_enet>;
 280         phy-mode = "rgmii-id";
 281         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 282         phy-reset-duration = <10>;
 283         phy-reset-post-delay = <100>;
 284         status = "okay";
 285 };
 286
 287 &hdmi {
 288         ddc-i2c-bus = <&i2c3>;
 289         status = "okay";
 290 };
 291
 292 &i2c1 {
 293         clock-frequency = <100000>;
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_i2c1>;
 296         status = "okay";
 297
 298         gsc: gsc@20 {
 299                 compatible = "gw,gsc";
 300                 reg = <0x20>;
 301                 interrupt-parent = <&gpio1>;
 302                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 303                 interrupt-controller;
 304                 #interrupt-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 adc {
 308                         compatible = "gw,gsc-adc";
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311
 312                         channel@0 {
 313                                 gw,mode = <0>;
 314                                 reg = <0x00>;
 315                                 label = "temp";
 316                         };
 317
 318                         channel@2 {
 319                                 gw,mode = <1>;
 320                                 reg = <0x02>;
 321                                 label = "vdd_vin";
 322                         };
 323
 324                         channel@5 {
 325                                 gw,mode = <1>;
 326                                 reg = <0x05>;
 327                                 label = "vdd_3p3";
 328                         };
 329
 330                         channel@8 {
 331                                 gw,mode = <1>;
 332                                 reg = <0x08>;
 333                                 label = "vdd_bat";
 334                         };
 335
 336                         channel@b {
 337                                 gw,mode = <1>;
 338                                 reg = <0x0b>;
 339                                 label = "vdd_5p0";
 340                         };
 341
 342                         channel@e {
 343                                 gw,mode = <1>;
 344                                 reg = <0xe>;
 345                                 label = "vdd_arm";
 346                         };
 347
 348                         channel@11 {
 349                                 gw,mode = <1>;
 350                                 reg = <0x11>;
 351                                 label = "vdd_soc";
 352                         };
 353
 354                         channel@14 {
 355                                 gw,mode = <1>;
 356                                 reg = <0x14>;
 357                                 label = "vdd_3p0";
 358                         };
 359
 360                         channel@17 {
 361                                 gw,mode = <1>;
 362                                 reg = <0x17>;
 363                                 label = "vdd_1p5";
 364                         };
 365
 366                         channel@1d {
 367                                 gw,mode = <1>;
 368                                 reg = <0x1d>;
 369                                 label = "vdd_1p8";
 370                         };
 371
 372                         channel@20 {
 373                                 gw,mode = <1>;
 374                                 reg = <0x20>;
 375                                 label = "vdd_an1";
 376                         };
 377
 378                         channel@23 {
 379                                 gw,mode = <1>;
 380                                 reg = <0x23>;
 381                                 label = "vdd_2p5";
 382                         };
 383
 384                         channel@26 {
 385                                 gw,mode = <1>;
 386                                 reg = <0x26>;
 387                                 label = "vdd_gps";
 388                         };
 389
 390                         channel@29 {
 391                                 gw,mode = <1>;
 392                                 reg = <0x29>;
 393                                 label = "vdd_an2";
 394                         };
 395                 };
 396         };
 397
 398         gsc_gpio: gpio@23 {
 399                 compatible = "nxp,pca9555";
 400                 reg = <0x23>;
 401                 gpio-controller;
 402                 #gpio-cells = <2>;
 403                 interrupt-parent = <&gsc>;
 404                 interrupts = <4>;
 405         };
 406
 407         eeprom1: eeprom@50 {
 408                 compatible = "atmel,24c02";
 409                 reg = <0x50>;
 410                 pagesize = <16>;
 411         };
 412
 413         eeprom2: eeprom@51 {
 414                 compatible = "atmel,24c02";
 415                 reg = <0x51>;
 416                 pagesize = <16>;
 417         };
 418
 419         eeprom3: eeprom@52 {
 420                 compatible = "atmel,24c02";
 421                 reg = <0x52>;
 422                 pagesize = <16>;
 423         };
 424
 425         eeprom4: eeprom@53 {
 426                 compatible = "atmel,24c02";
 427                 reg = <0x53>;
 428                 pagesize = <16>;
 429         };
 430
 431         ds1672: rtc@68 {
 432                 compatible = "dallas,ds1672";
 433                 reg = <0x68>;
 434         };
 435 };
 436
 437 &i2c2 {
 438         clock-frequency = <100000>;
 439         pinctrl-names = "default";
 440         pinctrl-0 = <&pinctrl_i2c2>;
 441         status = "okay";
 442
 443         sgtl5000: codec@a {
 444                 compatible = "fsl,sgtl5000";
 445                 reg = <0x0a>;
 446                 #sound-dai-cells = <0>;
 447                 clocks = <&clks IMX6QDL_CLK_CKO>;
 448                 VDDA-supply = <&reg_1p8v>;
 449                 VDDIO-supply = <&reg_3p3v>;
 450         };
 451
 452         magn@1c {
 453                 compatible = "st,lsm9ds1-magn";
 454                 reg = <0x1c>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&pinctrl_mag>;
 457                 interrupt-parent = <&gpio5>;
 458                 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
 459         };
 460
 461         tca8418: keypad@34 {
 462                 compatible = "ti,tca8418";
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&pinctrl_keypad>;
 465                 reg = <0x34>;
 466                 interrupt-parent = <&gpio5>;
 467                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 468                 linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
 469                                  MATRIX_KEY(0x00, 0x00, BTN_1)
 470                                  MATRIX_KEY(0x01, 0x01, BTN_2)
 471                                  MATRIX_KEY(0x01, 0x00, BTN_3)
 472                                  MATRIX_KEY(0x02, 0x00, BTN_4)
 473                                  MATRIX_KEY(0x00, 0x03, BTN_5)
 474                                  MATRIX_KEY(0x00, 0x02, BTN_6)
 475                                  MATRIX_KEY(0x01, 0x03, BTN_7)
 476                                  MATRIX_KEY(0x01, 0x02, BTN_8)
 477                                  MATRIX_KEY(0x02, 0x02, BTN_9)
 478                 >;
 479                 keypad,num-rows = <4>;
 480                 keypad,num-columns = <4>;
 481         };
 482
 483         ltc3676: pmic@3c {
 484                 compatible = "lltc,ltc3676";
 485                 pinctrl-names = "default";
 486                 pinctrl-0 = <&pinctrl_pmic>;
 487                 reg = <0x3c>;
 488                 interrupt-parent = <&gpio1>;
 489                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 490
 491                 regulators {
 492                         /* VDD_DDR (1+R1/R2 = 2.105) */
 493                         reg_vdd_ddr: sw2 {
 494                                 regulator-name = "vddddr";
 495                                 regulator-min-microvolt = <868310>;
 496                                 regulator-max-microvolt = <1684000>;
 497                                 lltc,fb-voltage-divider = <221000 200000>;
 498                                 regulator-ramp-delay = <7000>;
 499                                 regulator-boot-on;
 500                                 regulator-always-on;
 501                         };
 502
 503                         /* VDD_ARM (1+R1/R2 = 1.931) */
 504                         reg_vdd_arm: sw3 {
 505                                 regulator-name = "vddarm";
 506                                 regulator-min-microvolt = <796551>;
 507                                 regulator-max-microvolt = <1544827>;
 508                                 lltc,fb-voltage-divider = <243000 261000>;
 509                                 regulator-ramp-delay = <7000>;
 510                                 regulator-boot-on;
 511                                 regulator-always-on;
 512                                 linux,phandle = <&reg_vdd_arm>;
 513                         };
 514
 515                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 516                         reg_1p8v: sw4 {
 517                                 regulator-name = "vdd1p8";
 518                                 regulator-min-microvolt = <1033310>;
 519                                 regulator-max-microvolt = <2004000>;
 520                                 lltc,fb-voltage-divider = <301000 200000>;
 521                                 regulator-ramp-delay = <7000>;
 522                                 regulator-boot-on;
 523                                 regulator-always-on;
 524                         };
 525
 526                         /* VDD_1P0 (1+R1/R2 = 1.39): PCIe/ENET-PHY */
 527                         reg_1p0v: ldo2 {
 528                                 regulator-name = "vdd1p0";
 529                                 regulator-min-microvolt = <950000>;
 530                                 regulator-max-microvolt = <1050000>;
 531                                 lltc,fb-voltage-divider = <78700 200000>;
 532                                 regulator-boot-on;
 533                                 regulator-always-on;
 534                         };
 535
 536                         /* VDD_AUD_1P8: Audio codec */
 537                         reg_aud_1p8v: ldo3 {
 538                                 regulator-name = "vdd1p8a";
 539                                 regulator-min-microvolt = <1800000>;
 540                                 regulator-max-microvolt = <1800000>;
 541                                 regulator-boot-on;
 542                         };
 543
 544                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 545                         reg_3p0v: ldo4 {
 546                                 regulator-name = "vdd3p0";
 547                                 regulator-min-microvolt = <3023250>;
 548                                 regulator-max-microvolt = <3023250>;
 549                                 lltc,fb-voltage-divider = <634000 200000>;
 550                                 regulator-boot-on;
 551                                 regulator-always-on;
 552                         };
 553                 };
 554         };
 555
 556         imu@6a {
 557                 compatible = "st,lsm9ds1-imu";
 558                 reg = <0x6a>;
 559                 st,drdy-int-pin = <1>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&pinctrl_imu>;
 562                 interrupt-parent = <&gpio5>;
 563                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
 564         };
 565 };
 566
 567 &i2c3 {
 568         clock-frequency = <100000>;
 569         pinctrl-names = "default";
 570         pinctrl-0 = <&pinctrl_i2c3>;
 571         status = "okay";
 572
 573         egalax_ts: touchscreen@4 {
 574                 compatible = "eeti,egalax_ts";
 575                 reg = <0x04>;
 576                 interrupt-parent = <&gpio5>;
 577                 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
 578                 wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 579         };
 580 };
 581
 582 &ldb {
 583         fsl,dual-channel;
 584         status = "okay";
 585
 586         lvds-channel@0 {
 587                 fsl,data-mapping = "spwg";
 588                 fsl,data-width = <18>;
 589                 status = "okay";
 590
 591                 display-timings {
 592                         native-mode = <&timing0>;
 593                         timing0: hsd100pxn1 {
 594                                 clock-frequency = <65000000>;
 595                                 hactive = <1024>;
 596                                 vactive = <768>;
 597                                 hback-porch = <220>;
 598                                 hfront-porch = <40>;
 599                                 vback-porch = <21>;
 600                                 vfront-porch = <7>;
 601                                 hsync-len = <60>;
 602                                 vsync-len = <10>;
 603                         };
 604                 };
 605         };
 606 };
 607
 608 &pcie {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&pinctrl_pcie>;
 611         reset-gpio = <&gpio4 31 GPIO_ACTIVE_LOW>;
 612         status = "okay";
 613 };
 614
 615 &pwm2 {
 616         pinctrl-names = "default";
 617         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 618         status = "disabled";
 619 };
 620
 621 &pwm3 {
 622         pinctrl-names = "default";
 623         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 624         status = "disabled";
 625 };
 626
 627 &pwm4 {
 628         #pwm-cells = <2>;
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&pinctrl_pwm4>;
 631         status = "okay";
 632 };
 633
 634 &ssi1 {
 635         status = "okay";
 636 };
 637
 638 &uart1 {
 639         pinctrl-names = "default";
 640         pinctrl-0 = <&pinctrl_uart1>;
 641         uart-has-rtscts;
 642         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 643         status = "okay";
 644 };
 645
 646 &uart2 {
 647         pinctrl-names = "default";
 648         pinctrl-0 = <&pinctrl_uart2>;
 649         status = "okay";
 650 };
 651
 652 &uart5 {
 653         pinctrl-names = "default";
 654         pinctrl-0 = <&pinctrl_uart5>;
 655         status = "okay";
 656 };
 657
 658 &usbotg {
 659         vbus-supply = <&reg_usb_otg_vbus>;
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pinctrl_usbotg>;
 662         disable-over-current;
 663         dr_mode = "otg";
 664         status = "okay";
 665 };
 666
 667 &usbh1 {
 668         vbus-supply = <&reg_usb_h1_vbus>;
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&pinctrl_usbh1>;
 671         status = "okay";
 672 };
 673
 674 &usdhc2 {
 675         pinctrl-names = "default";
 676         pinctrl-0 = <&pinctrl_usdhc2>;
 677         bus-width = <8>;
 678         vmmc-supply = <&reg_3p3v>;
 679         non-removable;
 680         status = "okay";
 681 };
 682
 683 &usdhc3 {
 684         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 685         pinctrl-0 = <&pinctrl_usdhc3>;
 686         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 687         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 688         cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
 689         vmmc-supply = <&reg_3p3v>;
 690         status = "okay";
 691 };
 692
 693 &wdog1 {
 694         pinctrl-names = "default";
 695         pinctrl-0 = <&pinctrl_wdog>;
 696         fsl,ext-reset-output;
 697 };
 698
 699 &iomuxc {
 700         pinctrl_audmux: audmuxgrp {
 701                 fsl,pins = <
 702                         /* AUD4 */
 703                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 704                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x110b0
 705                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 706                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 707                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 708                         /* AUD6 */
 709                         MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x130b0
 710                         MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x130b0
 711                         MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x130b0
 712                         MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x130b0
 713                 >;
 714         };
 715
 716         pinctrl_ecspi3: escpi3grp {
 717                 fsl,pins = <
 718                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 719                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 720                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 721                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 722                 >;
 723         };
 724
 725         pinctrl_enet: enetgrp {
 726                 fsl,pins = <
 727                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 728                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 729                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 730                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 731                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 732                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 733                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 734                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 735                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 736                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 737                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 738                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 739                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 740                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 741                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 742                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 743                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 744                 >;
 745         };
 746
 747         pinctrl_flexcan: flexcangrp {
 748                 fsl,pins = <
 749                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 750                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 751                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 752                 >;
 753         };
 754
 755         pinctrl_gpio_leds: gpioledsgrp {
 756                 fsl,pins = <
 757                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 758                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 759                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 760                 >;
 761         };
 762
 763         pinctrl_i2c1: i2c1grp {
 764                 fsl,pins = <
 765                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 766                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 767                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 768                 >;
 769         };
 770
 771         pinctrl_i2c2: i2c2grp {
 772                 fsl,pins = <
 773                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 774                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 775                 >;
 776         };
 777
 778         pinctrl_i2c3: i2c3grp {
 779                 fsl,pins = <
 780                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 781                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 782                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x4001b0b0 /* DIOI2C_DIS# */
 783                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x0001b0b0 /* LVDS_TOUCH_IRQ# */
 784                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x0001b0b0 /* LVDS_BACKEN */
 785                 >;
 786         };
 787
 788         pinctrl_imu: imugrp {
 789                 fsl,pins = <
 790                         MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x1b0b0
 791                 >;
 792         };
 793
 794         pinctrl_keypad: keypadgrp {
 795                 fsl,pins = <
 796                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x0001b0b0 /* KEYPAD_IRQ# */
 797                         MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30       0x0001b0b0 /* KEYPAD_LED_EN */
 798                 >;
 799         };
 800
 801         pinctrl_mag: maggrp {
 802                 fsl,pins = <
 803                         MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b0
 804                 >;
 805         };
 806
 807         pinctrl_pcie: pciegrp {
 808                 fsl,pins = <
 809                         MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31      0x1b0b0    /* PCI_RST# */
 810                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b0 /* PCIESKT_WDIS# */
 811                 >;
 812         };
 813
 814         pinctrl_pmic: pmicgrp {
 815                 fsl,pins = <
 816                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 817                 >;
 818         };
 819
 820         pinctrl_pps: ppsgrp {
 821                 fsl,pins = <
 822                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 823                 >;
 824         };
 825
 826         pinctrl_pwm2: pwm2grp {
 827                 fsl,pins = <
 828                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 829                 >;
 830         };
 831
 832         pinctrl_pwm3: pwm3grp {
 833                 fsl,pins = <
 834                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 835                 >;
 836         };
 837
 838         pinctrl_pwm4: pwm4grp {
 839                 fsl,pins = <
 840                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 841                 >;
 842         };
 843
 844         pinctrl_uart1: uart1grp {
 845                 fsl,pins = <
 846                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 847                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 848                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 849                 >;
 850         };
 851
 852         pinctrl_uart2: uart2grp {
 853                 fsl,pins = <
 854                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 855                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 856                 >;
 857         };
 858
 859         pinctrl_uart5: uart5grp {
 860                 fsl,pins = <
 861                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 862                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 863                 >;
 864         };
 865
 866         pinctrl_usbh1: usbh1grp {
 867                 fsl,pins = <
 868                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* USBHUB_RST# */
 869                 >;
 870         };
 871
 872         pinctrl_usbotg: usbotggrp {
 873                 fsl,pins = <
 874                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 875                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 876                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 877                 >;
 878         };
 879
 880         pinctrl_usdhc2: usdhc2grp {
 881                 fsl,pins = <
 882                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
 883                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
 884                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
 885                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
 886                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
 887                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
 888                         MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x170f9
 889                         MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x170f9
 890                         MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x170f9
 891                         MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x170f9
 892                 >;
 893         };
 894
 895         pinctrl_usdhc3: usdhc3grp {
 896                 fsl,pins = <
 897                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 898                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 899                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 900                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 901                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 902                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 903                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 904                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 905                 >;
 906         };
 907
 908         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 909                 fsl,pins = <
 910                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 911                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 912                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 913                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 914                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 915                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 916                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 917                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 918                 >;
 919         };
 920
 921         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 922                 fsl,pins = <
 923                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 924                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 925                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 926                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 927                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 928                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 929                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 930                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 931                 >;
 932         };
 933
 934         pinctrl_wdog: wdoggrp {
 935                 fsl,pins = <
 936                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 937                 >;
 938         };
 939 };