arch/arm/dts/imx6qdl-gw54xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/sound/fsl-imx-audmux.h>
  10
  11 / {
  12         /* these are used by bootloader for disabling nodes */
  13         aliases {
  14                 led0 = &led0;
  15                 led1 = &led1;
  16                 led2 = &led2;
  17                 mmc0 = &usdhc3;
  18                 nand = &gpmi;
  19                 ssi0 = &ssi1;
  20                 usb0 = &usbh1;
  21                 usb1 = &usbotg;
  22         };
  23
  24         chosen {
  25                 bootargs = "console=ttymxc1,115200";
  26         };
  27
  28         backlight {
  29                 compatible = "pwm-backlight";
  30                 pwms = <&pwm4 0 5000000>;
  31                 brightness-levels = <0 4 8 16 32 64 128 255>;
  32                 default-brightness-level = <7>;
  33         };
  34
  35         gpio-keys {
  36                 compatible = "gpio-keys";
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 user-pb {
  41                         label = "user_pb";
  42                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  43                         linux,code = <BTN_0>;
  44                 };
  45
  46                 user-pb1x {
  47                         label = "user_pb1x";
  48                         linux,code = <BTN_1>;
  49                         interrupt-parent = <&gsc>;
  50                         interrupts = <0>;
  51                 };
  52
  53                 key-erased {
  54                         label = "key-erased";
  55                         linux,code = <BTN_2>;
  56                         interrupt-parent = <&gsc>;
  57                         interrupts = <1>;
  58                 };
  59
  60                 eeprom-wp {
  61                         label = "eeprom_wp";
  62                         linux,code = <BTN_3>;
  63                         interrupt-parent = <&gsc>;
  64                         interrupts = <2>;
  65                 };
  66
  67                 tamper {
  68                         label = "tamper";
  69                         linux,code = <BTN_4>;
  70                         interrupt-parent = <&gsc>;
  71                         interrupts = <5>;
  72                 };
  73
  74                 switch-hold {
  75                         label = "switch_hold";
  76                         linux,code = <BTN_5>;
  77                         interrupt-parent = <&gsc>;
  78                         interrupts = <7>;
  79                 };
  80         };
  81
  82         leds {
  83                 compatible = "gpio-leds";
  84                 pinctrl-names = "default";
  85                 pinctrl-0 = <&pinctrl_gpio_leds>;
  86
  87                 led0: user1 {
  88                         label = "user1";
  89                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  90                         default-state = "on";
  91                         linux,default-trigger = "heartbeat";
  92                 };
  93
  94                 led1: user2 {
  95                         label = "user2";
  96                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  97                         default-state = "off";
  98                 };
  99
 100                 led2: user3 {
 101                         label = "user3";
 102                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 103                         default-state = "off";
 104                 };
 105         };
 106
 107         memory@10000000 {
 108                 device_type = "memory";
 109                 reg = <0x10000000 0x40000000>;
 110         };
 111
 112         pps {
 113                 compatible = "pps-gpio";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_pps>;
 116                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 117                 status = "okay";
 118         };
 119
 120         regulators {
 121                 compatible = "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <0>;
 124
 125                 reg_1p0v: regulator@0 {
 126                         compatible = "regulator-fixed";
 127                         reg = <0>;
 128                         regulator-name = "1P0V";
 129                         regulator-min-microvolt = <1000000>;
 130                         regulator-max-microvolt = <1000000>;
 131                         regulator-always-on;
 132                 };
 133
 134                 reg_3p3v: regulator@1 {
 135                         compatible = "regulator-fixed";
 136                         reg = <1>;
 137                         regulator-name = "3P3V";
 138                         regulator-min-microvolt = <3300000>;
 139                         regulator-max-microvolt = <3300000>;
 140                         regulator-always-on;
 141                 };
 142
 143                 reg_usb_h1_vbus: regulator@2 {
 144                         compatible = "regulator-fixed";
 145                         reg = <2>;
 146                         regulator-name = "usb_h1_vbus";
 147                         regulator-min-microvolt = <5000000>;
 148                         regulator-max-microvolt = <5000000>;
 149                         regulator-always-on;
 150                 };
 151
 152                 reg_usb_otg_vbus: regulator@3 {
 153                         compatible = "regulator-fixed";
 154                         reg = <3>;
 155                         regulator-name = "usb_otg_vbus";
 156                         regulator-min-microvolt = <5000000>;
 157                         regulator-max-microvolt = <5000000>;
 158                         gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 159                         enable-active-high;
 160                 };
 161         };
 162
 163         sound-analog {
 164                 compatible = "fsl,imx6q-ventana-sgtl5000",
 165                              "fsl,imx-audio-sgtl5000";
 166                 model = "sgtl5000-audio";
 167                 ssi-controller = <&ssi1>;
 168                 audio-codec = <&sgtl5000>;
 169                 audio-routing =
 170                         "MIC_IN", "Mic Jack",
 171                         "Mic Jack", "Mic Bias",
 172                         "Headphone Jack", "HP_OUT";
 173                 mux-int-port = <1>;
 174                 mux-ext-port = <4>;
 175         };
 176 };
 177
 178 &audmux {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
 181         status = "okay";
 182
 183         ssi2 {
 184                 fsl,audmux-port = <1>;
 185                 fsl,port-config = <
 186                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 187                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 188                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 189                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 190                         IMX_AUDMUX_V2_PTCR_SYN)
 191                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 192                 >;
 193         };
 194
 195         aud5 {
 196                 fsl,audmux-port = <4>;
 197                 fsl,port-config = <
 198                         IMX_AUDMUX_V2_PTCR_SYN
 199                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
 200         };
 201 };
 202
 203 &can1 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_flexcan1>;
 206         status = "okay";
 207 };
 208
 209 &clks {
 210         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 211                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 212         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 213                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 214 };
 215
 216 &ecspi2 {
 217         cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_ecspi2>;
 220         status = "okay";
 221 };
 222
 223 &fec {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pinctrl_enet>;
 226         phy-mode = "rgmii-id";
 227         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 228         phy-reset-duration = <10>;
 229         phy-reset-post-delay = <100>;
 230         status = "okay";
 231 };
 232
 233 &gpmi {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_gpmi_nand>;
 236         status = "okay";
 237 };
 238
 239 &hdmi {
 240         ddc-i2c-bus = <&i2c3>;
 241         status = "okay";
 242 };
 243
 244 &i2c1 {
 245         clock-frequency = <100000>;
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_i2c1>;
 248         status = "okay";
 249
 250         gsc: gsc@20 {
 251                 compatible = "gw,gsc";
 252                 reg = <0x20>;
 253                 interrupt-parent = <&gpio1>;
 254                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 255                 interrupt-controller;
 256                 #interrupt-cells = <1>;
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259
 260                 adc {
 261                         compatible = "gw,gsc-adc";
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264
 265                         channel@0 {
 266                                 gw,mode = <0>;
 267                                 reg = <0x00>;
 268                                 label = "temp";
 269                         };
 270
 271                         channel@2 {
 272                                 gw,mode = <1>;
 273                                 reg = <0x02>;
 274                                 label = "vdd_vin";
 275                         };
 276
 277                         channel@5 {
 278                                 gw,mode = <1>;
 279                                 reg = <0x05>;
 280                                 label = "vdd_3p3";
 281                         };
 282
 283                         channel@8 {
 284                                 gw,mode = <1>;
 285                                 reg = <0x08>;
 286                                 label = "vdd_bat";
 287                         };
 288
 289                         channel@b {
 290                                 gw,mode = <1>;
 291                                 reg = <0x0b>;
 292                                 label = "vdd_5p0";
 293                         };
 294
 295                         channel@e {
 296                                 gw,mode = <1>;
 297                                 reg = <0xe>;
 298                                 label = "vdd_arm";
 299                         };
 300
 301                         channel@11 {
 302                                 gw,mode = <1>;
 303                                 reg = <0x11>;
 304                                 label = "vdd_soc";
 305                         };
 306
 307                         channel@14 {
 308                                 gw,mode = <1>;
 309                                 reg = <0x14>;
 310                                 label = "vdd_3p0";
 311                         };
 312
 313                         channel@17 {
 314                                 gw,mode = <1>;
 315                                 reg = <0x17>;
 316                                 label = "vdd_1p5";
 317                         };
 318
 319                         channel@1d {
 320                                 gw,mode = <1>;
 321                                 reg = <0x1d>;
 322                                 label = "vdd_1p8";
 323                         };
 324
 325                         channel@20 {
 326                                 gw,mode = <1>;
 327                                 reg = <0x20>;
 328                                 label = "vdd_1p0";
 329                         };
 330
 331                         channel@23 {
 332                                 gw,mode = <1>;
 333                                 reg = <0x23>;
 334                                 label = "vdd_2p5";
 335                         };
 336
 337                         channel@26 {
 338                                 gw,mode = <1>;
 339                                 reg = <0x26>;
 340                                 label = "vdd_gps";
 341                         };
 342                 };
 343
 344                 fan-controller@2c {
 345                         compatible = "gw,gsc-fan";
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         reg = <0x2c>;
 349                 };
 350         };
 351
 352         gsc_gpio: gpio@23 {
 353                 compatible = "nxp,pca9555";
 354                 reg = <0x23>;
 355                 gpio-controller;
 356                 #gpio-cells = <2>;
 357                 interrupt-parent = <&gsc>;
 358                 interrupts = <4>;
 359         };
 360
 361         eeprom1: eeprom@50 {
 362                 compatible = "atmel,24c02";
 363                 reg = <0x50>;
 364                 pagesize = <16>;
 365         };
 366
 367         eeprom2: eeprom@51 {
 368                 compatible = "atmel,24c02";
 369                 reg = <0x51>;
 370                 pagesize = <16>;
 371         };
 372
 373         eeprom3: eeprom@52 {
 374                 compatible = "atmel,24c02";
 375                 reg = <0x52>;
 376                 pagesize = <16>;
 377         };
 378
 379         eeprom4: eeprom@53 {
 380                 compatible = "atmel,24c02";
 381                 reg = <0x53>;
 382                 pagesize = <16>;
 383         };
 384
 385         rtc: ds1672@68 {
 386                 compatible = "dallas,ds1672";
 387                 reg = <0x68>;
 388         };
 389 };
 390
 391 &i2c2 {
 392         clock-frequency = <100000>;
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&pinctrl_i2c2>;
 395         status = "okay";
 396
 397         pmic: pfuze100@8 {
 398                 compatible = "fsl,pfuze100";
 399                 reg = <0x08>;
 400
 401                 regulators {
 402                         sw1a_reg: sw1ab {
 403                                 regulator-min-microvolt = <300000>;
 404                                 regulator-max-microvolt = <1875000>;
 405                                 regulator-boot-on;
 406                                 regulator-always-on;
 407                                 regulator-ramp-delay = <6250>;
 408                         };
 409
 410                         sw1c_reg: sw1c {
 411                                 regulator-min-microvolt = <300000>;
 412                                 regulator-max-microvolt = <1875000>;
 413                                 regulator-boot-on;
 414                                 regulator-always-on;
 415                                 regulator-ramp-delay = <6250>;
 416                         };
 417
 418                         sw2_reg: sw2 {
 419                                 regulator-min-microvolt = <800000>;
 420                                 regulator-max-microvolt = <3950000>;
 421                                 regulator-boot-on;
 422                                 regulator-always-on;
 423                         };
 424
 425                         sw3a_reg: sw3a {
 426                                 regulator-min-microvolt = <400000>;
 427                                 regulator-max-microvolt = <1975000>;
 428                                 regulator-boot-on;
 429                                 regulator-always-on;
 430                         };
 431
 432                         sw3b_reg: sw3b {
 433                                 regulator-min-microvolt = <400000>;
 434                                 regulator-max-microvolt = <1975000>;
 435                                 regulator-boot-on;
 436                                 regulator-always-on;
 437                         };
 438
 439                         sw4_reg: sw4 {
 440                                 regulator-min-microvolt = <800000>;
 441                                 regulator-max-microvolt = <3300000>;
 442                         };
 443
 444                         swbst_reg: swbst {
 445                                 regulator-min-microvolt = <5000000>;
 446                                 regulator-max-microvolt = <5150000>;
 447                                 regulator-boot-on;
 448                                 regulator-always-on;
 449                         };
 450
 451                         snvs_reg: vsnvs {
 452                                 regulator-min-microvolt = <1000000>;
 453                                 regulator-max-microvolt = <3000000>;
 454                                 regulator-boot-on;
 455                                 regulator-always-on;
 456                         };
 457
 458                         vref_reg: vrefddr {
 459                                 regulator-boot-on;
 460                                 regulator-always-on;
 461                         };
 462
 463                         vgen1_reg: vgen1 {
 464                                 regulator-min-microvolt = <800000>;
 465                                 regulator-max-microvolt = <1550000>;
 466                         };
 467
 468                         vgen2_reg: vgen2 {
 469                                 regulator-min-microvolt = <800000>;
 470                                 regulator-max-microvolt = <1550000>;
 471                         };
 472
 473                         vgen3_reg: vgen3 {
 474                                 regulator-min-microvolt = <1800000>;
 475                                 regulator-max-microvolt = <3300000>;
 476                         };
 477
 478                         vgen4_reg: vgen4 {
 479                                 regulator-min-microvolt = <1800000>;
 480                                 regulator-max-microvolt = <3300000>;
 481                                 regulator-always-on;
 482                         };
 483
 484                         vgen5_reg: vgen5 {
 485                                 regulator-min-microvolt = <1800000>;
 486                                 regulator-max-microvolt = <3300000>;
 487                                 regulator-always-on;
 488                         };
 489
 490                         vgen6_reg: vgen6 {
 491                                 regulator-min-microvolt = <1800000>;
 492                                 regulator-max-microvolt = <3300000>;
 493                                 regulator-always-on;
 494                         };
 495                 };
 496         };
 497 };
 498
 499 &i2c3 {
 500         clock-frequency = <100000>;
 501         pinctrl-names = "default";
 502         pinctrl-0 = <&pinctrl_i2c3>;
 503         status = "okay";
 504
 505         sgtl5000: audio-codec@a {
 506                 compatible = "fsl,sgtl5000";
 507                 reg = <0x0a>;
 508                 clocks = <&clks IMX6QDL_CLK_CKO>;
 509                 VDDA-supply = <&sw4_reg>;
 510                 VDDIO-supply = <&reg_3p3v>;
 511         };
 512
 513         touchscreen: egalax_ts@4 {
 514                 compatible = "eeti,egalax_ts";
 515                 reg = <0x04>;
 516                 interrupt-parent = <&gpio7>;
 517                 interrupts = <12 2>;
 518                 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 519         };
 520
 521         accel@1e {
 522                 compatible = "nxp,fxos8700";
 523                 reg = <0x1e>;
 524         };
 525 };
 526
 527 &ldb {
 528         status = "okay";
 529
 530         lvds-channel@0 {
 531                 fsl,data-mapping = "spwg";
 532                 fsl,data-width = <18>;
 533                 status = "okay";
 534
 535                 display-timings {
 536                         native-mode = <&timing0>;
 537                         timing0: hsd100pxn1 {
 538                                 clock-frequency = <65000000>;
 539                                 hactive = <1024>;
 540                                 vactive = <768>;
 541                                 hback-porch = <220>;
 542                                 hfront-porch = <40>;
 543                                 vback-porch = <21>;
 544                                 vfront-porch = <7>;
 545                                 hsync-len = <60>;
 546                                 vsync-len = <10>;
 547                         };
 548                 };
 549         };
 550 };
 551
 552 &pcie {
 553         pinctrl-names = "default";
 554         pinctrl-0 = <&pinctrl_pcie>;
 555         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 556         status = "okay";
 557 };
 558
 559 &pwm1 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 562         status = "disabled";
 563 };
 564
 565 &pwm2 {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 568         status = "disabled";
 569 };
 570
 571 &pwm3 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 574         status = "disabled";
 575 };
 576
 577 &pwm4 {
 578         #pwm-cells = <2>;
 579         pinctrl-names = "default", "state_dio";
 580         pinctrl-0 = <&pinctrl_pwm4_backlight>;
 581         pinctrl-1 = <&pinctrl_pwm4_dio>;
 582         status = "okay";
 583 };
 584
 585 &ssi1 {
 586         status = "okay";
 587 };
 588
 589 &ssi2 {
 590         status = "okay";
 591 };
 592
 593 &uart1 {
 594         pinctrl-names = "default";
 595         pinctrl-0 = <&pinctrl_uart1>;
 596         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 597         status = "okay";
 598 };
 599
 600 &uart2 {
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&pinctrl_uart2>;
 603         status = "okay";
 604 };
 605
 606 &uart5 {
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&pinctrl_uart5>;
 609         status = "okay";
 610 };
 611
 612 &usbotg {
 613         vbus-supply = <&reg_usb_otg_vbus>;
 614         pinctrl-names = "default";
 615         pinctrl-0 = <&pinctrl_usbotg>;
 616         disable-over-current;
 617         dr_mode = "otg";
 618         status = "okay";
 619 };
 620
 621 &usbh1 {
 622         vbus-supply = <&reg_usb_h1_vbus>;
 623         status = "okay";
 624 };
 625
 626 &usdhc3 {
 627         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 628         pinctrl-0 = <&pinctrl_usdhc3>;
 629         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 630         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 631         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 632         vmmc-supply = <&reg_3p3v>;
 633         no-1-8-v; /* firmware will remove if board revision supports */
 634         status = "okay";
 635 };
 636
 637 &wdog1 {
 638         status = "disabled";
 639 };
 640
 641 &wdog2 {
 642         pinctrl-names = "default";
 643         pinctrl-0 = <&pinctrl_wdog>;
 644         fsl,ext-reset-output;
 645         status = "okay";
 646 };
 647
 648 &iomuxc {
 649         pinctrl_audmux: audmuxgrp {
 650                 fsl,pins = <
 651                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 652                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 653                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 654                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 655                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 656                         MX6QDL_PAD_EIM_D25__AUD5_RXC            0x130b0
 657                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 658                         MX6QDL_PAD_EIM_D24__AUD5_RXFS           0x130b0
 659                 >;
 660         };
 661
 662         pinctrl_enet: enetgrp {
 663                 fsl,pins = <
 664                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 665                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 666                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 667                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 668                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 669                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 670                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 671                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 672                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 673                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 674                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 675                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 676                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 677                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 678                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 679                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 680                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 681                 >;
 682         };
 683
 684         pinctrl_ecspi2: escpi2grp {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 687                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 688                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 689                         MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 690                 >;
 691         };
 692
 693         pinctrl_flexcan1: flexcan1grp {
 694                 fsl,pins = <
 695                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 696                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 697                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 698                 >;
 699         };
 700
 701         pinctrl_gpio_leds: gpioledsgrp {
 702                 fsl,pins = <
 703                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 704                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 705                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 706                 >;
 707         };
 708
 709         pinctrl_gpmi_nand: gpminandgrp {
 710                 fsl,pins = <
 711                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 712                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 713                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 714                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 715                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 716                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 717                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 718                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 719                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 720                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 721                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 722                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 723                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 724                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 725                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 726                 >;
 727         };
 728
 729         pinctrl_i2c1: i2c1grp {
 730                 fsl,pins = <
 731                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 732                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 733                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 734                 >;
 735         };
 736
 737         pinctrl_i2c2: i2c2grp {
 738                 fsl,pins = <
 739                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 740                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 741                 >;
 742         };
 743
 744         pinctrl_i2c3: i2c3grp {
 745                 fsl,pins = <
 746                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 747                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 748                 >;
 749         };
 750
 751         pinctrl_pcie: pciegrp {
 752                 fsl,pins = <
 753                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0 /* PCIE IRQ */
 754                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0 /* PCIE RST */
 755                 >;
 756         };
 757
 758         pinctrl_pps: ppsgrp {
 759                 fsl,pins = <
 760                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 761                 >;
 762         };
 763
 764         pinctrl_pwm1: pwm1grp {
 765                 fsl,pins = <
 766                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 767                 >;
 768         };
 769
 770         pinctrl_pwm2: pwm2grp {
 771                 fsl,pins = <
 772                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 773                 >;
 774         };
 775
 776         pinctrl_pwm3: pwm3grp {
 777                 fsl,pins = <
 778                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 779                 >;
 780         };
 781
 782         pinctrl_pwm4_backlight: pwm4grpbacklight {
 783                 fsl,pins = <
 784                         /* LVDS_PWM J6.5 */
 785                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 786                 >;
 787         };
 788
 789         pinctrl_pwm4_dio: pwm4grpdio {
 790                 fsl,pins = <
 791                         /* DIO3 J16.4 */
 792                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 793                 >;
 794         };
 795
 796         pinctrl_uart1: uart1grp {
 797                 fsl,pins = <
 798                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 799                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 800                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 801                 >;
 802         };
 803
 804         pinctrl_uart2: uart2grp {
 805                 fsl,pins = <
 806                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 807                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 808                 >;
 809         };
 810
 811         pinctrl_uart5: uart5grp {
 812                 fsl,pins = <
 813                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 814                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 815                 >;
 816         };
 817
 818         pinctrl_usbotg: usbotggrp {
 819                 fsl,pins = <
 820                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 821                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 822                 >;
 823         };
 824
 825         pinctrl_usdhc3: usdhc3grp {
 826                 fsl,pins = <
 827                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 828                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 829                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 830                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 831                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 832                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 833                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 834                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 835                 >;
 836         };
 837
 838         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 839                 fsl,pins = <
 840                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 841                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 842                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 843                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 844                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 845                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 846                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 847                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 848                 >;
 849         };
 850
 851         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 852                 fsl,pins = <
 853                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 854                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 855                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 856                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 857                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 858                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 859                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 860                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 861                 >;
 862         };
 863
 864         pinctrl_wdog: wdoggrp {
 865                 fsl,pins = <
 866                         MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 867                 >;
 868         };
 869 };