arch/arm/dts/imx6qdl-gw53xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         /* these are used by bootloader for disabling nodes */
  12         aliases {
  13                 led0 = &led0;
  14                 led1 = &led1;
  15                 led2 = &led2;
  16                 mmc0 = &usdhc3;
  17                 nand = &gpmi;
  18                 ssi0 = &ssi1;
  19                 usb0 = &usbh1;
  20                 usb1 = &usbotg;
  21         };
  22
  23         chosen {
  24                 bootargs = "console=ttymxc1,115200";
  25         };
  26
  27         backlight {
  28                 compatible = "pwm-backlight";
  29                 pwms = <&pwm4 0 5000000>;
  30                 brightness-levels = <0 4 8 16 32 64 128 255>;
  31                 default-brightness-level = <7>;
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 user-pb {
  40                         label = "user_pb";
  41                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  42                         linux,code = <BTN_0>;
  43                 };
  44
  45                 user-pb1x {
  46                         label = "user_pb1x";
  47                         linux,code = <BTN_1>;
  48                         interrupt-parent = <&gsc>;
  49                         interrupts = <0>;
  50                 };
  51
  52                 key-erased {
  53                         label = "key-erased";
  54                         linux,code = <BTN_2>;
  55                         interrupt-parent = <&gsc>;
  56                         interrupts = <1>;
  57                 };
  58
  59                 eeprom-wp {
  60                         label = "eeprom_wp";
  61                         linux,code = <BTN_3>;
  62                         interrupt-parent = <&gsc>;
  63                         interrupts = <2>;
  64                 };
  65
  66                 tamper {
  67                         label = "tamper";
  68                         linux,code = <BTN_4>;
  69                         interrupt-parent = <&gsc>;
  70                         interrupts = <5>;
  71                 };
  72
  73                 switch-hold {
  74                         label = "switch_hold";
  75                         linux,code = <BTN_5>;
  76                         interrupt-parent = <&gsc>;
  77                         interrupts = <7>;
  78                 };
  79         };
  80
  81         leds {
  82                 compatible = "gpio-leds";
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&pinctrl_gpio_leds>;
  85
  86                 led0: user1 {
  87                         label = "user1";
  88                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  89                         default-state = "on";
  90                         linux,default-trigger = "heartbeat";
  91                 };
  92
  93                 led1: user2 {
  94                         label = "user2";
  95                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  96                         default-state = "off";
  97                 };
  98
  99                 led2: user3 {
 100                         label = "user3";
 101                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 102                         default-state = "off";
 103                 };
 104         };
 105
 106         memory@10000000 {
 107                 device_type = "memory";
 108                 reg = <0x10000000 0x40000000>;
 109         };
 110
 111         pps {
 112                 compatible = "pps-gpio";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_pps>;
 115                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 116                 status = "okay";
 117         };
 118
 119         reg_1p0v: regulator-1p0v {
 120                 compatible = "regulator-fixed";
 121                 regulator-name = "1P0V";
 122                 regulator-min-microvolt = <1000000>;
 123                 regulator-max-microvolt = <1000000>;
 124                 regulator-always-on;
 125         };
 126
 127         reg_3p3v: regulator-3p3v {
 128                 compatible = "regulator-fixed";
 129                 regulator-name = "3P3V";
 130                 regulator-min-microvolt = <3300000>;
 131                 regulator-max-microvolt = <3300000>;
 132                 regulator-always-on;
 133         };
 134
 135         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 136                 compatible = "regulator-fixed";
 137                 regulator-name = "usb_h1_vbus";
 138                 regulator-min-microvolt = <5000000>;
 139                 regulator-max-microvolt = <5000000>;
 140                 regulator-always-on;
 141         };
 142
 143         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 144                 compatible = "regulator-fixed";
 145                 regulator-name = "usb_otg_vbus";
 146                 regulator-min-microvolt = <5000000>;
 147                 regulator-max-microvolt = <5000000>;
 148                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 149                 enable-active-high;
 150         };
 151
 152         sound {
 153                 compatible = "fsl,imx6q-ventana-sgtl5000",
 154                              "fsl,imx-audio-sgtl5000";
 155                 model = "sgtl5000-audio";
 156                 ssi-controller = <&ssi1>;
 157                 audio-codec = <&codec>;
 158                 audio-routing =
 159                         "MIC_IN", "Mic Jack",
 160                         "Mic Jack", "Mic Bias",
 161                         "Headphone Jack", "HP_OUT";
 162                 mux-int-port = <1>;
 163                 mux-ext-port = <4>;
 164         };
 165 };
 166
 167 &audmux {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_audmux>;
 170         status = "okay";
 171 };
 172
 173 &can1 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_flexcan1>;
 176         status = "okay";
 177 };
 178
 179 &clks {
 180         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 181                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 182         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 183                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 184 };
 185
 186 &fec {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_enet>;
 189         phy-mode = "rgmii-id";
 190         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 191         phy-reset-duration = <10>;
 192         phy-reset-post-delay = <100>;
 193         status = "okay";
 194 };
 195
 196 &gpmi {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_gpmi_nand>;
 199         status = "okay";
 200 };
 201
 202 &hdmi {
 203         ddc-i2c-bus = <&i2c3>;
 204         status = "okay";
 205 };
 206
 207 &i2c1 {
 208         clock-frequency = <100000>;
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_i2c1>;
 211         status = "okay";
 212
 213         gsc: gsc@20 {
 214                 compatible = "gw,gsc";
 215                 reg = <0x20>;
 216                 interrupt-parent = <&gpio1>;
 217                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 218                 interrupt-controller;
 219                 #interrupt-cells = <1>;
 220                 #size-cells = <0>;
 221
 222                 adc {
 223                         compatible = "gw,gsc-adc";
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226
 227                         channel@0 {
 228                                 gw,mode = <0>;
 229                                 reg = <0x00>;
 230                                 label = "temp";
 231                         };
 232
 233                         channel@2 {
 234                                 gw,mode = <1>;
 235                                 reg = <0x02>;
 236                                 label = "vdd_vin";
 237                         };
 238
 239                         channel@5 {
 240                                 gw,mode = <1>;
 241                                 reg = <0x05>;
 242                                 label = "vdd_3p3";
 243                         };
 244
 245                         channel@8 {
 246                                 gw,mode = <1>;
 247                                 reg = <0x08>;
 248                                 label = "vdd_bat";
 249                         };
 250
 251                         channel@b {
 252                                 gw,mode = <1>;
 253                                 reg = <0x0b>;
 254                                 label = "vdd_5p0";
 255                         };
 256
 257                         channel@e {
 258                                 gw,mode = <1>;
 259                                 reg = <0xe>;
 260                                 label = "vdd_arm";
 261                         };
 262
 263                         channel@11 {
 264                                 gw,mode = <1>;
 265                                 reg = <0x11>;
 266                                 label = "vdd_soc";
 267                         };
 268
 269                         channel@14 {
 270                                 gw,mode = <1>;
 271                                 reg = <0x14>;
 272                                 label = "vdd_3p0";
 273                         };
 274
 275                         channel@17 {
 276                                 gw,mode = <1>;
 277                                 reg = <0x17>;
 278                                 label = "vdd_1p5";
 279                         };
 280
 281                         channel@1d {
 282                                 gw,mode = <1>;
 283                                 reg = <0x1d>;
 284                                 label = "vdd_1p8";
 285                         };
 286
 287                         channel@20 {
 288                                 gw,mode = <1>;
 289                                 reg = <0x20>;
 290                                 label = "vdd_1p0";
 291                         };
 292
 293                         channel@23 {
 294                                 gw,mode = <1>;
 295                                 reg = <0x23>;
 296                                 label = "vdd_2p5";
 297                         };
 298
 299                         channel@26 {
 300                                 gw,mode = <1>;
 301                                 reg = <0x26>;
 302                                 label = "vdd_gps";
 303                         };
 304
 305                         channel@29 {
 306                                 gw,mode = <1>;
 307                                 reg = <0x29>;
 308                                 label = "vdd_an1";
 309                         };
 310                 };
 311         };
 312
 313         gsc_gpio: gpio@23 {
 314                 compatible = "nxp,pca9555";
 315                 reg = <0x23>;
 316                 gpio-controller;
 317                 #gpio-cells = <2>;
 318                 interrupt-parent = <&gsc>;
 319                 interrupts = <4>;
 320         };
 321
 322         eeprom1: eeprom@50 {
 323                 compatible = "atmel,24c02";
 324                 reg = <0x50>;
 325                 pagesize = <16>;
 326         };
 327
 328         eeprom2: eeprom@51 {
 329                 compatible = "atmel,24c02";
 330                 reg = <0x51>;
 331                 pagesize = <16>;
 332         };
 333
 334         eeprom3: eeprom@52 {
 335                 compatible = "atmel,24c02";
 336                 reg = <0x52>;
 337                 pagesize = <16>;
 338         };
 339
 340         eeprom4: eeprom@53 {
 341                 compatible = "atmel,24c02";
 342                 reg = <0x53>;
 343                 pagesize = <16>;
 344         };
 345
 346         rtc: ds1672@68 {
 347                 compatible = "dallas,ds1672";
 348                 reg = <0x68>;
 349         };
 350 };
 351
 352 &i2c2 {
 353         clock-frequency = <100000>;
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_i2c2>;
 356         status = "okay";
 357
 358         ltc3676: pmic@3c {
 359                 compatible = "lltc,ltc3676";
 360                 reg = <0x3c>;
 361                 interrupt-parent = <&gpio1>;
 362                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 363
 364                 regulators {
 365                         /* VDD_SOC (1+R1/R2 = 1.635) */
 366                         reg_vdd_soc: sw1 {
 367                                 regulator-name = "vddsoc";
 368                                 regulator-min-microvolt = <674400>;
 369                                 regulator-max-microvolt = <1308000>;
 370                                 lltc,fb-voltage-divider = <127000 200000>;
 371                                 regulator-ramp-delay = <7000>;
 372                                 regulator-boot-on;
 373                                 regulator-always-on;
 374                         };
 375
 376                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 377                         reg_1p8v: sw2 {
 378                                 regulator-name = "vdd1p8";
 379                                 regulator-min-microvolt = <1033310>;
 380                                 regulator-max-microvolt = <2004000>;
 381                                 lltc,fb-voltage-divider = <301000 200000>;
 382                                 regulator-ramp-delay = <7000>;
 383                                 regulator-boot-on;
 384                                 regulator-always-on;
 385                         };
 386
 387                         /* VDD_ARM (1+R1/R2 = 1.635) */
 388                         reg_vdd_arm: sw3 {
 389                                 regulator-name = "vddarm";
 390                                 regulator-min-microvolt = <674400>;
 391                                 regulator-max-microvolt = <1308000>;
 392                                 lltc,fb-voltage-divider = <127000 200000>;
 393                                 regulator-ramp-delay = <7000>;
 394                                 regulator-boot-on;
 395                                 regulator-always-on;
 396                         };
 397
 398                         /* VDD_DDR (1+R1/R2 = 2.105) */
 399                         reg_vdd_ddr: sw4 {
 400                                 regulator-name = "vddddr";
 401                                 regulator-min-microvolt = <868310>;
 402                                 regulator-max-microvolt = <1684000>;
 403                                 lltc,fb-voltage-divider = <221000 200000>;
 404                                 regulator-ramp-delay = <7000>;
 405                                 regulator-boot-on;
 406                                 regulator-always-on;
 407                         };
 408
 409                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 410                         reg_2p5v: ldo2 {
 411                                 regulator-name = "vdd2p5";
 412                                 regulator-min-microvolt = <2490375>;
 413                                 regulator-max-microvolt = <2490375>;
 414                                 lltc,fb-voltage-divider = <487000 200000>;
 415                                 regulator-boot-on;
 416                                 regulator-always-on;
 417                         };
 418
 419                         /* VDD_AUD_1P8: Audio codec */
 420                         reg_aud_1p8v: ldo3 {
 421                                 regulator-name = "vdd1p8a";
 422                                 regulator-min-microvolt = <1800000>;
 423                                 regulator-max-microvolt = <1800000>;
 424                                 regulator-boot-on;
 425                         };
 426
 427                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 428                         reg_3p0v: ldo4 {
 429                                 regulator-name = "vdd3p0";
 430                                 regulator-min-microvolt = <3023250>;
 431                                 regulator-max-microvolt = <3023250>;
 432                                 lltc,fb-voltage-divider = <634000 200000>;
 433                                 regulator-boot-on;
 434                                 regulator-always-on;
 435                         };
 436                 };
 437         };
 438 };
 439
 440 &i2c3 {
 441         clock-frequency = <100000>;
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_i2c3>;
 444         status = "okay";
 445
 446         codec: sgtl5000@a {
 447                 compatible = "fsl,sgtl5000";
 448                 reg = <0x0a>;
 449                 clocks = <&clks IMX6QDL_CLK_CKO>;
 450                 VDDA-supply = <&reg_1p8v>;
 451                 VDDIO-supply = <&reg_3p3v>;
 452         };
 453
 454         touchscreen: egalax_ts@4 {
 455                 compatible = "eeti,egalax_ts";
 456                 reg = <0x04>;
 457                 interrupt-parent = <&gpio1>;
 458                 interrupts = <11 2>;
 459                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 460         };
 461
 462         accel@1e {
 463                 compatible = "nxp,fxos8700";
 464                 reg = <0x1e>;
 465         };
 466 };
 467
 468 &ldb {
 469         status = "okay";
 470
 471         lvds-channel@0 {
 472                 fsl,data-mapping = "spwg";
 473                 fsl,data-width = <18>;
 474                 status = "okay";
 475
 476                 display-timings {
 477                         native-mode = <&timing0>;
 478                         timing0: hsd100pxn1 {
 479                                 clock-frequency = <65000000>;
 480                                 hactive = <1024>;
 481                                 vactive = <768>;
 482                                 hback-porch = <220>;
 483                                 hfront-porch = <40>;
 484                                 vback-porch = <21>;
 485                                 vfront-porch = <7>;
 486                                 hsync-len = <60>;
 487                                 vsync-len = <10>;
 488                         };
 489                 };
 490         };
 491 };
 492
 493 &pcie {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&pinctrl_pcie>;
 496         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 497         status = "okay";
 498 };
 499
 500 &pwm2 {
 501         pinctrl-names = "default";
 502         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 503         status = "disabled";
 504 };
 505
 506 &pwm3 {
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 509         status = "disabled";
 510 };
 511
 512 &pwm4 {
 513         #pwm-cells = <2>;
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&pinctrl_pwm4>;
 516         status = "okay";
 517 };
 518
 519 &ssi1 {
 520         status = "okay";
 521 };
 522
 523 &uart1 {
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pinctrl_uart1>;
 526         rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 527         status = "okay";
 528 };
 529
 530 &uart2 {
 531         pinctrl-names = "default";
 532         pinctrl-0 = <&pinctrl_uart2>;
 533         status = "okay";
 534 };
 535
 536 &uart5 {
 537         pinctrl-names = "default";
 538         pinctrl-0 = <&pinctrl_uart5>;
 539         status = "okay";
 540 };
 541
 542 &usbotg {
 543         vbus-supply = <&reg_usb_otg_vbus>;
 544         pinctrl-names = "default";
 545         pinctrl-0 = <&pinctrl_usbotg>;
 546         disable-over-current;
 547         dr_mode = "otg";
 548         status = "okay";
 549 };
 550
 551 &usbh1 {
 552         vbus-supply = <&reg_usb_h1_vbus>;
 553         status = "okay";
 554 };
 555
 556 &usdhc3 {
 557         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 558         pinctrl-0 = <&pinctrl_usdhc3>;
 559         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 560         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 561         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 562         vmmc-supply = <&reg_3p3v>;
 563         no-1-8-v; /* firmware will remove if board revision supports */
 564         status = "okay";
 565 };
 566
 567 &wdog1 {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&pinctrl_wdog>;
 570         fsl,ext-reset-output;
 571 };
 572
 573 &iomuxc {
 574         pinctrl_audmux: audmuxgrp {
 575                 fsl,pins = <
 576                         MX6QDL_PAD_SD2_DAT0__AUD4_RXD           0x130b0
 577                         MX6QDL_PAD_SD2_DAT3__AUD4_TXC           0x130b0
 578                         MX6QDL_PAD_SD2_DAT2__AUD4_TXD           0x110b0
 579                         MX6QDL_PAD_SD2_DAT1__AUD4_TXFS          0x130b0
 580                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* AUD4_MCK */
 581                 >;
 582         };
 583
 584         pinctrl_enet: enetgrp {
 585                 fsl,pins = <
 586                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 587                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 588                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 589                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 590                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 591                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 592                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 593                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 594                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 595                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 596                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 597                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 598                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 599                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 600                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 601                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 602                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 603                 >;
 604         };
 605
 606         pinctrl_flexcan1: flexcan1grp {
 607                 fsl,pins = <
 608                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 609                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 610                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0 /* CAN_STBY */
 611                 >;
 612         };
 613
 614         pinctrl_gpio_leds: gpioledsgrp {
 615                 fsl,pins = <
 616                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06   0x1b0b0
 617                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 618                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15   0x1b0b0
 619                 >;
 620         };
 621
 622         pinctrl_gpmi_nand: gpminandgrp {
 623                 fsl,pins = <
 624                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 625                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 626                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 627                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 628                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 629                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 630                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 631                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 632                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 633                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 634                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 635                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 636                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 637                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 638                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 639                 >;
 640         };
 641
 642         pinctrl_i2c1: i2c1grp {
 643                 fsl,pins = <
 644                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 645                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 646                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 647                 >;
 648         };
 649
 650         pinctrl_i2c2: i2c2grp {
 651                 fsl,pins = <
 652                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 653                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 654                 >;
 655         };
 656
 657         pinctrl_i2c3: i2c3grp {
 658                 fsl,pins = <
 659                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 660                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 661                 >;
 662         };
 663
 664         pinctrl_pcie: pciegrp {
 665                 fsl,pins = <
 666                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
 667                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29  0x1b0b0 /* PCIE RST */
 668                 >;
 669         };
 670
 671         pinctrl_pmic: pmicgrp {
 672                 fsl,pins = <
 673                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 674                 >;
 675         };
 676
 677         pinctrl_pps: ppsgrp {
 678                 fsl,pins = <
 679                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 680                 >;
 681         };
 682
 683         pinctrl_pwm2: pwm2grp {
 684                 fsl,pins = <
 685                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 686                 >;
 687         };
 688
 689         pinctrl_pwm3: pwm3grp {
 690                 fsl,pins = <
 691                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 692                 >;
 693         };
 694
 695         pinctrl_pwm4: pwm4grp {
 696                 fsl,pins = <
 697                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 698                 >;
 699         };
 700
 701         pinctrl_uart1: uart1grp {
 702                 fsl,pins = <
 703                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 704                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 705                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x4001b0b1 /* TEN */
 706                 >;
 707         };
 708
 709         pinctrl_uart2: uart2grp {
 710                 fsl,pins = <
 711                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 712                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 713                 >;
 714         };
 715
 716         pinctrl_uart5: uart5grp {
 717                 fsl,pins = <
 718                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 719                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 720                 >;
 721         };
 722
 723         pinctrl_usbotg: usbotggrp {
 724                 fsl,pins = <
 725                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 726                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 727                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 728                 >;
 729         };
 730
 731         pinctrl_usdhc3: usdhc3grp {
 732                 fsl,pins = <
 733                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 734                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 735                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 736                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 737                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 738                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 739                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 740                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 741                 >;
 742         };
 743
 744         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 745                 fsl,pins = <
 746                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 747                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 748                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 749                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 750                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 751                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 752                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 753                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 754                 >;
 755         };
 756
 757         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 758                 fsl,pins = <
 759                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 760                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 761                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 762                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 763                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 764                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 765                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 766                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 767                 >;
 768         };
 769
 770         pinctrl_wdog: wdoggrp {
 771                 fsl,pins = <
 772                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 773                 >;
 774         };
 775 };